KR100557622B1 - semiconductor memory device setup/hold time tunning circuit - Google Patents

Abstract

The present invention relates to a setup / hold time control circuit of a semiconductor memory device, and more particularly, a technique for optimizing setup / hold time by controlling a delay option using a test mode code when testing a packaged product. to be. To this end, the present invention provides a plurality of controls for controlling the delay amount of an input buffer unit for buffering and outputting address, command, and data information input from the outside, and the setup / hold time delay option unit by performing logical operation on an address signal in a test mode. A control unit for outputting a signal, a setup / hold time delay option unit controlled by the plurality of control signals to adjust a setup / hold time delay amount of the output of the input buffer unit, and an output of the setup / hold time delay option unit. And a latch unit configured to latch in synchronization with the internal clock signal.

Description

Semiconductor memory device setup / hold time tunning circuit

1 is a block diagram of a setup / hold time control circuit of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of the setup / hold delay unit of FIG. 1. FIG.

3 is a block diagram of a setup / hold time control circuit of a semiconductor memory device according to an embodiment of the present invention.

4 is a detailed circuit diagram of the setup / hold delay unit of FIG. 3.

5A and 5B are detailed circuit diagrams of the controller of FIG. 3.

The present invention relates to a setup / hold time control circuit of a semiconductor memory device, and more particularly, a technique for optimizing setup / hold time by controlling a delay option using a test mode code when testing a packaged product. to be.

In a semiconductor memory device, a setup / hold time is given when an address, command, or data is input. When the signals such as address, command, or data are input, the signals must be inputted before a certain time on the basis of the external clock signal, so that the signals are stably latched, and the signals must be held for a predetermined time on the basis of the external clock signal. It is recognized correctly.

In this case, a time for which the signals are applied before a predetermined time based on the external clock signal is called a setup time, and a time when the signals are maintained for a predetermined time based on the external clock signal is called a hold time.

This setup / hold time is a race between a reference signal such as a clock and a delayed signal inside a semiconductor memory device such as an address, command or data. It is inevitable to implement an optional delay that allows the asynchronous signals to be pushed and pulled in the +/- directions, respectively.

It is very important to adjust this setup / hold time delay amount to match the actual setup / hold delay amount on the wafer.

1 is a block diagram of a setup / hold time control circuit of a semiconductor memory device according to an embodiment of the present invention.

The setup / hold time control circuit of a conventional semiconductor memory device is composed of an input buffer section 1, a setup / hold time delay option section 2, and a latch section 3.

The input buffer unit 1 converts and outputs address information, command information, and data information input from the outside into signals usable internally.

The setup / hold time delay option unit 2 receives the output of the input buffer unit 1 and adjusts the setup / hold value to the specification in consideration of process variation, power supply noise, and line loading according to the circuit layout. do.

The latch section 3 latches the address information, command information, and data information passed through the setup / hold time delay option section 2 in synchronization with the internal clock ICLK.

FIG. 2 is a detailed circuit diagram of the setup / hold time delay option unit 2 of FIG. 1.

The conventional setup / hold time delay option unit 2 is composed of delay units 11, 12, 13 and metal options M1 to M4. Each of the delay units 11, 12, and 13 includes capacitors C1 to C6 and metal options M5 to M10 in a delay circuit composed of a plurality of inverters I1 to I6, so that the input signal SIN is capacitors C1 to C6 and metal options M5. To an output signal SOUT by delaying the setup / hold time option delay determined by M10.

In FIG. 2, the metal options M1, M3, and M4 are turned off, and only the metal options M2 are connected to output a delayed signal through the delay unit 11.

This conventional setup / hold time control circuit cuts metal options M1 to M10 through a focused ion beam (FIB) experiment on a packaged sample when the setup / hold time delay amount and the actual setup / hold delay amount on the wafer do not match. To adjust the amount of delay desired.

However, the setup / hold time tuning method using such FIB equipment is often difficult when there are two metal layers. In other words, the metal layer on the upper layer among the two metal layers has no free space due to the metal line wiring, so the metal option is often formed on the metal layer on the lower layer. Is difficult. Therefore, in this case, there is a problem in that data obtained by simulation based on experimental results is used, and an incorrect setup / hold time delay value is applied.

An object of the present invention to solve the above problems is to control the actual setup / hold time delay option by using the code of the test mode when testing the packaged product, more accurate setup / hold by reflecting the actual wafer characteristics as it is To provide a time delay option.

The present invention for achieving the above object to control the delay amount of the input buffer unit for buffering and outputting the address, command, data information input from the outside and the setup / hold time delay option unit by performing a logical operation on the address signal in the test mode A control unit for outputting a plurality of control signals for;

A setup / hold time delay option unit which is controlled by the plurality of control signals to adjust the setup / hold time delay amount of the output of the input buffer unit, and latches the output of the setup / hold time delay option unit in synchronization with an internal clock signal. Characterized in that it comprises a latch portion to be configured.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a setup / hold time control circuit of a semiconductor memory device according to an embodiment of the present invention.

The setup / hold time control circuit of the semiconductor memory device includes an input buffer unit 10, a setup / hold time delay option unit 20, a latch unit 30, and a controller 40.

The input buffer unit 10 changes and outputs address information, command information, and data information input from the outside into signals that can be used therein. Here, the input buffer unit 10 may be implemented as a static or dynamic type buffer.

The setup / hold time delay option unit 20 receives the output of the input buffer unit 10 and adjusts the setup / hold value to a specification in consideration of process variation, power supply noise, and line loading according to the circuit layout. Tune the setup / hold time.

The latch unit 30 latches the address information, command information, and data information passed through the setup / hold time delay option unit 20 in synchronization with the internal clock ICLK.

The control unit 40 controls control signals OUT <0: 3>, OUTB <0: 3>, CTOUT <0: 5>, and CTOUTB <0: 5 for controlling the tuning operation of the setup / hold time delay option unit 20. Output> Here, the control signals OUT <0: 3>, OUTB <0: 3>, CTOUT <0: 5>, and CTOUTB <0: 5> are input signals INO, IN1, and CTRL0 to addresses that are used after entering the test mode. Generated using CTRL5.

4 is a detailed circuit diagram of the setup / hold time delay option unit 20 of FIG. 3.

The setup / hold time delay option unit 20 includes delay units 21, 22, and 23 and transmission gates T1 to T4.

Each of the delay units 21, 22, and 23 includes capacitors C7 to C12 and transfer gates T5 to T10 in a delay circuit composed of a plurality of inverters I7 to I12, so that the input signal SIN is capacitors C7 to C12 and transfer gate T5. To delay the setup / hold time option delay determined by T10 to provide the output signal SOUT.

And a transfer gate T5 and T6 for controlling the on / off of the capacitors C7 and C8 and the capacitors C7 and C8 to which a power supply voltage is applied, centered on a common node between the inverters I7 and I8 connected in series of the delay unit 21, respectively. Since the configurations of the delay units 22 and 23 are the same as those of the delay unit 21, a detailed description thereof will be omitted.

The transfer gates T1 to T4 control whether or not the outputs of the delay units 21, 22, and 23 are transmitted. That is, when only the transmission gate T1 is turned on, the input signal SIN is directly output without being delayed. When only the transmission gate T2 is turned on, the input signal SIN is outputted through the delay unit 21. ), And when only the transmission gate T4 is turned on, it outputs through all of the delay units 21, 22, and 23.

The transfer gates T5 to T10 are controlled by control signals CTOUT0 to CTOUT5 and CTOUTB0 to CTOUTB5, respectively, to control the total delay time by controlling the on / off of each capacitor C7 to C12.

Although FIG. 4 illustrates an example of implementing only a capacitor and a transfer gate controlling on / off of the capacitor, a delay amount may be adjusted by adding a resistor between the capacitor and the transfer gate as necessary.

5A and 5B are detailed circuit diagrams of the controller 40 of FIG. 3.

The controller 40 includes a first control signal generator 41 of FIG. 5A and a second control signal generator 42 of FIG. 5B. That is, FIG. 5A is a circuit for generating control signals OUT <0: 3> and OUTB <0: 3> for controlling the transfer gates T1 to T4, and FIG. 5B is a control signal CTOUT for controlling the transfer gates T5 to T10. This circuit generates <0: 5> and CTOUTB <0: 5>.

As shown in Fig. 5A, the first control signal generator 41 is composed of inverters I13 to I18 and NAND gates NAND1 to NAND4, and decodes the input signals IN0 and IN1 to output signals OUT <0: 3> and OUTB. Outputs <0: 3>.

As shown in Fig. 5B, the second control signal generator 42 is composed of inverters I19 and I20, and receives the input signals CTRL0 to CRTL5 to output the output signals CTOUT <0: 5> and CTOUTB <0: 5>. Output

As described above, the setup / hold time control circuit of the semiconductor memory device according to the present invention provides the amount of delay close to the actual value without the FIB experiment when the setup / hold time delay amount and the setup / hold delay amount on the actual wafer do not match. This allows you to easily see the optimized delay through the test.

As described above, the present invention controls the actual setup / hold time delay option by using the test mode code when testing the packaged product, so that the accurate setup / hold time delay option is reflected by reflecting the actual wafer characteristics. There is an effect that can be provided.                     

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (6)

An input buffer unit for buffering and outputting address, command, and data information input from the outside; A control unit for outputting a plurality of control signals for controlling the delay amount of the setup / hold time delay option unit by performing a logical operation on the address signal in the test mode; A setup / hold time delay option unit controlled by the plurality of control signals to adjust a setup / hold time delay amount of the output of the input buffer unit; And A latch unit for latching an output of the setup / hold time delay option unit in synchronization with an internal clock signal; The setup / hold time control circuit of a semiconductor memory device, characterized in that comprising a. The method of claim 1, wherein the control unit, A first control signal generator for decoding the address signal and outputting a first control signal among the plurality of control signals; And A second control signal generator for delaying or inverting the address signal to output a second control signal among the plurality of control signals; And a setup / hold time control circuit of a semiconductor memory device. The method of claim 1, wherein the first control signal generator, First and second inverting means for inverting the address signal output from the test mode, respectively; A plurality of NAND gates that NAND gate the outputs of the first and second inverting means, respectively; And A plurality of third inverting means for inverting and outputting the outputs of the plurality of NAND gates; And a setup / hold time control circuit of the semiconductor memory device. The method of claim 1, wherein the second control signal generator, First inverting means for inverting and outputting the address signal output from the test mode; And Second inverting means for inverting and outputting the output of the first inverting means And a setup / hold time control circuit of the semiconductor memory device. The method of claim 1, wherein the setup / hold time delay option unit, First, second, and third delay units for controlling a delay amount according to a second control signal of the plurality of control signals to delay an input signal according to the delay amount; And The plurality of transmission gates provided at respective input terminals of the first, second, and third delay units and output terminals of the third delay unit, respectively, and controlled by a first control signal of the plurality of control signals to determine an output pass; And a setup / hold time control circuit of a semiconductor memory device. The method of claim 5, wherein the first, second, and third delay unit, First and second inverting means connected in series to delay and output the input signal; A first capacitor to which a power supply voltage is applied; A first transmission gate connected to an output terminal of the first inverting means and controlled by the second control signal to control on / off of the first capacitor; A second capacitor to which a ground voltage is applied; And A second transmission gate connected to an output terminal of the first inverting means and controlled by the second control signal to control on / off of the second capacitor And a setup / hold time control circuit of a semiconductor memory device.

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