KR100546804B1 - A Manufacturing Method of Layer Insulation Film of Semiconductor Element - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an interlayer insulating film of a semiconductor device, wherein voids generated during deposition of a BPSG film used as an interlayer insulating film between a gate electrode and a metal line when the aspect ratio between gate electrodes of a semiconductor device is large. The present invention relates to a method for manufacturing an interlayer insulating film of a semiconductor device capable of improving the yield of the semiconductor device by removing voids.

The manufacturing method according to the present invention comprises the steps of forming a gate electrode and a sidewall spacer on its side on a semiconductor substrate; Depositing an etch stop layer on the entire surface of the semiconductor substrate by omitting a source / drain annealing process after source / drain ion implantation with the gate electrode and sidewall spacers and depositing and annealing a primary BPSG film on the etch stop layer And depositing and annealing the secondary BPSG film on the primary BPSG film, and then performing CMP for planarization.

In the present invention, the BPSG film deposition process is performed twice in the case of depositing the BPSG film, which is an interlayer insulating film between the gate electrode and the metal line, but in the prior art, the source / drain annealing process performed just before the deposition of the etch stop film is performed on the first BPSG film deposition Immediately proceeds to serve as both BPSG annealing and source / drain annealing, and BPSG flow is improved by the effect of relatively high temperature source / drain annealing process. At this time, the flow effect is improved by thinly depositing the thickness of the first BPSG film. After the growth of the primary BPSG film, the slit voids formed between the gate electrodes can be completely removed, as well as the source / drain annealing in the state where the thickness of the BPSG film is thin. In other words, the same characteristics as the source / drain annealing performed before the deposition of the etch stop film can be achieved. You can remove the void without any change in the.

Semiconductor, Device, Substrate, Interlayer, Insulating Film, BPSG, Etching, Annealing, Slit, Void

Description

A manufacturing method of layer insulation film of semiconductor element

1A to 1C are cross-sectional views illustrating a method of manufacturing an interlayer insulating film according to the related art.

2A through 2E are cross-sectional views illustrating a method of manufacturing an interlayer insulating film of an egg salicide semiconductor device according to an exemplary embodiment of the present invention.

 Explanation of symbols on the main parts of the drawings

100: semiconductor substrate

102: gate electrode

104: sidewall spacer

106: etching stop film

108: primary BPSG interlayer insulating film (before annealing)

108a: primary BPSG interlayer insulating film (after annealing)

110: secondary BPSG interlayer insulating film

The present invention relates to a method for manufacturing an interlayer insulating film of a semiconductor device, and more particularly, to deposit a BPSG film used as an interlayer insulating film between a gate electrode and a metal line when the aspect ratio between gate electrodes of a semiconductor device is large. The present invention relates to a method for manufacturing an interlayer insulating film of a semiconductor device capable of improving the yield of a semiconductor device by removing voids generated at the time.

In general, as semiconductor devices are highly integrated, not only the width of the wiring but also the distance between the wiring and the wiring tends to decrease significantly. Therefore, there is a tendency that the width of the gate length and the distance between the gate electrodes are further narrowed. This makes it difficult to obtain good embedding between the gate electrodes when using a conventional silicon oxide film as an interlayer insulating film. Alternatively, USG (HDP-USG: BPSG) film or a high density plasma CVD method can be obtained. High Density Plasma-CVD-Undoped Silicate Glass) film is used.

The BPSG film has a high etching selectivity with a silicon nitride film covering the gate electrode and serving as an etching stopper when forming the contact hole. The BPSG film has high fluidity and is an interlayer insulating film between the gate electrode and the metal line. It is used a lot.

Even when the BPSG film has excellent gap fill characteristics (hole filling characteristics), so-called slit voids are generated at the time of growth when filling between the gate electrodes having a narrow width. In particular, when the aspect ratio between the gate electrodes is large, it becomes more deep. When forming contact holes between the gate electrodes, bridges are generated between adjacent contact holes by the slit voids, which lowers the yield of semiconductor devices. It is necessary to dissipate the slit void by performing melting, reflowing and annealing on the BPSG film.

Melting, reflowing, and annealing processes of the BPSG film require high temperature conditions of at least 700 ° C., usually 800 ° C. or higher, and the higher the aspect ratio between the gate electrodes, the higher the temperature annealing process is required to remove the slit voids. However, at high temperatures, the probability of out-diffusion of boron (B) increases and changes in the transistors such as changes in the profile of source / drain junctions cause problems in device characteristics. In the case of a semiconductor device to which a salicide process is applied, a salicide formed on a source / drain junction may be deeper into the junction, causing a junction leakage current.

Therefore, BPSG annealing is generally performed at 700 ° C. without exceeding 700 ° C. or more in the BPSG annealing process in consideration of all the problems in the high temperature annealing mentioned above.

The 700 ° C. temperature is a temperature that has been commonly used for a long time, and is similarly applied to a salicide process application device as well as a semiconductor device to which an non-salicide process is applied.

 1A to 1C are diagrams sequentially illustrating a process of manufacturing an interlayer insulating film of a semiconductor device according to the prior art. Looking at the conventional interlayer insulating film manufacturing process with reference to these drawings as follows.

 First, as shown in FIG. 1A, a field oxide film is formed on a silicon substrate as a semiconductor substrate 10 by a shallow trench isolation (STI) process, and a gate oxide film (not shown) is formed on an active region of the semiconductor substrate 10. Form. Then, a doped poly silicon is deposited as a conductive layer on the gate oxide layer, and the doped polysilicon layer is patterned by a photolithography and an etching process using a gate mask to form a gate electrode 12. The gate oxide film is also patterned.

 Although not shown in the drawings, a LDD (Lightly Doped Drain) ion implantation process is performed to form an LDD region in the semiconductor substrate 10 exposed by the gate electrode 12. Subsequently, a silicon nitride film is deposited as an insulating thin film on the entire surface of the semiconductor substrate, and dry etching is performed to form the gate electrode 12 and the sidewall spacers 14. Then, although not shown in the figure, the gate electrode 12 and the sidewall spacer 14 are used as a mask to perform a source / drain ion implantation process to form a source / drain region in the semiconductor substrate 10 to form a gate electrode. (12) A semiconductor element of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source / drain region is manufactured.

Next, as shown in FIG. 1B, the etch stop layer 16 is manufactured.

This etch stop film 16 serves as a safe contact hole etching control as an etch stopper during contact hole etching, and also prevents diffusion of boron (B) or phosphorus (P) dopants from the BPSG film into the semiconductor substrate. Done.

Therefore, it is advantageous to use a silicon nitride film as the etch stop film 16 rather than a silicon oxide film. An etch stop layer 16 thinly deposited is formed on the entire upper surface of the semiconductor substrate 10.

At this time, when the silicon nitride film is used as the etch stop film 16, the thickness thereof is appropriately about 350 kPa.

Subsequently, as shown in FIG. 1C, the BPSG is deposited as an interlayer insulating film 18 on the upper surface of the etch stop layer 16, and the surface of the BPSG film 18 is planarized by a chemical mechanical polishing (CMP) process.

 By the way, even if the gap fill characteristics of the BPSG in the interlayer insulating film manufacturing process of the semiconductor device according to the prior art as described above, the aspect ratio between the gate electrode increases according to the trend of high integration of the semiconductor device, in this case When slit voids 20 are generated between the gate electrodes during the growth of the BPSG film to form contact holes between the gate electrodes, a bridge is generated between the adjacent contact holes by the slit voids 20 and the semiconductor is formed. The problem of lowering the yield of the device is caused.

Accordingly, the present invention has been invented to solve the above problems, and an object of the present invention is to deposit a BPSG film twice, first and second times when forming an interlayer insulating film of a semiconductor device, and perform annealing on each, The source / drain annealing process, which is relatively hotter than the BPSG annealing temperature, is carried out after the deposition of the primary BPSG film, which is much thinner than the secondary BPSG film, to remove the slit void, and then to deposit the secondary BPSG film thickly and to perform the general BPSG annealing process. The present invention provides a method for manufacturing an interlayer insulating film of a semiconductor device capable of removing slit voids as a result.

In order to achieve the above object, in the present invention, forming a gate electrode and a sidewall spacer on the side of the semiconductor substrate and etching the source / drain ion on the entire surface of the semiconductor substrate after the source / drain ions are implanted in the state where the gate electrode and the sidewall spacer are present And depositing and annealing a first BPSG film on the etch stop film, and depositing and annealing a second BPSG film on the first BPSG film, and then performing a CMP for planarization. do.

The sidewall spacer is a silicon nitride film, and the etch stop film is a silicon nitride film.

In addition, the thickness of the primary BPSG film is 500 kPa to 2,000 kPa.

In addition, the present invention also provides a manufacturing method of proceeding after the deposition of the first BPSG film under the same conditions of the source / drain annealing proceeded before the etch stop film deposition.

In the present invention, as the etch stop film, a silicon nitride film having a superior role than that of the silicon oxide film is used, and the BPSG film is deposited twice, and when the first BPSG film is deposited, its thickness is reduced to about 500 kPa to 2,000 kPa, and the original etch stop film is used. The source / drain annealing process, which was performed just before the deposition of the film, is omitted, and the source / drain annealing process is performed after the first BPSG film is deposited, thereby serving as a source / drain annealing function and at the same time serving as a BPSG annealing. Since the BPSG flow is easy to proceed at a high temperature (800 ° C. to 1,000 ° C.) compared to the annealing temperature of 700 ° C., slit voids formed between the gate electrodes having a high aspect ratio during the first BPSG film deposition can be removed.

In this case, since the BPSG film is a relatively thin film formed primarily, it is easier to remove the slit voids formed in the lower portion of the narrow gap between the gate electrodes in the final interlayer insulating film than in the case where the thickness of the BPSG film was deposited at one time, thereby making it easier to remove the BPSG film at once. After deposition, slit voids that are not removed during the source / drain annealing process may also be removed.

The BPSG slit void can also be completely removed without changing the transistor characteristics of the device during source / drain annealing in a state where the thickness of the BPSG film is not thick.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

2A to 2E are diagrams illustrating a semiconductor manufacturing process procedure according to the present invention.

First, the present invention describes a particularly salicylic process because the salicided source / drain junction mentioned above can cause junction leakage current in relatively high temperature processes. It is mainly used in low power processes of semiconductor devices such as slow SRAM.

 As shown in FIG. 2A, as the semiconductor substrate 100, a field oxide film is formed on a silicon substrate by an STI process, and a gate oxide film (not shown) is formed on the active region of the semiconductor substrate 100. . Next, a doped poly silicon is deposited as a conductive layer on the gate oxide layer, and a photo polysilicon layer is patterned using a gate mask to pattern the doped polysilicon layer to form a gate electrode 102. The gate oxide film is also patterned.

 Next, although not shown, a LDD (Lightly Doped Drain) ion implantation process is performed to form an LDD region in the semiconductor substrate 100 exposed by the gate electrode 102. Subsequently, a silicon nitride film is deposited as an insulating thin film on the entire surface of the semiconductor substrate and dry-etched to form the gate electrode 102 and the sidewall spacer 104. Then, although not shown in the drawing, the gate electrode 102 and the sidewall spacer 104 are masked to perform a source / drain ion implantation process to form a source / drain region in the semiconductor substrate 100 to form a gate electrode ( 102) A semiconductor device of a MOSFET having a source / drain region is manufactured.

Next, as shown in FIG. 2B, the etching stop layer 106 is manufactured.

In this case, it is important to omit the source / drain annealing process originally performed before the deposition of the etch stop layer 106, and then proceed with the source / drain annealing process after the deposition of the first BPSG film described in FIGS. 2C and 2D.

The role of the etch stop layer 106 serves as a safe contact hole etching control as an etch stopper during contact hole etching, and at the same time serves to prevent diffusion of boron (B) or phosphorus (P) dopant into the semiconductor substrate of the BPSG film. do.

Therefore, it is advantageous to use a silicon nitride film as the etch stop film 106 rather than a silicon oxide film. In the present invention, a silicon nitride film is particularly used because the temperature of the subsequent primary BPSG annealing process is relatively high. The thickness of the silicon nitride film as the etch stop film is 350 kPa.

An etch stop layer 106 thinly deposited is formed on the entire upper surface of the semiconductor substrate 100.

Subsequently, as shown in FIG. 2C, the first BPSG film 108 is deposited as thin as about 500 kPa to 2,000 kPa as an interlayer insulating film on the entire upper surface of the etch stop film 106. At this time, the slit void 200 is also formed between the narrow gate electrodes.

Next, as shown in FIG. 2D, the source / drain annealing process, which was omitted after the source / drain ion implantation, is performed under the same conditions. In this case, in the case of the source / drain annealing process, the flow of the BPSG film is facilitated because the BPSG film is formed at a higher temperature than the BPSG annealing temperature (700 ° C.) for the reliable diffusion of the source / drain junction and the thickness of the first formed BPSG film is thinner. You can certainly remove all the slit voids inside. As a result, after the annealing, a void-free primary BPSG film 108a is formed.

 Next, as shown in FIG. 2E, the second BPSG film 110 is thickly deposited for planarization as an interlayer insulating film, and the surface of the second BPSG film 110 is subjected to a chemical mechanical polishing (CMP) process after a normal 700 ° C. annealing process. By planarizing to obtain a void-free interlayer insulating film between the gate electrode and the metal line, as a result, it is possible to prevent the inter-contact hole bridge to contribute to the improvement of the yield of the semiconductor device.

As described above, the present invention is applied to the process of a semiconductor device, and during the deposition of the BPSG film, which is an interlayer insulating film between the gate electrode and the metal line, the BPSG film deposition process is performed twice, but before the etch stop film deposition in the related art. The source / drain annealing process is performed immediately after the deposition of the first BPSG film to serve as a BPSG annealing role and a source / drain annealing role, and the BPSG flow is improved by the effect of the relatively high temperature source / drain annealing process. By thinly depositing the thickness of the primary BPSG film, the flow effect can be doubled to completely remove the slit voids formed between the gate electrodes after the growth of the first BPSG film, as well as the source / drain annealing in the thin state of the BPSG film. Source / drain annealing that proceeds immediately after source / drain ion implantation in prior art, i.e. before etch stop film deposition In the same advantage it can be removed without any voids changes in characteristics of the transistors.

In addition, the manufacturing method of the present invention has the advantage that it can be easily applied using a conventionally applied process without the addition of a difficult process such as additional mask process.

Claims (5)

In the method of manufacturing an interlayer insulating film of a semiconductor device, Forming a gate electrode on the semiconductor substrate and sidewall spacers on the side thereof;  Depositing an etch stop layer on the entire surface of the semiconductor substrate after source / drain ion implantation in the state where the gate electrode and the sidewall spacer are present;  Depositing and annealing a first BPSG film on the etch stop layer;  And depositing a second BPSG film on the first BPSG film, annealing the same, and then performing CMP for planarization. The method of claim 1, The sidewall spacer is a method of manufacturing an interlayer insulating film of a semiconductor device, characterized in that the silicon nitride film. The method of claim 1, The etch stop layer is a method of manufacturing an interlayer insulating film of a semiconductor device, characterized in that the silicon nitride film. The method of claim 1, The primary BPSG film has a thickness of 500 kPa to 2,000 kPa. The method of claim 1, And annealing the primary BPSG film to simultaneously perform source / drain annealing.

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