KR20050012582A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

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Publication number
KR20050012582A
KR20050012582A KR1020030051582A KR20030051582A KR20050012582A KR 20050012582 A KR20050012582 A KR 20050012582A KR 1020030051582 A KR1020030051582 A KR 1020030051582A KR 20030051582 A KR20030051582 A KR 20030051582A KR 20050012582 A KR20050012582 A KR 20050012582A
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KR
South Korea
Prior art keywords
film
bpsg
gate
silicon substrate
semiconductor device
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KR1020030051582A
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Korean (ko)
Inventor
신주한
Original Assignee
매그나칩 반도체 유한회사
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Priority to KR1020030051582A priority Critical patent/KR20050012582A/en
Publication of KR20050012582A publication Critical patent/KR20050012582A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to reduce effectively thermal budget of an interlayer dielectric by depositing a BPSG(Boron Phosphorous Silicate Glass) layer as a passivation barrier layer on an oxide layer. CONSTITUTION: A transistor including a gate(5) is formed on a silicon substrate(1). An oxide layer(7) is formed on the gate and the silicon substrate by HDPCVD(High Density Plasma Chemical Vapor Deposition). A BPSG layer(9) as a passivation barrier layer is then formed on the oxide layer. The passivation barrier layer is annealed.

Description

반도체 소자의 제조방법{METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 층간절연막에 기인하는 공정 마진 및 소자 특성 저하를 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing process margins and device characteristics from being lowered due to an interlayer insulating film.

현재 대부분의 반도체 제조 공정에서는 게이트들 사이의 절연 물질로서, 즉, 층간절연 물질로서 매립(gap-fill) 및 평탄화 특성이 양호한 BPSG(Boron Phosphrous Silicate Glass)를 사용하고 있다.Currently, most semiconductor manufacturing processes use BPSG (Boron Phosphrous Silicate Glass), which has good gap-filling and planarization characteristics, as an insulating material between gates, that is, an interlayer insulating material.

또한, 상기 BPSG를 절연 물질로 사용하게 되면, 게이트 형성후의 열공정시에상기 BPSG에 함유되어 있는 붕소(B) 및 인(P)이 실리콘 기판 내에 확산되어 기판 불순물 농도의 변동을 일으키는 바, 이러한 문제를 방지하기 위해, 아울러, 고집적화에 따른 보더리스 콘택(borderless contact) 마진을 확보하기 위해, 상기 BPSG의 형성 전에 기판의 전면 상에 실리콘 질화막을 증착하고 있다.In addition, when the BPSG is used as an insulating material, boron (B) and phosphorus (P) contained in the BPSG are diffused in the silicon substrate during the thermal process after the gate formation, which causes variations in the substrate impurity concentration. The silicon nitride film is deposited on the entire surface of the substrate prior to the formation of the BPSG in order to prevent the defects and to secure a borderless contact margin due to high integration.

자세하게, 종래 기술에 따른 비트라인 콘택 형성 단계까지의 공정을 설명하면 다음과 같다.In detail, the process up to the bit line contact forming step according to the prior art will be described.

먼저, 실리콘 기판의 적소에 STI(Shallow Trench Isolation) 공정에 따라 트렌치형의 소자분리막들을 형성하고, 실리콘 기판 상에 게이트와 소오스 및 드레인 영역을 포함한 트랜지스터를 형성한다.First, trench-type device isolation layers are formed in place on a silicon substrate according to a shallow trench isolation (STI) process, and a transistor including a gate, a source, and a drain region is formed on the silicon substrate.

그 다음, 상기 트랜지스터를 포함한 실리콘 기판의 전 영역 상에 실리콘 질화막을 증착하고, 상기 실리콘 질화막 상에 층간절연 물질로서 BPSG막을 증착한다.Then, a silicon nitride film is deposited on the entire region of the silicon substrate including the transistor, and a BPSG film is deposited on the silicon nitride film as an interlayer insulating material.

이어서, 상기 BPSG막을 식각하여 콘택홀들을 형성하고, 상기 콘택홀을 포함한 BPSG막 상에 베리어막 및 텅스텐막을 차례로 증착한다.Subsequently, contact holes are formed by etching the BPSG film, and a barrier film and a tungsten film are sequentially deposited on the BPSG film including the contact hole.

이후, 상기 텅스텐막과 베리어막을 CMP(Chemical mechanical Polishing)하여 비트라인용 콘택플러그를 형성한 후, 후속의 비트라인 형성 공정을 진행한다.Thereafter, the tungsten film and the barrier film are formed by chemical mechanical polishing (CMP) to form a contact plug for a bit line, and then a subsequent bit line forming process is performed.

그러나, 층간절연 물질로서 BPSG를 사용하는 경우, 다음과 같은 문제점이 발생된다.However, when BPSG is used as the interlayer insulating material, the following problem occurs.

우선, 소자의 크기가 작아짐에 따라 상대적으로 층간절연막의 두께가 두꺼워지면서 콘택을 형성하는 포토 공정에서 포토레지스트 마진(margin)이 부족하고, 식각 공정에서 양호한 프로파일(profile)을 구현하기 어렵다. 또한, 콘택플러그 형성시에는 베리어막의 증착이 어려울 뿐만 아니라, 텅스텐에 의한 콘택홀의 완전 매립이 이루어지지 못하여, 콘택플러그의 저항 증가가 유발된다.First, as the size of the device becomes smaller, the thickness of the interlayer insulating layer becomes relatively thick, so that the photoresist margin is insufficient in the photo process for forming a contact, and it is difficult to implement a good profile in the etching process. In addition, when the contact plug is formed, not only the barrier film is deposited, but also the contact holes are not completely filled by tungsten, thereby increasing the resistance of the contact plug.

반면, 층간절연막의 두께가 얇아지면, 이웃하는 배선들 사이 및 상하 배선들 사이의 기생 용량이 증가하여 신호 지연 현상이 유발된다.On the other hand, when the thickness of the interlayer insulating film becomes thin, the parasitic capacitance between neighboring wirings and between the upper and lower wirings increases, causing a signal delay phenomenon.

또한, BPSG는 막 특성상 그의 치밀화(desification)를 위해 증착후에 고온 어닐링을 해주어야 하는데, 이러한 고온 어닐링 과정에서 소자 특성이 변동 및 저하될 수 있다.In addition, the BPSG has to be subjected to a high temperature annealing after deposition for its densification due to the characteristics of the film, and the device characteristics may be changed and degraded during the high temperature annealing process.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 층간절연막에 기인하는 소자 특성 저하를 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing the deterioration of device characteristics caused by an interlayer insulating film, which is devised to solve the above problems.

도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.1A to 1D are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1 : 실리콘 기판 3 : 소자분리막1 silicon substrate 3 device isolation film

5 : 게이트 7 : 산화막5 gate 7 oxide film

9 : BPSG막 또는 PSG막9: BPSG film or PSG film

상기 목적을 달성하기 위한 본 발명은, 실리콘 기판 상에 게이트를 포함한 트랜지스터를 형성하는 단계; 상기 게이트 및 실리콘 기판 상에 산화막을 형성하는 단계; 상기 산화막 표면에 패시베이션 배리어막을 형성하는 단계; 및 상기 패시베이션 배리어막에 열처리 공정을 진행하는 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object, forming a transistor including a gate on a silicon substrate; Forming an oxide film on the gate and the silicon substrate; Forming a passivation barrier film on the oxide film surface; And performing a heat treatment process on the passivation barrier film.

(실시예)(Example)

이하, 본 발명의 바람직한 실시예에 대해 첨부된 도면을 참조하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도이다.1A to 1D are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

본 발명에 따른 반도체 소자의 제조방법은, 도 1a에 도시된 바와 같이, 실리콘 기판(1)의 적소에 STI 공정에 따라 액티브 영역을 한정하는 트렌치형의 소자분리막(3)을 형성한다. 그 다음, 상기 소자분리막(3)을 포함한 기판의 전 영역 상에 게이트 산화막 및 게이트 도전막을 차례로 형성하고, 이들을 패터닝(Patterning)하여 실리콘 기판(1) 상에 게이트(5)를 형성한다.In the method for manufacturing a semiconductor device according to the present invention, as shown in FIG. 1A, a trench type device isolation film 3 defining an active region in accordance with an STI process is formed in place of the silicon substrate 1. Next, a gate oxide film and a gate conductive film are sequentially formed on the entire region of the substrate including the device isolation film 3, and patterned to form a gate 5 on the silicon substrate 1.

이어서, 도시하지는 않았으나, 공지의 LDD(Lightly Doped Drain) 이온주입 공정과, 스페이서 형성 공정 및 소오스 및 드레인 이온주입 공정을 차례로 수행하여 상기 게이트 양측의 기판 표면에 LDD 영역을 갖는 소오스 및 드레인 영역을 형성하여 이를 통해 트랜지스터를 형성한다.Subsequently, although not shown, a known lightly doped drain (LDD) ion implantation process, a spacer forming process, and a source and drain ion implantation process are sequentially performed to form source and drain regions having LDD regions on the substrate surfaces on both sides of the gate. Thereby forming a transistor.

그 다음, 도 1b에 도시된 바와 같이, 상기 게이트(5)를 포함한 실리콘 기판(1)의 전 영역 상에 HDPCVD(High Density Plasma Chemical Vapor Deposition) 방식을 사용하여 산화막(7)을 증착한다. 이때, 산화막(7)의 증착 온도는 350℃∼650℃ 정도이다. 여기에서, 산화막(7)은 층간절연막의 역할을 한다. 또한, HDPCVD 방식을 사용하는 경우, 낮은 온도에서도 산화막을 증착할 수 있다.Next, as illustrated in FIG. 1B, an oxide film 7 is deposited on the entire region of the silicon substrate 1 including the gate 5 by using HDPCVD (High Density Plasma Chemical Vapor Deposition). At this time, the deposition temperature of the oxide film 7 is about 350 ° C to 650 ° C. Here, the oxide film 7 serves as an interlayer insulating film. In addition, when the HDPCVD method is used, the oxide film can be deposited even at a low temperature.

이어서, 도 1c에 도시된 바와 같이, HDPCVD 방식을 사용하여 산화막(7)을 증착한 후에 유동성 이온의 침투를 막기 위해 보호막의 역할을 할 수 있는 BPSG막 또는 PSG(Phosphrous Silicate Glass)막(9)을 증착한다. 이때, BPSG막의 농도는 붕소와 인의 비율로 결정되며, 이때에 붕소와 인을 12:4 mol%∼13:6 mol% 정도의 비율로 한다.Subsequently, as shown in FIG. 1C, after the deposition of the oxide film 7 using the HDPCVD method, the BPSG film or the Phosphrous Silicate Glass (PSG) film 9, which may serve as a protective film to prevent the infiltration of fluid ions, may be used. Deposit. At this time, the concentration of the BPSG film is determined by the ratio of boron and phosphorus, at this time boron and phosphorus in a ratio of 12: 4 mol% to 13: 6 mol%.

그 다음, 도 1d에 도시된 바와 같이, BPSG막 또는 PSG막(9)을 증착한 후에 수분 흡수를 막기 위해 고속 열처리 공정(Rapid Thermal Process : RTP)(11)을 진행한다. 이때, 고속 열처리 공정(11)을 진행하기 위한 온도는 350℃∼650℃ 정도이다. 여기에서, BPSG막은 열처리 공정을 수행하지 않으면, 습식 세정 공정 등에서 수분을 흡수하여 BPO4라는 결정을 형성할 수 있다. 또한, 고속 열처리 공정(11) 대신 수분 흡수를 막기 위해 퍼니스 어닐링(Furnace Anneal) 공정을 진행할 수 있다.Next, as shown in FIG. 1D, after depositing the BPSG film or PSG film 9, a rapid thermal process (RTP) 11 is performed to prevent moisture absorption. At this time, the temperature for advancing the high speed heat treatment process 11 is about 350 to 650 degreeC. Here, if the BPSG film is not subjected to the heat treatment process, the BPSG film may absorb water in a wet cleaning process to form a crystal called BPO 4 . In addition, a furnace annealing process may be performed instead of the high speed heat treatment process 11 to prevent moisture absorption.

따라서, 본 발명은 HDPCVD 방식을 사용하여 산화막을 형성하여 매립한 후에 BPSG막 또는 PSG막을 증착함으로써, 유동성 이온의 침투를 막는 보호막 역할을 하여 층간절연막의 열적부하(Thermal Budget)를 효과적으로 감소시킬 수 있다.Accordingly, the present invention can effectively reduce the thermal budget of the interlayer insulating film by acting as a protective film to prevent the penetration of fluidic ions by depositing a BPSG film or PSG film after the oxide film is formed and embedded using the HDPCVD method. .

이상, 본 발명을 몇 가지 예를 들어 설명하였으나, 본 발명은 이에 한정되는 것은 아니며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 본 발명의 사상에서 벗어나지 않으면서 많은 수정과 변형을 가할 수 있음을 이해할 것이다.In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person of ordinary skill in the art may make many modifications and variations without departing from the spirit of the present invention. I will understand.

이상에서와 같이, 본 발명에 의하면, HDPCVD 방식을 사용하여 산화막을 형성하여 매립한 후에 BPSG막 또는 PSG막을 증착함으로써, 유동성 이온의 침투를 막는 보호막 역할을 하여 층간절연막의 열적부하를 감소시킬 수 있다.As described above, according to the present invention, by depositing a BPSG film or a PSG film after forming and embedding an oxide film using the HDPCVD method, it is possible to reduce the thermal load of the interlayer insulating film by acting as a protective film to prevent the penetration of fluid ions. .

또한, 층간절연막의 열적부하가 감소함에 따라 살리사이드(Salicide)의 열화를 방지하여 저항의 증가 또는 문턱전압의 이동 등과 같은 소자의 특성을 개선할수 있다.In addition, as the thermal load of the interlayer insulating layer decreases, degradation of the salicide may be prevented, thereby improving device characteristics such as an increase in resistance or a shift in threshold voltage.

Claims (5)

실리콘 기판 상에 게이트를 포함한 트랜지스터를 형성하는 단계;Forming a transistor including a gate on the silicon substrate; 상기 게이트 및 실리콘 기판 상에 산화막을 형성하는 단계;Forming an oxide film on the gate and the silicon substrate; 상기 산화막 표면에 패시베이션 배리어막을 형성하는 단계; 및Forming a passivation barrier film on the oxide film surface; And 상기 패시베이션 배리어막에 열처리 공정을 진행하는 단계를 포함하여 구성되는 것을 특징으로 하는 반도체 소자의 제조방법.And performing a heat treatment process on the passivation barrier film. 제 1 항에 있어서, 상기 패시베이션 배리어막은 BPSG막 또는 PSG막을 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the passivation barrier film is a BPSG film or a PSG film. 제 2 항에 있어서, 상기 BPSG막은 붕소 및 인을 12:4 mol%∼13:6 mol% 정도의 비율로 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 2, wherein the BPSG film uses boron and phosphorus at a ratio of about 12: 4 mol% to about 13: 6 mol%. 제 1 항에 있어서, 상기 열처리 공정은 고속 열처리 공정 또는 퍼니스 어닐링 공정을 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the heat treatment process uses a high speed heat treatment process or a furnace annealing process. 제 4 항에 있어서, 상기 고속 열처리 공정은 350℃∼650℃ 정도의 온도에서 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 4, wherein the high-speed heat treatment is performed at a temperature of about 350 ° C. to about 650 ° C. 6.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009126478A1 (en) * 2008-04-08 2009-10-15 Fairchild Semiconductor Corporation Bpsg film deposition with undoped capping

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009126478A1 (en) * 2008-04-08 2009-10-15 Fairchild Semiconductor Corporation Bpsg film deposition with undoped capping

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