KR100541151B1 - 반도체 소자의 금속배선 형성방법 - Google Patents
반도체 소자의 금속배선 형성방법 Download PDFInfo
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- KR100541151B1 KR100541151B1 KR1020030049468A KR20030049468A KR100541151B1 KR 100541151 B1 KR100541151 B1 KR 100541151B1 KR 1020030049468 A KR1020030049468 A KR 1020030049468A KR 20030049468 A KR20030049468 A KR 20030049468A KR 100541151 B1 KR100541151 B1 KR 100541151B1
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- copper
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- metal wiring
- coating film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (8)
- 하부금속배선이 형성된 반도체 기판상에 층간 절연막을 형성하고, 상기 층간 절연막을 패터닝하여 상기 하부금속배선을 노출하는 비아홀 및 금속배선 트렌치를 형성하는 단계;상기 비아홀 및 금속배선 트렌치가 형성된 결과물 상에 구리막을 형성한 후 평탄화 공정을 수행하여 비아 및 금속배선을 형성하는 단계;상기 비아 및 금속배선이 형성된 결과물 상부에 코팅막 형성이온을 증착하여 코팅막을 형성한 후 열처리공정을 수행하여 상기 구리막 상부에만 구리- 코팅막을 형성하는 단계; 및상기 구리-코팅막이 형성된 결과물 상에 캡핑막을 형성하는 단계를 포함하는 반도체소자의 금속배선 형성방법.
- 삭제
- 제2 항에 있어서, 상기 코팅막 형성이온은Pd, Ti , Ru, Ta, W, Co, Ni, Cu, Mg, Pt 또는 WP 중 어느 하나를 사용하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.
- 제2 항에 있어서, 상기 열처리공정은N2 , H2 또는 Ar 기체를 이용하여 200~ 600℃ 정도의 온도에서 0.5~ 3정도의 시간동안 수행하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.
- 하부금속배선이 형성된 반도체 기판상에 층간 절연막을 형성하고, 상기 층간 절연막을 패터닝하여 상기 하부금속배선을 노출하는 비아홀 및 금속배선 트렌치를 형성하는 단계;상기 비아홀 및 금속배선 트렌치의 측벽에 베리어 메탈층을 형성하는 단계;상기 베리어 메탈층이 형성된 결과물 상에 구리층을 형성한 후 제1 평탄화 공정을 수행하여 비아 및 금속배선을 형성하는 단계;상기 비아 및 금속배선이 형성된 결과물 상에 코팅막 형성이온을 증착하여 코팅막을 형성하는 단계;상기 코팅막이 형성된 결과물에 열처리공정을 수행하여 상기 코팅막을 형성하는 이온이 상기 베리어 메탈층 및 상기 구리층 내부로 이동 반응하여 상기 베리어 메탈층과 상기 코팅막 사이 및 상기 구리층 상부에 구리- 코팅막을 형성하는 단계; 및상기 코팅막, 구리- 코팅막 및 베리어 메탈층을 제1 습식식각공정과 제2 평탄화공정을 순차적으로 진행하여 제거하여, 상기 비아 및 금속배선을 매립하는 구리층 상부에만 구리- 코팅막을 형성하는 단계; 및상기 구리-코팅막이 형성된 결과물 상에 캡핑막을 형성하는 단계를 포함하는 반도체 소자의 금속배선 형성방법.
- 제5 항에 있어서, 상기 열처리공정은N2 , H2 또는 Ar 기체를 이용하여 200~ 600℃ 정도의 온도에서 0.5~ 3정도의 시간동안 수행하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.
- 제5 항에 있어서, 상기 코팅막 형성이온은Pd, Ti , Ru, Ta, W, Co, Ni, Cu, Mg, Pt 또는 WP 중 어느 하나를 사용하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.
- 제5 항에 있어서, 상기 제1 습식식각공정은NH4OH/H2O2/H2O, HCl/H2O2/H2O 또는 H2SO4/H2O2/O3/DI수용액 중 어느 하나를 사용하고, -5~ 140℃ 정도의 온도에서 10~ 30분 정도 진행하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.
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KR1020030049468A KR100541151B1 (ko) | 2003-07-18 | 2003-07-18 | 반도체 소자의 금속배선 형성방법 |
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KR1020030049468A KR100541151B1 (ko) | 2003-07-18 | 2003-07-18 | 반도체 소자의 금속배선 형성방법 |
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KR20050009653A KR20050009653A (ko) | 2005-01-25 |
KR100541151B1 true KR100541151B1 (ko) | 2006-01-11 |
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KR100744247B1 (ko) * | 2005-12-28 | 2007-07-30 | 동부일렉트로닉스 주식회사 | 구리 배선 형성 방법 |
KR101006522B1 (ko) * | 2008-08-08 | 2011-01-07 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 및 그의 형성방법 |
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