KR100525116B1 - Method for forming pad region of semiconductor device - Google Patents
Method for forming pad region of semiconductor device Download PDFInfo
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- KR100525116B1 KR100525116B1 KR10-1999-0003544A KR19990003544A KR100525116B1 KR 100525116 B1 KR100525116 B1 KR 100525116B1 KR 19990003544 A KR19990003544 A KR 19990003544A KR 100525116 B1 KR100525116 B1 KR 100525116B1
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- aluminum wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 패드영역 형성방법에 관한 것으로, 종래에는 노출된 알루미늄 배선의 표면에 직접 알루미늄 와이어를 본딩함에 따라 알루미늄 배선의 표면상태(평탄도 등)에 의해 접촉불량과 같은 본딩불량이 발생하는 문제점이 있었다. 따라서, 본 발명은 반도체소자가 형성된 실리콘기판의 상부에 순차적으로 알루미늄 배선, 반사방지막 및 소자보호막을 형성한 후, 사진식각공정을 통해 소자보호막 및 반사방지막의 일부를 식각하여 패드영역의 알루미늄 배선을 노출시키는 공정과; 상기 노출된 알루미늄 배선의 일부를 사진식각공정을 통해 식각하여 홈을 형성하는 공정과; 웨이퍼의 각 소자를 절단하여 개별소자로 만든 다음 상기 알루미늄 배선의 일부에 형성된 홈에 도전성 와이어를 본딩하는 공정으로 이루어지는 반도체소자의 패드영역 형성방법을 통해 노출된 알루미늄 배선의 표면 일부에 형성된 홈 상에 와이어를 본딩함에 따라 알루미늄 배선의 표면상태에 의한 본딩불량을 방지함과 아울러 다양한 감광막 패턴 제작에 의해 상기 홈을 다양한 형태로 형성함에 따라 본딩 적용에 유리한 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a pad region of a semiconductor device. In the related art, bonding defects such as contact failures are generated due to the surface state (flatness, etc.) of aluminum wirings by bonding the aluminum wires directly to the exposed surface of the aluminum wirings. There was a problem. Accordingly, the present invention sequentially forms an aluminum wiring, an antireflection film, and a device protection film on the silicon substrate on which the semiconductor device is formed, and then, by etching a portion of the device protection film and the antireflection film through a photolithography process, the aluminum wiring of the pad region is removed. Exposing; Forming a groove by etching a portion of the exposed aluminum wiring through a photolithography process; Each element of the wafer is cut into individual elements, and then a conductive wire is bonded to a groove formed in a part of the aluminum wiring, thereby forming a pad region of the semiconductor device. As the wire is bonded, the bonding defect is prevented due to the surface state of the aluminum wiring, and the grooves are formed in various shapes by manufacturing various photoresist patterns, which is advantageous in bonding applications.
Description
본 발명은 반도체소자의 패드영역 형성방법에 관한 것으로, 특히 반도체소자를 와이어-본딩(wire bonding)하는 패드영역에서의 본딩불량을 방지하기에 적당하도록 한 반도체소자의 패드영역 형성방법에 관한 것이다.The present invention relates to a method of forming a pad region of a semiconductor device, and more particularly, to a method of forming a pad region of a semiconductor device suitable for preventing a bonding failure in a pad region for wire-bonding a semiconductor device.
종래 반도체소자의 패드영역 형성방법을 도1a 내지 도1c에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A method of forming a pad region of a conventional semiconductor device will now be described in detail with reference to the procedure cross-sectional view shown in FIGS. 1A to 1C.
먼저, 도1a에 도시한 바와같이 반도체소자가 형성된 실리콘기판(1) 상부에 순차적으로 알루미늄 배선(2), 반사방지막(3) 및 소자보호막(4)을 형성한 후, 상기 소자보호막(4)의 상부에 감광막(PR1)을 도포하고, 노광 및 현상하여 패드영역이 오픈되는 감광막(PR1) 패턴을 형성한다. 이때, 소자보호막(4)은 평탄화를 위한 PSG(phosphosilica glass)막과 실리콘질화막의 적층구조로 형성된다.First, as shown in FIG. 1A, an aluminum wiring 2, an antireflection film 3, and a device protection film 4 are sequentially formed on the silicon substrate 1 on which the semiconductor device is formed, and then the device protection film 4 is formed. The photoresist film PR1 is coated on the upper portion of the substrate, and the photoresist film PR1 pattern is formed by exposing and developing the pad region. In this case, the device protection film 4 is formed of a laminated structure of a PSG (phosphosilica glass) film and a silicon nitride film for planarization.
그리고, 도1b에 도시한 바와같이 상기 감광막(PR1) 패턴을 적용하여 상기 소자보호막(4)과 반사방지막(3)을 건식 식각함으로써, 알루미늄 배선(2)을 노출시킨 후, 감광막(PR1) 패턴을 제거한다. Then, as shown in FIG. 1B, the device protective film 4 and the anti-reflection film 3 are dry-etched by applying the photoresist film PR1 pattern to expose the aluminum wiring 2, and then the photoresist film PR1 pattern. Remove it.
그리고, 웨이퍼의 각 소자를 절단하여 개별소자로 만든 다음(chip sawing) 도1c에 도시한 바와같이 상기 노출된 알루미늄 배선(2) 상에 알루미늄과 같은 도전성 와이어(5)를 본딩(6)한다.Then, each element of the wafer is cut and chip sawed, and then a conductive wire 5 such as aluminum is bonded 6 on the exposed aluminum wiring 2 as shown in FIG. 1C.
그러나, 상기한 바와같은 종래 반도체소자의 패드영역 형성방법은 노출된 알루미늄 배선의 표면에 직접 알루미늄 와이어를 본딩함에 따라 알루미늄 배선의 표면상태(평탄도 등)에 의해 접촉불량과 같은 본딩불량이 발생하는 문제점이 있었다. However, in the method of forming a pad region of a conventional semiconductor device as described above, bonding defects such as poor contact occur due to the surface state (flatness, etc.) of the aluminum wiring by bonding the aluminum wire directly to the exposed surface of the aluminum wiring. There was a problem.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 알루미늄 배선의 표면상태에 의한 본딩불량을 방지할 수 있는 반도체소자의 패드영역 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to provide a method for forming a pad region of a semiconductor device capable of preventing a bonding defect caused by a surface state of an aluminum wiring.
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 패드영역 형성방법은 반도체소자가 형성된 실리콘기판의 상부에 순차적으로 알루미늄 배선, 반사방지막 및 소자보호막을 형성한 후, 사진식각공정을 통해 소자보호막 및 반사방지막의 일부를 식각하여 패드영역의 알루미늄 배선을 노출시키는 공정과; 상기 노출된 알루미늄 배선의 일부를 사진식각공정을 통해 식각하여 홈을 형성하는 공정과; 웨이퍼의 각 소자를 절단하여 개별소자로 만든 다음 상기 알루미늄 배선의 일부에 형성된 홈에 도전성 와이어를 본딩하는 공정을 구비하여 이루어지는 것을 특징으로 한다.The method for forming a pad region of a semiconductor device for achieving the object of the present invention as described above is formed by sequentially forming an aluminum wiring, an anti-reflection film and a device protection film on the silicon substrate on which the semiconductor device is formed, and then through a photolithography process Etching a portion of the protective film and the anti-reflection film to expose the aluminum wiring in the pad region; Forming a groove by etching a portion of the exposed aluminum wiring through a photolithography process; Cutting each element of the wafer into individual elements, and then bonding a conductive wire to a groove formed in a part of the aluminum wiring.
상기한 바와같은 본 발명에 의한 반도체소자의 패드영역 형성방법을 도2a 내지 도2e에 도시한 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.A method of forming a pad region of a semiconductor device according to the present invention as described above will be described in detail with reference to a cross-sectional view shown in FIGS. 2A to 2E as an embodiment.
먼저, 도2a에 도시한 바와같이 반도체소자가 형성된 실리콘기판(11) 상부에 순차적으로 알루미늄 배선(12), 반사방지막(13) 및 소자보호막(14)을 형성한 후, 상기 소자보호막(14)의 상부에 감광막(PR11)을 도포하고, 노광 및 현상하여 패드영역이 오픈되는 감광막(PR11) 패턴을 형성한다. 이때, 소자보호막(14)은 종래와 동일하게 평탄화를 위한 PSG막과 실리콘질화막의 적층구조로 형성된다.First, as shown in FIG. 2A, the aluminum wiring 12, the antireflection film 13, and the device protection film 14 are sequentially formed on the silicon substrate 11 on which the semiconductor device is formed, and then the device protection film 14 is formed. The photoresist film PR11 is applied on the upper portion of the substrate, and the photoresist film PR11 pattern is formed by exposing and developing the pad region. At this time, the element protection film 14 is formed of a laminated structure of a PSG film and a silicon nitride film for planarization as in the prior art.
그리고, 도2b에 도시한 바와같이 상기 감광막(PR11) 패턴을 적용하여 상기 소자보호막(14)과 반사방지막(13)을 건식 식각함으로써, 알루미늄 배선(12)을 노출시킨 후, 감광막(PR11) 패턴을 제거한다. As shown in FIG. 2B, the device protective film 14 and the anti-reflection film 13 are dry-etched by applying the photoresist film PR11 pattern to expose the aluminum wiring 12, and then the photoresist film PR11 pattern. Remove it.
그리고, 도2c에 도시한 바와같이 상기 노출된 알루미늄 배선(12) 및 반사방지막(13)의 상부전면에 감광막(PR12)을 도포하고, 노광 및 현상하여 본딩영역이 오픈되는 감광막(PR12) 패턴을 형성한다. 이때, 본딩영역을 오픈시키는 감광막(PR12) 패턴은 도3a 및 도3b의 평면도에 도시한 바와같이 다양하게 형성될 수 있다.As shown in FIG. 2C, the photoresist film PR12 is coated on the exposed front surfaces of the aluminum wiring 12 and the antireflection film 13, and the photoresist film PR12 pattern is formed by exposing and developing the bonding region to open. Form. In this case, the photoresist film PR12 pattern for opening the bonding region may be variously formed as shown in the plan views of FIGS. 3A and 3B.
그리고, 도2d에 도시한 바와같이 상기 감광막(PR12) 패턴을 적용하여 본딩영역이 오픈된 알루미늄 배선(12)을 식각함으로써, 홈(15)을 형성하고 감광막(PR12) 패턴을 제거한다. 이때, 홈(15)은 건식 또는 습식식각중에 선택된 하나의 방법으로 노출된 알루미늄 배선(12)을 2000Å∼4000Å 정도 식각하여 형성하는 것이 바람직하다.As shown in FIG. 2D, the grooves 15 are formed and the photoresist film PR12 pattern is removed by etching the aluminum wiring 12 having the bonding region open by applying the photoresist film PR12 pattern. At this time, the groove 15 is preferably formed by etching the aluminum wiring 12 exposed by one method selected from dry or wet etching about 2000 ~ 4000 ~.
그리고, 웨이퍼의 각 소자를 절단하여 개별소자로 만든 다음(chip sawing) 도2e에 도시한 바와같이 상기 노출된 알루미늄 배선(12)의 홈(15) 상에 알루미늄과 같은 도전성 와이어(16)를 본딩(17)한다. 이때, 본딩(17)은 Au와 Al의 합금으로 형성하는 것이 바람직하다.Then, each element of the wafer is cut to chip sawing, and then a conductive wire 16 such as aluminum is bonded to the groove 15 of the exposed aluminum wiring 12 as shown in FIG. 2E. (17) At this time, the bonding 17 is preferably formed of an alloy of Au and Al.
상기한 바와같은 본 발명에 의한 반도체소자의 패드영역 형성방법은 노출된 알루미늄 배선의 표면 일부에 형성된 홈 상에 와이어를 본딩함에 따라 알루미늄 배선의 표면상태에 의한 본딩불량을 방지함과 아울러 다양한 감광막 패턴 제작에 의해 상기 홈을 다양한 형태로 형성함에 따라 본딩 적용에 유리한 효과가 있다.As described above, the method for forming a pad region of a semiconductor device according to the present invention prevents bonding failure due to the surface state of the aluminum wiring by bonding wires on grooves formed in a part of the exposed surface of the aluminum wiring and various photoresist pattern patterns. As the grooves are formed in various forms by manufacturing, there is an advantageous effect to the bonding application.
도1a 내지 도1c는 종래 반도체소자의 패드영역 형성방법을 보인 수순단면도.1A to 1C are cross-sectional views showing a method for forming a pad region of a conventional semiconductor device.
도2a 내지 도2e는 본 발명의 일 실시예를 보인 수순단면도.Figures 2a to 2e is a cross-sectional view showing an embodiment of the present invention.
도3a 및 도3c는 도2c의 감광막 패턴을 예로써 도시한 평면도.3A and 3C are plan views showing the photosensitive film pattern of Fig. 2C as an example.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
11:실리콘기판12:알루미늄 배선11: Silicon substrate 12: Aluminum wiring
13:반사방지막14:소자보호막13: Anti-reflective coating 14: Element protective film
15:홈16:도전성 와이어15: groove 16: conductive wire
17:본딩PR11,PR12:감광막17: bonding PR11, PR12: photosensitive film
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0003544A KR100525116B1 (en) | 1999-02-03 | 1999-02-03 | Method for forming pad region of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0003544A KR100525116B1 (en) | 1999-02-03 | 1999-02-03 | Method for forming pad region of semiconductor device |
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| Publication Number | Publication Date |
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| KR20000055085A KR20000055085A (en) | 2000-09-05 |
| KR100525116B1 true KR100525116B1 (en) | 2005-11-01 |
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1999
- 1999-02-03 KR KR10-1999-0003544A patent/KR100525116B1/en not_active IP Right Cessation
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| KR20000055085A (en) | 2000-09-05 |
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