KR100508020B1 - Thin Film Transistor for Liquid Crystal Display - Google Patents

Abstract

The structure of the gate electrode of the thin film transistor used in the liquid crystal display device is formed to have a branch extending to one side, and the width of the drain electrode is formed wider than this branch so that the branch of the gate electrode and the drain electrode overlap. This causes electrons between the metal layers to be attracted to the center portion, thereby reducing the parasitic capacitance between the gate electrode and the drain electrode.

Description

Thin Film Transistor for Liquid Crystal Display

The present invention relates to a thin film transistor substrate of a liquid crystal display device.

The structure of a thin film transistor substrate of a general liquid crystal display device is shown in FIG. 1. A plurality of gate lines 11 and 12 and data lines 21 and 22 that cross each other are formed, and gate electrodes 11 are formed at branches of the gate line 11 adjacent to the intersection of the gate line 11 and the data line 21. 15), a thin film transistor including an amorphous silicon layer 30 and source / drain electrodes 25 and 26 is formed. In addition, a pixel electrode 40 made of a transparent conductive film is formed in each pixel defined by the intersection of the gate lines 11 and 12 and the data lines 21 and 22, and a storage electrode 50 for a storage capacitor is formed. .

2 illustrates a pixel equivalent circuit of a thin film transistor liquid crystal display. Here, the part indicated by the dotted line represents the parasitic capacitance between the gate and the drain.

만큼의 전압 시프트가 생기게 된다.When the liquid crystal display is driven, the liquid crystal capacitor Clc and the storage capacitor Cst act as loads to which the thin film transistor should be driven. When a positive pulse is applied to the gate electrode 150 connected thereto through the gate line 11, the thin film transistor is turned on, and at this time, the signal voltage applied to the source electrode 25 of the thin film transistor through the data line 21 is It flows through the amorphous silicon layer 30 to the drain electrode 26 and is then applied to the pixel electrode 40 which is one terminal of the liquid crystal capacitor Clc and the storage capacitor Cst. The signal voltage is maintained even after the gate voltage is turned off and applied to the liquid crystal. However, because of the parasitic capacitance between the gate and drain, the pixel voltage

There will be a voltage shift.

The voltage shift generated at this time is also referred to as kick-back, which causes problems such as afterimages and flicker.

In the thin film transistor substrate of FIG. 1, an overlapping structure between each electrode in a channel portion of a thin film transistor formed of a gate and a source / drain is shown in FIG. 3. That is, the gate line 15 is formed wide and the source electrode 25 and the drain electrode 26 overlap with each other.

At this time, since the width of the drain electrode 26 is smaller than the width of the gate line 15 positioned below it, the equipotential lines in the plane cut along the line IV-IV 'of FIG. 3 are shown in FIG. As shown in the drawing, the drain electrode is bent in the drain electrode direction. In addition, if the potential is measured along the line V-V 'of FIG. 4, the graph shown in FIG. 5 is obtained. That is, the potential of the edge portion of the drain electrode is higher than that of the center portion. The distribution of electrons at the overlapping portion of the gate electrode and the drain electrode is mainly dependent on the gate voltage, and especially at the high voltage at which the gate is turned on, as shown in FIG. The electrons migrate to the nearby amorphous silicon layer. Therefore, in addition to the plate capacity according to the plate overlap area A between the two metals, the parasitic capacity is increased because the effect of the edge is increased.

In the present invention, a parasitic capacitance between a gate and a drain electrode which generates a kickback voltage of a thin film transistor substrate of a liquid crystal display device is reduced.

In order to solve the above problems, the present invention forms a branch on the gate electrode. This branch is formed to be narrower in width in the drain electrode direction than the drain electrode so that the branch of the gate electrode and the drain electrode overlap.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

6 is a plan view of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 7 is an enlarged view of a gate electrode and a source / drain electrode of the thin film transistor portion of FIG. 6.

6 and 7, the horizontal gate lines 110 and 120 transmitting the scan signal and the vertical data lines 210 and 220 transmitting the image signal are insulated from each other and cross each other. The pixel electrode 400 is formed inside the display unit of the pixel defined by the intersection of the gate lines 110 and 120 and the data lines 210 and 220. The pixel electrode 400 is connected to the thin film transistor to receive an image signal from the data line 210. The storage electrode 500 for forming the storage capacitor is formed as part of the gate pattern.

Now, the structure of the thin film transistor will be described in detail.

The gate electrode 150 of the thin film transistor is a branch extending upward from the gate line 110, and a branch 160 having a width smaller than the width of the drain electrode 260 extends toward the drain electrode 260. . A gate insulating film (not shown) is formed on the gate electrode 150 and the branch 160, and an amorphous silicon layer 300 is formed thereon. On the amorphous silicon layer 300, a source electrode 250 and a drain electrode 260 connected to the data line 210 are formed to face each other with respect to the gate electrode 150. In addition, an amorphous silicon layer (not shown) heavily doped with n-type impurities is formed between the amorphous silicon layer 300, the source electrode 250, and the drain electrode 260 to form the amorphous silicon layer 300 and the source light drain. The contact resistance between the electrodes 250 and 260 is reduced. The drain electrode 260 and the gate electrode 150 overlap with the branch 160 of the gate electrode 150.

At this time, since a certain amount of current flowing from the source to the drain should be secured in a state where a voltage is applied, the width of the source electrode 250 is sufficiently wide.

In this way, the overlap area A 'of the drain electrode 260 and the gate electrode 150 is reduced, and the potential distribution between the drain electrode 260 and the gate electrode 150 is reversed to that according to the prior art.

8 is a cross-sectional view taken along the line VII-VII 'of FIG. 7 and an equipotential line in the cross-section. The equipotential lines between the gate electrode 150 and the drain electrode 260 are bent toward the gate electrode 150 as opposed to the case according to the prior art. The potential distribution from the center of the drain electrode 260 along the line VII-VII 'of FIG. 8 is shown in FIG. That is, the potential is the highest at the center of the drain electrode 260, and the potential is lowered toward the edge.

When the potential distribution is shown in FIG. 9, electrons between the two electrodes are driven to the overlapping portion of the gate electrode 150 and the drain electrode 260 having a high potential, and the electrons gathered at the overlapping portion contribute to the formation of a channel. It does not lead to an increase. That is, since electrons are collected in the center, even when a high voltage is applied to the gate electrode, the capacity of the edge portion is reduced as compared with the case of the related art.

As in the embodiment of the present invention, when the gate electrode is formed, electrons are concentrated at the center portion of the overlapping portion of the gate electrode and the drain electrode, thereby reducing the parasitic capacitance between the gate electrode and the drain electrode.

1 is a plan view of a thin film transistor substrate of a liquid crystal display according to the prior art,

FIG. 2 illustrates an equivalent circuit in pixel units of the thin film transistor liquid crystal display shown in FIG. 1;

3 is an enlarged view illustrating an electrode structure of the thin film transistor of FIG. 1;

FIG. 4 illustrates an equipotential line taken along a line IV-IV ′ of FIG. 3.

FIG. 5 is a graph showing the electric potential measured along the VV ′ line of FIG. 4;

6 is a plan view of a thin film transistor substrate of a liquid crystal display according to an exemplary embodiment of the present invention;

FIG. 7 is an enlarged view illustrating an electrode structure of the thin film transistor of FIG. 6;

FIG. 8 illustrates an equipotential line taken along a line VII-VII 'of FIG. 7,

FIG. 9 is a graph illustrating a potential measured along a line VII-VII 'of FIG. 8.

Claims (1)

Insulation board, A gate line extending in one direction on the insulating substrate, A gate electrode connected to the gate line and having a branch extending to one side; A semiconductor layer formed on the gate electrode and insulated from the gate electrode, A data line insulated from and intersecting the gate line; A source electrode connected to the data line and at least partially overlapping the gate electrode; And a drain electrode facing the source electrode around the gate electrode and overlapping a branch of the gate electrode and having a width wider than that of the branch of the gate electrode.

Images