KR100506973B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- KR100506973B1 KR100506973B1 KR10-1999-0003620A KR19990003620A KR100506973B1 KR 100506973 B1 KR100506973 B1 KR 100506973B1 KR 19990003620 A KR19990003620 A KR 19990003620A KR 100506973 B1 KR100506973 B1 KR 100506973B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- teos
- usg
- teos film
- deposited
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명에 따른 반도체소자의 제조방법을 제시한다. 본 발명은 화학기상증착 장치에서 유전체막으로 사용되는 O3 - TEOS막(또는 USG막) 증착하기 전에 소정의 서셉터 온도를 유지한 상태에서 먼저 오존이 제거된 순수한 TEOS막을 코딩하고나서 O3 - TEOS막(또는 USG막)을 증착한다.A method of manufacturing a semiconductor device according to the present invention is provided. The invention O 3 is used as a dielectric film in a chemical vapor deposition device after coding before depositing TEOS film (or USG film) while maintaining the predetermined susceptor temperature pure first ozone is removed TEOS film O 3 - A TEOS film (or USG film) is deposited.
따라서, O3 - TEOS막(또는 USG막) 증착시에 병행하게 되는 NH3 플라즈마 처리 공정을 생략할 수 있다. 또한, O3 - TEOS막(또는 USG막) 증착시에 소수성 폴리머의 흡착을 방해하는 요소가 제거됨으로서 표면 감수성을 개선시킬 수 있어 소자의 생산 수율을 향상시킨다.Therefore, the NH 3 plasma treatment step that is performed in parallel when the O 3 -TEOS film (or USG film) is deposited can be omitted. In addition, the surface susceptibility can be improved by eliminating the elements that hinder the adsorption of the hydrophobic polymer during deposition of the O 3 -TEOS film (or USG film), thereby improving the production yield of the device.
Description
본 발명은 반도체소자의 제조방법에 있어서 화학기상증착 장치에서의 유전체막 증착에 관한 것으로, 특히 O3 - TEOS막(또는 USG막(Undoped Silicate Glass)이라 함) 증착시에 표면 감수성을 개선하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the deposition of a dielectric film in a chemical vapor deposition apparatus in a method of manufacturing a semiconductor device, and in particular, to improve surface sensitivity during deposition of an O 3 -TEOS film (or USG film (Undoped Silicate Glass)). A method for manufacturing a semiconductor device.
일반적으로, 화학기상증착 장치에서의 유전체막(Dieletric Film)으로는 O3 - TEOS막(또는 USG막)을 사용한다. 이러한 유전체막은 하지막의 의존성이 강하다는 특성이 있다.In general, an O 3 -TEOS film (or USG film) is used as a dielectric film in a chemical vapor deposition apparatus. Such a dielectric film is characterized by a strong dependency of the underlying film.
특히, O3 - TEOS막의 표면 구성물 중에는 -OH기가 존재하는데 -OH기는 O3 - TEOS막(또는 USG막) 증착을 방해하여 높은 오존 농도에서 중간체로서의 폴리머를 생성시킨다. 이러한 폴리머는 소수성의 말단기를 가지고 있어 TEOS막의 반응에 의해 생성된 H2O가 친수성 표면에 흡착하여 소수성 폴리머의 흡착을 방해하게 된다.In particular, O 3 - TEOS film surface during the composition -OH group O 3 to -OH group is present - by interfering with the TEOS film (or USG film) deposited as an intermediate to produce a polymer at a high concentration of ozone. Such a polymer has a hydrophobic end group, so that H 2 O generated by the reaction of the TEOS membrane adsorbs on the hydrophilic surface, thereby preventing the adsorption of the hydrophobic polymer.
도 1 은 종래 반도체소자의 제조방법을 도시한 플로우차트이다.1 is a flowchart illustrating a method of manufacturing a conventional semiconductor device.
먼저, S10 단계에서는 반도체기판 상에 하지막으로 표면 산화막의 역할을 하는 HTO(High Temperature Oxidation : HTO)막을 증착한다.First, in step S10, a high temperature oxide (HTO) film, which serves as a surface oxide film, is deposited on the semiconductor substrate as a base film.
이어서, S20 단계에서는 챔버내의 서셉터(Susceptor)를 가열시켜 400℃의 온도 상태를 유지한다. Subsequently, in step S20, a susceptor in the chamber is heated to maintain a temperature of 400 ° C.
다음, S30 단계에서는 후속 공정의 O3 - TEOS막(또는 USG막)을 증착하기 전에 암모니아(NH3) 분위기에서 플라즈마 처리 공정을 실시한다.Next, in step S30, a plasma treatment process is performed in an ammonia (NH 3 ) atmosphere before depositing the O 3 -TEOS film (or USG film) of a subsequent process.
그 후, S40 단계에서는 유전체막으로 사용되는 O3 - TEOS막(또는 USG막)을 상기 하지막 상에 증착한다.Thereafter, in step S40, an O 3 -TEOS film (or USG film) used as a dielectric film is deposited on the base film.
상기와 같은 종래 기술에 따르면 다음과 같은 문제점을 유발시킨다.According to the prior art as described above causes the following problems.
유전체막으로 반도체기판의 하지막 상에 O3 - TEOS막(또는 USG막)을 증착하기 전에 소수성 폴리머의 흡착을 방해하는 요소를 제거하기 위해서는 반드시 NH3 플라즈마 처리 공정을 진행하여야 한다.Before the deposition of the O 3 -TEOS film (or USG film) on the underlayer of the semiconductor substrate with the dielectric film, the NH 3 plasma treatment process must be performed to remove the elements that hinder the adsorption of the hydrophobic polymer.
이는 유전체막으로서 O3 - TEOS막(또는 USG막)을 증착과는 별개로 NH3 플라즈마 처리공정을 진행해야하므로 공정 단계를 복잡하게 한다. 따라서, 소자의 생산 수율을 저하시킨다.This complicates the process step since the NH 3 plasma treatment process must be performed separately from the deposition of the O 3 -TEOS film (or USG film) as the dielectric film. Thus, the production yield of the device is lowered.
상기한 문제점을 해결하기 위한 본 발명의 목적은 O3 - TEOS막(또는 USG막) 증착시에 병행하게 되는 NH3 플라즈마 처리 공정을 생략하도록 한 반도체소자의 제조방법을 제공하는 데 있다.An object of the present invention for solving the above problems is to provide a method for manufacturing a semiconductor device to omit the NH 3 plasma treatment process that is performed in parallel when the O 3 -TEOS film (or USG film) deposition.
본 발명의 다른 목적은 O3 - TEOS막(또는 USG막) 증착시에 표면 감수성을 개선하도록 한 반도체소자의 제조방법을 제공하는 데 있다.Another object of the present invention is to provide a method for manufacturing a semiconductor device to improve the surface sensitivity when depositing an O 3 -TEOS film (or USG film).
상기한 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은The semiconductor device manufacturing method according to the present invention to achieve the above object is
반도체기판에 하지막을 증착하는 단계;Depositing a base film on a semiconductor substrate;
상기 하지막 상에 순수한 TEOS막을 코팅하는 단계; 및Coating a pure TEOS film on the base film; And
상기 TEOS막 상에 O3 - TEOS막을 증착하는 단계를 포함한다.And depositing an O 3 -TEOS film on the TEOS film.
이 때, 상기 TEOS막 및 O3 - TEOS막은 430 ∼ 470℃의 서셉터 온도에서 증착됨이 바람직하다.At this time, the TEOS film and the O 3 -TEOS film is preferably deposited at a susceptor temperature of 430 ~ 470 ℃.
상기한 본 발명에 따르면, 화학기상장치에서의 유전체막으로 먼저 순수한 TEOS막을 코팅하고나서 O3 - TEOS막(또는 USG막)을 증착함으로서 O3 - TEOS막(또는 USG막) 증착시에 병행하게 되는 NH3 플라즈마 처리 공정을 생략하도록 하여 유전체막의 표면 감수성을 개선시킬 수 있다.According to the present invention as described above, a pure TEOS film is first coated with a dielectric film in a chemical vapor apparatus, and then an O 3 -TEOS film (or USG film) is deposited in parallel to deposit an O 3 -TEOS film (or USG film). The surface susceptibility of the dielectric film can be improved by omitting the NH 3 plasma treatment step.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체소자의 제조방법에 대하여 상세하게 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2 는 본 발명에 따른 반도체소자의 제조방법을 도시한 플로우차트이다.2 is a flowchart illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, S50 단계에서는 반도체기판 상에 하지막으로 표면 산화막의 역할을 하는 HTO막을 증착한다.First, in step S50 is deposited on the semiconductor substrate HTO film serving as a surface oxide film as a base film.
이어서, S60 단계에서는 갭필(Gap Fill) 및 거칠기(Roughness)를 향상시킬 수 있도록 서셉터(Susceptor)를 가열하여 430℃ ∼ 470℃ 상태로 유지한다. 이 때, 서셉터 온도를 종래 500℃의 서셉터 온도 보다 낮은 상태로 유지함으로서 후속 공정의 O3 - TEOS막(또는 USG막) 증착시에 하지막에 대한 영향을 최소화할 수 있다.Subsequently, in step S60, a susceptor is heated to maintain a gap fill and roughness at 430 ° C. to 470 ° C. so as to improve gap fill and roughness. At this time, by maintaining the susceptor temperature lower than the susceptor temperature of the conventional 500 ℃ can minimize the effect on the underlying film during the deposition of the O 3 -TEOS film (or USG film) of the subsequent process.
다음, S70 단계에서는 소수성의 말단기 생성을 저지할 수 있도록 먼저 오존을 제거한 순수한 재질의 TEOS막을 하지막 상에 증착한다.Next, in step S70, in order to prevent the generation of hydrophobic end groups, a TEOS film made of pure ozone is first deposited on the underlying film.
이 때, 순수한 TEOS막이 증착됨으로서 후속 공정의 O3 - TEOS막(또는 USG막) 증착시 소수성 폴리머의 흡착 방해 요소를 제거할 수 있다. 또한, 종래 O3 - TEOS막(또는 USG막)을 증착하기 전에 필수적으로 병행하게 되는 암모니아(NH3) 분위기에서의 플라즈마 처리 공정을 생략할 수 있다.At this time, since the pure TEOS film is deposited, it is possible to remove the adsorption blocking element of the hydrophobic polymer during the deposition of the O 3 -TEOS film (or USG film) in a subsequent process. In addition, the plasma treatment process in an ammonia (NH 3 ) atmosphere which is essentially parallel to the conventional deposition of the O 3 -TEOS film (or USG film) can be omitted.
그 후, S80 단계에서는 순수한 TEOS막이 코딩된 상태에서 O3 - TEOS막(또는 USG막)을 증착함으로서 유전체막의 형성 공정이 완료된다.Thereafter, in step S80, the process of forming the dielectric film is completed by depositing an O 3 -TEOS film (or USG film) in the state where the pure TEOS film is coded.
상기한 본 발명에 따르면, 유전체막으로 O3 - TEOS막(또는 USG막) 증착시에 먼저 430℃ ∼ 470℃의 서셉터 온도를 유지한 상태에서 먼저 순수한 TEOS막을 코팅하고나서 O3 - TEOS막(또는 USG막)을 증착함으로서 유전체막의 증착시에 병행하게 되는 NH3 플라즈마 처리 공정을 생략할 수 있다.According to the present invention described above, when the O 3 -TEOS film (or USG film) is deposited as a dielectric film, the pure TEOS film is first coated with a susceptor temperature of 430 ° C to 470 ° C, and then the O 3 -TEOS film By depositing (or USG film), the NH 3 plasma treatment step that is performed in parallel with the deposition of the dielectric film can be omitted.
이상에서와 같이 본 발명에 따르면, 화학기상증착 장치에서 유전체막으로 사용되는 O3 - TEOS막(또는 USG막) 증착하기 전에 430℃ ∼ 470℃의 서셉터 온도를 유지한 상태에서 먼저 오존이 제거된 순수한 재질의 TEOS막을 코딩하고나서 O3 - TEOS막(또는 USG막)을 증착한다.As described above, according to the present invention, ozone is first removed while maintaining a susceptor temperature of 430 ° C to 470 ° C before deposition of the O 3 -TEOS film (or USG film) used as the dielectric film in the chemical vapor deposition apparatus. After the TEOS film was made of pure material, an O 3 -TEOS film (or USG film) was deposited.
따라서, O3 - TEOS막(또는 USG막) 증착시에 병행하게 되는 NH3 플라즈마 처리 공정을 생략할 수 있다. 또한, O3 - TEOS막(또는 USG막) 증착시에 소수성 폴리머의 흡착을 방해하는 요소가 제거됨으로서 표면 감수성을 개선시킬 수 있어 소자의 생산 수율을 향상시킨다.Therefore, the NH 3 plasma treatment step that is performed in parallel when the O 3 -TEOS film (or USG film) is deposited can be omitted. In addition, the surface susceptibility can be improved by eliminating the elements that hinder the adsorption of the hydrophobic polymer during deposition of the O 3 -TEOS film (or USG film), thereby improving the production yield of the device.
도 1 은 종래 반도체소자의 제조 공정을 도시한 플로우차트1 is a flowchart showing a manufacturing process of a conventional semiconductor device
도 2 는 본 발명에 따른 반도체소자의 제조 공정을 도시한 플로우차트2 is a flowchart illustrating a manufacturing process of a semiconductor device according to the present invention.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-1999-0003620A KR100506973B1 (en) | 1999-02-03 | 1999-02-03 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-1999-0003620A KR100506973B1 (en) | 1999-02-03 | 1999-02-03 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20000055158A KR20000055158A (en) | 2000-09-05 |
KR100506973B1 true KR100506973B1 (en) | 2005-08-09 |
Family
ID=19573264
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-1999-0003620A KR100506973B1 (en) | 1999-02-03 | 1999-02-03 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100506973B1 (en) |
-
1999
- 1999-02-03 KR KR10-1999-0003620A patent/KR100506973B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20000055158A (en) | 2000-09-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102403102B1 (en) | semiconductor processing equipment | |
US10204782B2 (en) | Combined anneal and selective deposition process | |
US20010050039A1 (en) | Method of forming a thin film using atomic layer deposition method | |
KR100624903B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
KR100323874B1 (en) | Method of forming an aluminum oxide film in a semiconductor device | |
US9570287B2 (en) | Flowable film curing penetration depth improvement and stress tuning | |
JPH1187341A (en) | Film formation and film-forming apparatus | |
KR20030084125A (en) | Process for depositing insulating film on substrate at low temperature | |
US20010039125A1 (en) | Method for making an insulating film | |
KR100506973B1 (en) | Method for manufacturing semiconductor device | |
KR0172031B1 (en) | Layer insulation film forming method of semiconductor device | |
JPH08203894A (en) | Fabrication of semiconductor device | |
KR101082921B1 (en) | Method for forming silicon oxide layer of semiconductor device | |
CN103943465A (en) | Preparation method of silicon oxide film | |
KR100318456B1 (en) | A method for forming tantalum oxide capacitor in semiconductor device | |
KR20010088207A (en) | Method of forming composite dielectric film of tantalum oxide and titanium oxide | |
KR100511914B1 (en) | Method for fabricating of semiconductor device using PECYCLE-CVD | |
KR20030064083A (en) | A Method Of Forming Silicon Nitride Thin Film by Atomic Layer Deposition | |
KR100467475B1 (en) | Capacitor Formation Method of Semiconductor Device | |
KR20030058271A (en) | Atomic layer deposition process using plasma | |
KR20160120511A (en) | Method of fabricating semiconductor device | |
KR100470129B1 (en) | Method for the preparation of thin film transistor having improved interface property | |
KR100414749B1 (en) | Method for manufacturing diffusion barrier layer of semiconductor device | |
JPH06252133A (en) | Manufacture of semiconductor device | |
JP2629587B2 (en) | Method for manufacturing semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
LAPS | Lapse due to unpaid annual fee |