KR100470129B1 - Method for the preparation of thin film transistor having improved interface property - Google Patents
Method for the preparation of thin film transistor having improved interface property Download PDFInfo
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- KR100470129B1 KR100470129B1 KR10-2002-0004378A KR20020004378A KR100470129B1 KR 100470129 B1 KR100470129 B1 KR 100470129B1 KR 20020004378 A KR20020004378 A KR 20020004378A KR 100470129 B1 KR100470129 B1 KR 100470129B1
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- 239000010409 thin film Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims abstract description 13
- 239000010408 film Substances 0.000 claims abstract description 87
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims abstract description 18
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 18
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000001301 oxygen Substances 0.000 claims abstract description 9
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims description 11
- 238000009832 plasma treatment Methods 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 230000007704 transition Effects 0.000 abstract description 18
- 230000007547 defect Effects 0.000 abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000004458 analytical method Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Abstract
본 발명은 계면특성이 우수한 박막 트랜지스터의 제조방법에 관한 것으로서, 폴리실리콘 반도체막 위에 이산화규소 절연막을 1차 증착시킨 다음, 증착된 절연막을 산소, 질소 또는 산화질소로 플라즈마 처리하고, 이어서 절연막을 추가로 증착시키는 본 발명의 방법에 따르면, 반도체막과 절연막 간의 계면부 및 전이영역의 결함을 감소시키고 전기적 화학적 특성을 개선시켜 우수한 전기적 특성을 갖는 박막 트랜지스터를 제조할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor having excellent interfacial properties, wherein a silicon dioxide insulating film is first deposited on a polysilicon semiconductor film, and the deposited insulating film is plasma treated with oxygen, nitrogen, or nitrogen oxide, and then an insulating film is added. According to the method of the present invention, the thin film transistor having excellent electrical properties can be manufactured by reducing defects in the interface portion and transition region between the semiconductor film and the insulating film and improving the electrochemical properties.
Description
본 발명은 계면특성이 우수한 박막 트랜지스터의 제조방법에 관한 것으로서, 구체적으로는 반도체막 위에 절연막을 증착시키는 중간에 플라즈마 처리를 수행함으로써, 반도체막과 절연막 간의 계면부 및 전이영역의 결함을 감소시키고 전기적화학적 특성을 개선시켜 우수한 계면 특성을 가지는 박막 트랜지스터를 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor having excellent interfacial properties. Specifically, the plasma treatment is performed in the middle of depositing an insulating film on a semiconductor film, thereby reducing defects in the interface and transition region between the semiconductor film and the insulating film. The present invention relates to a method of manufacturing a thin film transistor having improved interfacial properties by improving chemical properties.
일반적인 박막 트랜지스터는 다층으로 구성되며, 반도체막, 절연막, 보호막 및 전극 등을 포함한다. 폴리실리콘 반도체막 및 이산화규소 절연막을 포함하는 박막 트랜지스터를 제조함에 있어서, 플라즈마 화학증착법을 이용하여 반도체막 위에 이산화규소 절연막을 증착시키는 경우 플라즈마에 의한 계면의 결함(damage)을 최소화하고 두 막 사이의 계면특성을 개선시키고자 하는 다양한 노력이 계속적으로 진행되어 왔다.A general thin film transistor is composed of a multilayer and includes a semiconductor film, an insulating film, a protective film, an electrode, and the like. In manufacturing a thin film transistor including a polysilicon semiconductor film and a silicon dioxide insulating film, in the case of depositing a silicon dioxide insulating film on the semiconductor film by using plasma chemical vapor deposition, the interface between the two films is minimized while minimizing the damage of the interface by the plasma. Various efforts have been made to improve the interfacial properties.
반도체막과 절연막 간의 계면특성을 개선하기 위한 일환으로서, 원격(remote) 플라즈마 화학증착법 및 전자-사이클로트론 공명(electron-cyclotron resonance) 플라즈마 화학증착법과 같은 다양한 증착법을 적용하거나, 또는 절연막 증착에 앞서 반도체막의 표면을 수소 또는 산소 등으로 플라즈마 처리하는 방법이 소개되었다.As part of improving the interfacial properties between the semiconductor film and the insulating film, various deposition methods such as remote plasma chemical vapor deposition and electron-cyclotron resonance plasma chemical vapor deposition may be applied, or the semiconductor film may be deposited before the insulating film is deposited. A method of plasma treating a surface with hydrogen or oxygen has been introduced.
그러나, 상기한 증착법에 사용되는 기구들은 대면적의 기판에 적용하기에는 한계가 있어 실제 TFT-LCD 등의 기판에 적용이 불가능하다는 문제점을 가진다. 또한, 상기한 표면 전처리방법은 그 개선효과가 미비하여 실공정에 거의 적용되지 못하고 있는 실정이다.However, the apparatuses used in the above deposition method have a problem in that it is impossible to apply to a substrate such as a TFT-LCD because there is a limit to apply to a large-area substrate. In addition, the above-described surface pretreatment method is a situation that is hardly applied to the actual process because the improvement effect is insignificant.
이에 본 발명자들은 예의 연구한 결과, 폴리실리콘 반도체막 위에 이산화규소 절연막을 증착시키는 중간에 플라즈마 처리를 수행함으로써, 반도체막과 절연막 간의 계면부 및 전이영역의 결함을 감소시키고 전기적 화학적 특성을 개선시켜 우수한 계면특성을 가지는 박막 트랜지스터를 제조할 수 있음을 발견하고 본 발명을 완성하게 되었다.Accordingly, the present inventors earnestly studied, and by performing a plasma treatment in the middle of depositing a silicon dioxide insulating film on a polysilicon semiconductor film, it is possible to reduce the defects of the interface portion and the transition region between the semiconductor film and the insulating film and to improve the electrochemical properties The present invention has been accomplished by discovering that a thin film transistor having interfacial properties can be manufactured.
본 발명의 목적은 폴리실리콘 반도체막과 이산화규소 절연막 간의 계면특성이 우수한 박막 트랜지스터의 제조방법을 제공하는 것이다.An object of the present invention is to provide a method for manufacturing a thin film transistor having excellent interface characteristics between a polysilicon semiconductor film and a silicon dioxide insulating film.
도 1은 본 발명에 따른 절연막 증착공정을 단계별로 보여주는 개략도이고;1 is a schematic view showing step by step an insulating film deposition process according to the present invention;
도 2a 내지 2c 각각은, 실시예 1, 2 및 비교예 각각에서 얻어진, 반도체막과 절연막 간의 계면부 및 전이영역(transition region)에 대해 XPS(X-ray Photoelectron Spectroscopy) 분석한 결과 그래프를 나타내며;2A to 2C each show graphs of the results of X-ray Photoelectron Spectroscopy (XPS) analysis on the interface region and transition region between the semiconductor film and the insulating film obtained in Examples 1, 2 and Comparative Examples, respectively;
도 3a 및 3b 각각은, 실시예 1 및 2에 있어서, 플라즈마 처리 이전에 증착시키는 절연막의 두께 변화에 따른 반도체막과 절연막 간의 계면부의 계면 결함 밀도 및 플랫밴드(flat band) 전이 변화 그래프 각각을 나타낸다.3A and 3B respectively show graphs of change in the interface defect density and flat band transition between the interface portion between the semiconductor film and the insulating film according to the thickness change of the insulating film deposited before the plasma treatment in Examples 1 and 2; .
상기 목적을 달성하기 위하여 본 발명에서는, 폴리실리콘 반도체막 및 이산화규소 절연막을 포함하는 박막 트랜지스터를 제조함에 있어서, 반도체막 위에 절연막을 1차 증착시킨 다음, 증착된 절연막을 산소, 질소 또는 산화질소로 플라즈마 처리하고, 이어서 절연막을 추가로 증착시키는 것을 특징으로 하는, 박막 트랜지스터의 제조방법을 제공한다.In order to achieve the above object, in the present invention, in manufacturing a thin film transistor including a polysilicon semiconductor film and a silicon dioxide insulating film, by first depositing an insulating film on the semiconductor film, the deposited insulating film to oxygen, nitrogen or nitrogen oxide A plasma treatment, followed by further depositing an insulating film, provides a method for producing a thin film transistor.
이하 본 발명에 대하여 보다 상세히 설명한다.Hereinafter, the present invention will be described in more detail.
본 발명의 방법은 이산화규소 절연막 증착 도중에 산소, 질소 또는 산화질소로 플라즈마 처리를 수행함으로써 절연막을 두 번에 나누어 증착시키는 것을 기술구성상 특징으로 한다.The method of the present invention is characterized by a technical configuration of depositing the insulating film in two portions by performing a plasma treatment with oxygen, nitrogen or nitrogen oxide during the deposition of the silicon dioxide insulating film.
본 발명에 따른 절연막 증착공정을 단계별로 보여주는 개략도를 도 1에 나타내었다. 도 1에 도시된 공정을 살펴보면, 단계 1)에서는 예를 들어, TEOS(테트라에톡시실란)/O2반응기체를 폴리실리콘 반도체막 위에 플라즈마 화학증착시켜 이산화규소 절연막을 형성하는데, 이때 형성하는 절연막의 두께는 추후 단계에서의 플라즈마 처리가 반도체막과 절연막 간의 계면부에까지 영향을 미칠 수 있게 하는 3 내지 9nm의 범위가 바람직하다. 상기한 절연막의 플라즈마 화학증착은 통상적으로 100 내지 500℃ 및 0.1 내지 10 torr의 조건 하에서 수행될 수 있다.A schematic diagram showing step by step an insulating film deposition process according to the present invention is shown in FIG. 1. Referring to the process illustrated in FIG. 1, in step 1), for example, a TEOS (tetraethoxysilane) / O 2 reactor is plasma-chemically deposited on a polysilicon semiconductor film to form a silicon dioxide insulating film. The thickness of is preferably in the range of 3 to 9 nm, which allows the plasma treatment in a later step to affect the interface between the semiconductor film and the insulating film. Plasma chemical vapor deposition of the insulating film can be carried out under the conditions of 100 to 500 ℃ and 0.1 to 10 torr typically.
단계 2)에서는, 증착된 절연막을 산소, 질소 또는 산화질소로 플라즈마 처리하여 플라즈마에 의해 이온화되거나 활성화된 라디칼들을 절연막에 침투시켜 계면부 및 전이영역까지 도달시킴으로써, 계면부 및 전이영역의 화학적 결합을 보다 치밀하게 하고 미반응 및 불완전반응된 실리콘의 산화상태를 우수하게 하여, 결함 상태가 많이 존재하는 전이영역의 두께를 감소시킨다.In step 2), the deposited insulating film is plasma treated with oxygen, nitrogen, or nitrogen oxide to infiltrate the insulating film with radicals ionized or activated by the plasma to reach the interface portion and the transition region, thereby chemically bonding the interface portion and the transition region. The denser and better oxidation state of unreacted and incompletely reacted silicon reduces the thickness of the transition region in which many defect states exist.
이러한 산소, 질소 또는 산화질소로의 플라즈마 처리는 100 내지 500℃ 및 0.1 내지 100 torr 하에서 10초 내지 10분 동안 수행될 수 있다.Such plasma treatment with oxygen, nitrogen or nitrogen oxide may be performed for 10 seconds to 10 minutes under 100 to 500 ℃ and 0.1 to 100 torr.
이어, 단계 3)에서는, 이산화규소 절연막을 상기 단계 1)에서와 동일한 조건하에서 원하는 두께까지 추가로 증착시켜 절연막의 증착을 완료한다. 통상적으로, 형성된 절연막은 50 내지 200nm의 두께를 가진다.Subsequently, in step 3), the silicon dioxide insulating film is further deposited to a desired thickness under the same conditions as in step 1) to complete deposition of the insulating film. Typically, the formed insulating film has a thickness of 50 to 200 nm.
이와 같이 형성된 폴리실리콘 반도체막 및 이산화규소 절연막(게이트 절연막) 위에 게이트막, 층간 절연막 및 전극을 통상적인 방법에 따라 차례로 형성시켜 박막 트랜지스터를 제조할 수 있다.A thin film transistor can be fabricated by sequentially forming a gate film, an interlayer insulating film, and an electrode on the polysilicon semiconductor film and the silicon dioxide insulating film (gate insulating film) thus formed in accordance with a conventional method.
본 발명의 방법에 따라 제조된 박막 트랜지스터는 결함이 감소되고 전기적화학적 특성이 개선된, 폴리실리콘 반도체막과 이산화규소 절연막 간의 계면부 및 전이영역을 포함하므로 우수한 전기적 특성을 나타낸다.The thin film transistor fabricated according to the method of the present invention exhibits excellent electrical properties because it includes an interface portion and a transition region between the polysilicon semiconductor film and the silicon dioxide insulating film, which have reduced defects and improved electrochemical properties.
이하, 본 발명을 하기 실시예에 의거하여 좀더 상세하게 설명하고자 한다. 단, 하기 실시예는 본 발명을 예시하기 위한 것일 뿐, 본 발명의 범위가 이들만으로 제한되는 것은 아니다.Hereinafter, the present invention will be described in more detail based on the following examples. However, the following examples are only for illustrating the present invention, and the scope of the present invention is not limited thereto.
실시예 1Example 1
실리콘 기판 위에 형성된 폴리실리콘 반도체막 위에, 350℃ 및 1 torr 조건 하에서 TEOS/O2반응기체를 플라즈마 화학증착시켜 이산화규소 절연막을 형성하였다. 이때, 형성되는 절연막의 두께를 0, 3, 6, 9 및 12nm로 변화시켰다. 증착된 절연막을 350℃ 및 1 torr 하에서 산소로 1분 동안 플라즈마 처리한 다음, 절연막의 증착을 다시 수행하여 두께 100nm의 이산화규소 절연막을 형성하였다.On the polysilicon semiconductor film formed on the silicon substrate, TEOS / O 2 reactor body was plasma chemically deposited at 350 ° C. and 1 torr conditions to form a silicon dioxide insulating film. At this time, the thickness of the insulating film formed was changed to 0, 3, 6, 9 and 12 nm. The deposited insulating film was plasma treated with oxygen at 350 ° C. and 1 torr for 1 minute, and then the insulating film was deposited again to form a silicon dioxide insulating film having a thickness of 100 nm.
실시예 2Example 2
산소 대신에 질소를 사용하여 플라즈마 처리한 것을 제외하고는, 상기 실시예 1과 동일한 방법을 수행하여 두께 100nm의 이산화규소 절연막을 형성하였다.A silicon dioxide insulating film having a thickness of 100 nm was formed in the same manner as in Example 1, except that the plasma treatment was performed using nitrogen instead of oxygen.
비교예Comparative example
실리콘 기판 위에 형성된 폴리실리콘 반도체막 위에, 350℃ 및 1 torr 조건하에서 TEOS/O2반응기체를 플라즈마 화학증착시켜 두께 100nm의 이산화규소 절연막을 한번에 형성하였다.On the polysilicon semiconductor film formed on the silicon substrate, a TEOS / O 2 reactor body was plasma chemically deposited at 350 ° C. and 1 torr conditions to form a silicon dioxide insulating film having a thickness of 100 nm at one time.
XPS(X-ray Photoelectron Spectroscopy) 분석X-ray photoelectron spectroscopy (XPS) analysis
상기 실시예 1, 2 및 비교예 각각에서 얻어진, 반도체막과 절연막 간의 계면부 및 전이영역(transition region)에 대해 XPS 분석을 수행하여, 그 결과를 도 2a 내지 2c 및 하기 표 1에 나타내었다. 이때, 도 2 및 표 1의 결과값은 실시예 1 및 2에서 플라즈마 처리 이전에 형성된 절연막의 두께가 6nm인 것에 대한 데이터이다.XPS analysis was performed on the interface portion and transition region between the semiconductor film and the insulating film obtained in each of Examples 1, 2 and Comparative Examples, and the results are shown in FIGS. 2A to 2C and Table 1 below. 2 and Table 1 show data for the thickness of the insulating film formed in Example 1 and 2 before the plasma treatment is 6 nm.
도 2a 내지 2c의 그래프에서, Six+의 x는 실리콘에 결합되어 있는 산소 원자 수를 의미하므로, 실시예 1 및 2의 계면부 및 전이영역의 실리콘의 산화 상태가 비교예보다 더 우수함을 알 수 있다.In the graphs of FIGS. 2A to 2C, since x in Si x + means the number of oxygen atoms bonded to silicon, it can be seen that the oxidation state of silicon in the interface portion and the transition region of Examples 1 and 2 is better than that of the comparative example. have.
아울러, 상기 표 1로부터 알 수 있듯이, 실시예 1 및 2의 전이영역의 실리콘 원자의 표면 밀도가 비교예보다 더 작으며, 이는 전이영역의 두께가 감소했음을 의미한다. 또한, 실시예 1 및 2의 경우, 비교예의 경우보다 θ3의 값이 더 커서 전이영역내에서 실리콘의 산화 상태가 보다 우수함을 알 수 있다.In addition, as can be seen from Table 1, the surface density of the silicon atoms in the transition region of Examples 1 and 2 is smaller than the comparative example, which means that the thickness of the transition region is reduced. In addition, in the case of Examples 1 and 2, the value of θ 3 is greater than that of the comparative example, and it can be seen that the oxidation state of silicon is better in the transition region.
최초 절연막의 두께에 따른 계면 결함 정도 분석Analysis of Interfacial Defects According to Thickness of Initial Insulator
상기 실시예 1 및 2에 있어서, 플라즈마 처리 이전에 증착시키는 절연막(최초 절연막)의 두께 변화에 따른 반도체막과 절연막 간의 계면부의 계면 결함 밀도 및 플랫밴드(flat band) 전이 변화를 측정하여, 그 결과를 도 3a 및 3b에 각각 나타내었다.In Examples 1 and 2, the interface defect density and the flat band transition change of the interface portion between the semiconductor film and the insulating film according to the thickness change of the insulating film (first insulating film) deposited before the plasma treatment were measured, and the result Are shown in FIGS. 3A and 3B, respectively.
도 3a 및 3b에 있어서, 계면 결함 밀도 및 플랫밴드 전이는 최초 절연막의 두께에 따라 계속 변하는데, 두께 3 내지 9nm에 해당하는 영역에서 계면 결함의 감소가 두드러짐을 알 수 있으며(도 3a), 절연막 내에 양으로 대전된 결함이 증가할수록 음으로 이동하는 플랫밴드 전위 역시 두께 3 내지 9nm에 해당하는 영역에서 0V(이상적인 플랫밴드 전위값)에 가깝게 측정됨을 알 수 있다(도 3b).In FIGS. 3A and 3B, the interfacial defect density and flat band transition continue to change with the thickness of the initial insulating film, and it can be seen that the reduction of the interfacial defects is prominent in the region corresponding to the thickness of 3 to 9 nm (FIG. 3A). It can be seen that as the positively charged defects increase, negatively moving flatband dislocations are also measured to be close to 0V (ideal flatband dislocation values) in a region corresponding to 3 to 9 nm in thickness (FIG. 3B).
이와 같이, 본 발명의 방법에 의하면, 폴리실리콘 반도체막과 이산화규소 절연막 간의 계면부 및 전이영역의 결함이 감소되고 전기적 화학적 특성이 개선되므로, 이를 포함하는 박막 트랜지스터는 우수한 전기적 특성을 나타낼 수 있다.As described above, according to the method of the present invention, the defects in the interface portion and the transition region between the polysilicon semiconductor film and the silicon dioxide insulating film are reduced and the electrochemical properties are improved, and thus the thin film transistor including the same may exhibit excellent electrical properties.
Claims (5)
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| KR970030863A (en) * | 1995-11-20 | 1997-06-26 | 김주용 | Method for manufacturing gate insulating film of thin film transistor |
| KR970052338A (en) * | 1995-12-23 | 1997-07-29 | 김주용 | Manufacturing method of semiconductor device |
| JP2000068261A (en) * | 1998-08-19 | 2000-03-03 | Toshiba Corp | Manufacture of semiconductor device |
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| JPH08186170A (en) * | 1994-12-28 | 1996-07-16 | Kawasaki Steel Corp | Manufacture of semiconductor device |
| KR970030863A (en) * | 1995-11-20 | 1997-06-26 | 김주용 | Method for manufacturing gate insulating film of thin film transistor |
| KR970052338A (en) * | 1995-12-23 | 1997-07-29 | 김주용 | Manufacturing method of semiconductor device |
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