KR100499635B1 - Method for patternning of wordline - Google Patents

Method for patternning of wordline Download PDF

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KR100499635B1
KR100499635B1 KR10-2002-0088140A KR20020088140A KR100499635B1 KR 100499635 B1 KR100499635 B1 KR 100499635B1 KR 20020088140 A KR20020088140 A KR 20020088140A KR 100499635 B1 KR100499635 B1 KR 100499635B1
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word line
device isolation
active region
forming
isolation layer
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KR10-2002-0088140A
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KR20040061840A (en
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박상원
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명의 반도체 소자의 워드라인 패터닝 방법은 트렌치 소자 분리 공정으로 반도체 기판을 활성영역과 비활성영역으로 구분하는 제 1 공정; 상기 비활성영역에 소자 분리형 산화막을 증착하여 소자 분리막을 형성하는 제 2공정; 상기 활성영역과 소자 분리막 상부에 게이트 산화막과 워드라인 형성물질을 순차적으로 증착하는 제 3공정; 및 상기 활성영역 상의 워드라인과 상기 소자 분리막 상의 워드라인이 서로 다른 폭을 갖도록 형성된 마스크를 이용하여 상기 산화막과 워드라인용 물질을 제거하여 워드라인을 형성하는 제 4공정을 통해 활성화 영역의 워드라인과 비활성화 영역의 워드라인의 폭을 달리 형성함으로써, 랜딩 플러그 콘택 면적을 증가시켜 셀에 저장되는 전하량의 손실을 줄이고 기생 트랜지스터의 생성을 막아 데이터 보유 시간을 향상시키게 된다.A word line patterning method of a semiconductor device of the present invention may include a first process of dividing a semiconductor substrate into an active region and an inactive region by a trench device isolation process; Forming a device isolation layer by depositing a device isolation oxide film in the inactive region; A third process of sequentially depositing a gate oxide layer and a word line forming material on the active region and the device isolation layer; And a word line of the active region through a fourth process of forming a word line by removing the oxide layer and the word line material by using a mask formed such that the word line on the active region and the word line on the device isolation layer have different widths. By forming different widths of the word lines of the and inactive regions, the landing plug contact area is increased to reduce the amount of charge stored in the cell and to prevent generation of parasitic transistors, thereby improving data retention time.

Description

반도체 소자의 워드라인 패터닝 방법{Method for patternning of wordline}Word line patterning method for semiconductor devices {Method for patternning of wordline}

본 발명은 반도체 소자의 워드라인 패터닝 방법에 관한 것으로, 보다 상세하게는, 워드라인을 이중 폭으로 형성하여 랜딩 플러그 콘택(Landing Plug Contact)의 면적을 기존 보다 크게 확보하여 콘택 저항을 줄여줌으로서, 셀에 저장되는 전하량의 손실을 줄이고 기생 트랜지스터의 생성을 막아 데이터 보유 시간(Retention time)을 향상시켜 반도체 소자의 신뢰성을 향살시킬 수 있는 워드라인 패터닝 방법에 관한 것이다.The present invention relates to a word line patterning method of a semiconductor device, and more particularly, by forming a word line in a double width to reduce the contact resistance by securing a larger area of the landing plug contact than before, The present invention relates to a word line patterning method capable of improving reliability of a semiconductor device by reducing loss of charge stored in a cell and preventing generation of parasitic transistors to improve data retention time.

반도체 소자 설계에서 디자인 룰이 점점 작아짐에 따라 랜딩 플러그 콘택의 면적이 작아지게 됨으로써, 충분한 랜딩 플러그 콘택 면적을 확보하기 위해 워드라인과 활성영역의 중첩이 커지고 있다.As design rules become smaller in semiconductor device design, the area of the landing plug contact becomes smaller, so that the overlap of the word line and the active area is increased to secure a sufficient landing plug contact area.

이로 인해, 기생 트랜지스터에 의한 영향이 커지게 되어 셀의 데이터 보유 시간이 줄어들고 있다.As a result, the influence of parasitic transistors is increased and the data retention time of the cell is reduced.

도 1은 종래 고집적 반도체 소자 공정을 이용하여 반도체 기판에 워드라인 WL1 ∼ WL4이 형성된 모습을 보여주는 평면도이다.FIG. 1 is a plan view illustrating the formation of word lines WL1 to WL4 on a semiconductor substrate using a conventional highly integrated semiconductor device process.

도 1에서 활성영역(2)은 활성영역(2)과 워드라인 WL1이 X축으로 잘못 정렬되어도 랜딩 플러그 콘택의 면적(4)을 최대한 확보하기 위해 활성영역(2)을 이웃한 워드라인 WL1 및 WL4와 일정 부분이 겹쳐지도록 길게 형성된다.In FIG. 1, the active area 2 includes the word line WL1 adjacent to the active area 2 to maximize the area 4 of the landing plug contact even when the active area 2 and the word line WL1 are misaligned on the X axis. It is formed long so that a portion overlaps with WL4.

디자인 룰이 클 때는 워드라인의 폭에 비해 활성영역과 워드라인이 겹쳐진 부분(3, 5)이 많지 않아 이처럼 겹쳐진 부분에 의한 기생 트랜지스터의 영향을 받지 않게된다. 그러나, 디자인 룰이 작아지면서 워드라인 폭이 좁아져 활성영역이 이웃하는 워드라인과 겹쳐진 부분이 워드라인의 폭에 비해 무시될 수 없을 정도로 크게 되어 기생 트랜지스터의 영향으로 인해 리프레쉬 특성을 악화시키게 된다.When the design rule is large, there are not many portions (3, 5) where the active region and the word lines overlap with the width of the word lines, so that the parasitic transistors are not affected by the overlapping portions. However, as the design rule decreases, the width of the word line is narrowed, and the portion where the active region overlaps with the neighboring word line becomes large enough to be ignored compared to the width of the word line, thereby degrading the refresh characteristic due to the influence of the parasitic transistor.

예컨대, 도 1에서 워드라인 WL1만 선택되었을 경우 기생 트랜지스터(5)가 턴 온 될 수 있고, 기생 트랜지스터(5)가 턴 온 되면, GIDL(Gate Induced Drain Current Leakage)가 발생하여 셀(6)에 저장되어 있던 전하가 누설된다. 그로인해, 셀(6)에 저장되어 있는 데이터의 보유 시간이 줄어들게 되어 리프레쉬 특성을 저하시킨다.For example, when only the word line WL1 is selected in FIG. 1, the parasitic transistor 5 may be turned on. When the parasitic transistor 5 is turned on, a GIDL (Gate Induced Drain Current Leakage) may occur to the cell 6. The stored charge leaks. As a result, the retention time of the data stored in the cell 6 is reduced, which lowers the refresh characteristics.

따라서, 상술한 문제점을 해결하기 위한 본 발명의 목적은 워드라인의 폭을 이중으로 형성하여 랜딩 플러그 콘택의 면적을 크게 확보하여 셀에 저장되는 전하량의 손실을 줄이고, 기생 트랜지스터의 생성을 막아 데이터 보유 시간을 향상시키는데 있다.Accordingly, an object of the present invention for solving the above problems is to double the width of the word line to secure a large area of the landing plug contact to reduce the amount of charge stored in the cell, to prevent the generation of parasitic transistors to retain data To improve time.

위와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 워드라인 패터닝 방법은 트렌치 소자 분리 공정으로 반도체 기판을 활성영역과 비활성영역으로 구분하는 제 1 공정; 상기 비활성영역에 소자 분리형 산화막을 증착하여 소자 분리막을 형성하는 제 2공정; 상기 활성영역과 소자 분리막 상부에 게이트 산화막과 워드라인 형성물질을 순차적으로 증착하는 제 3공정; 및 상기 활성영역 상의 워드라인과 상기 소자 분리막 상의 워드라인이 서로 다른 폭을 갖도록 형성된 마스크를 이용하여 상기 산화막과 워드라인용 물질을 제거하여 워드라인을 형성하는 제 4공정을 포함한다.Word line patterning method of the semiconductor device of the present invention for achieving the above object comprises a first step of dividing the semiconductor substrate into an active region and an inactive region in the trench isolation process; Forming a device isolation layer by depositing a device isolation oxide film in the inactive region; A third process of sequentially depositing a gate oxide layer and a word line forming material on the active region and the device isolation layer; And a fourth process of forming a word line by removing the oxide layer and the word line material by using a mask formed such that the word line on the active region and the word line on the device isolation layer have different widths.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따라 형성된 워드라인의 모습을 보여주는 평면도이다.2 is a plan view showing a state of a word line formed according to the present invention.

도 2를 참조하면, 워드라인 WL1 ∼ WL4의 폭은 균일하게 형성되지 않는다. 즉, 도 1에 도시된 종래의 기술에 따른 워드라인 WL1 ∼ WL4은 활성영역(2)과 겹쳐져 기생 트랜지스터(3, 5)가 형성되지만, 본 발명에 따른 도 2의 워드라인 WL1 ∼ WL4은 활성영역의 중심부와 오버랩되는 부분의 폭은 크게 형성하고 오버랩되지 않는 부분의 폭은 작게 형성함으로써 기생 트랜지스터가 형성되지 않음과 동시에 랜딩 플러그 콘택(7)의 면적이 증가된다.Referring to FIG. 2, the widths of the word lines WL1 to WL4 are not formed uniformly. That is, the word lines WL1 to WL4 according to the related art shown in FIG. 1 overlap with the active region 2 to form parasitic transistors 3 and 5, but the word lines WL1 to WL4 of FIG. 2 according to the present invention are active. The width of the portion overlapping with the central portion of the region is made large, and the width of the portion not overlapping is made small so that the parasitic transistor is not formed and the area of the landing plug contact 7 is increased.

도 3a 내지 도 3c는 본 발명의 실시예에 따른 반도체 소자의 워드라인 패터닝 방법을 보여주는 도면이다.3A to 3C are diagrams illustrating a word line patterning method of a semiconductor device according to an exemplary embodiment of the present invention.

도 3a를 참조하면, 반도체 기판(11) 상부에 패드 질화막(12) 및 패드 산화막(13)을 순차적으로 증착한다.Referring to FIG. 3A, a pad nitride film 12 and a pad oxide film 13 are sequentially deposited on the semiconductor substrate 11.

도 3b를 참조하면, 소자분리용 마스크를 이용한 노광 및 현상 공정으로 패드 질화막(12) 및 패드 산화막(13)을 식각하여 활성영역(14)을 정의하는 소자 분리용 트렌치(15)를 형성한다.Referring to FIG. 3B, the pad nitride layer 12 and the pad oxide layer 13 are etched by an exposure and development process using a device isolation mask to form a device isolation trench 15 defining an active region 14.

다음에는, 전체 표면 상부에 소자 분리용 트렌치(15)를 매립하는 소자 분리용 산화막을 증착한 후, 기계적 화학적 연마(CMP)로 소자분리막을 절연시키고 평탄화하면서 패드 산화막(13)과 패드 질화막(12)을 제거하여 소자 분리막을 형성한다.Next, after depositing a device isolation oxide film filling the device isolation trench 15 over the entire surface, the pad oxide film 13 and the pad nitride film 12 are insulated and planarized by mechanical chemical polishing (CMP). ) Is removed to form an isolation layer.

도 3c를 참조하면, 평탄화된 반도체 기판(11) 상부에 산화막(미도시) 및 워드라인용 물질(미도시)을 차례로 증착한다.Referring to FIG. 3C, an oxide film (not shown) and a word line material (not shown) are sequentially deposited on the planarized semiconductor substrate 11.

다음에는, 워드라인(WL3)에서 활성영역(14) 상의 부분(19)과 워드라인(WL4)에서 소자 분리막(16) 상의 부분(20)이 서로 다른 폭을 갖도록 제작된 마스크를 이용하여 상기 산화막 및 워드라인용 물질을 식각하여 서로 다른 폭을 갖는 게이트 산화막 패턴(17) 및 워드라인(18)을 형성한다. 여기에서, 도 3c는 도 2의 X-X'에 대한 단면을 나타낸 것이다.Next, the oxide layer is formed by using a mask fabricated such that the portion 19 on the active region 14 in the word line WL3 and the portion 20 on the device isolation layer 16 in the word line WL4 have different widths. And etching the material for the word line to form the gate oxide pattern 17 and the word line 18 having different widths. 3C is a cross-sectional view taken along line X-X 'of FIG.

상술한 바와 같이, 본 발명의 워드라인 패터닝 방법은 워드라인이 이중 폭을 갖도록 형성하여 랜딩 플러그 콘택 면적을 늘리고 기생 트랜지스터의 생성을 막아, 셀에 저장되는 전하량의 손실을 줄이고 데이터 보유 시간을 향상시켜줌으로써 반도체 소자의 신뢰성을 향상시킬 수 있다.As described above, the word line patterning method of the present invention is formed so that the word line has a double width to increase the landing plug contact area and prevent the generation of parasitic transistors, reducing the amount of charge stored in the cell and improve the data retention time In this way, the reliability of the semiconductor device can be improved.

도 1은 종래 공정에 따라 반도체 기판에 워드라인이 형성된 모습을 보여주는 평면도.1 is a plan view showing a word line formed on a semiconductor substrate according to a conventional process.

도 2는 본 발명에 따라 형성된 워드라인의 모습을 보여주는 평면도.Figure 2 is a plan view showing the appearance of the word line formed in accordance with the present invention.

도 3a 내지 도 3c는 본 발명의 실시예에 따른 반도체 소자의 워드라인 패터닝 방법을 보여주는 도면.3A to 3C illustrate a word line patterning method of a semiconductor device in accordance with an embodiment of the present invention.

Claims (2)

트렌치 소자 분리 공정으로 반도체 기판을 활성영역과 비활성영역으로 구분하는 제 1 공정;A first step of dividing the semiconductor substrate into an active region and an inactive region in a trench isolation process; 상기 비활성영역에 소자 분리형 산화막을 증착하여 소자 분리막을 형성하는 제 2공정;Forming a device isolation layer by depositing a device isolation oxide film in the inactive region; 상기 활성영역과 소자 분리막 상부에 게이트 산화막과 워드라인 형성물질을 순차적으로 증착하는 제 3공정; 및A third process of sequentially depositing a gate oxide layer and a word line forming material on the active region and the device isolation layer; And 상기 활성영역 상의 워드라인과 상기 소자 분리막 상의 워드라인이 서로 다른 폭을 갖도록 형성된 마스크를 이용하여 상기 산화막과 워드라인용 물질을 제거하여 워드라인을 형성하는 제 4공정을 포함하는 반도체 소자의 워드라인 패터닝 방법.And a fourth process of forming a word line by removing the oxide layer and the word line material by using a mask formed such that the word line on the active region and the word line on the device isolation layer have different widths. Patterning method. 제 1항에 있어서, 상기 제 4공정은The method of claim 1, wherein the fourth step 상기 소자 분리막 상의 워드라인의 폭을 상기 활성영역 상의 워드라인의 폭보다 좁게 형성하는 것을 특징으로 하는 반도체 소자의 워드라인 패터닝 방법.And forming a width of the word line on the device isolation layer to be smaller than the width of the word line on the active region.
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