KR101726326B1 - Cross point memory device - Google Patents

Abstract

The cross-point memory device of the present invention comprises a plurality of first word lines arranged in parallel with each other, a plurality of second word lines arranged parallel to each other between the first word lines, a plurality of first word lines arranged in parallel A plurality of second bit lines arranged in parallel with each other between first bit lines and a plurality of first bit lines arranged in parallel with each other between a first word line and a first bit line, And a plurality of intersection memory cells (Cells) electrically connected to each other. At this time, the cross-sectional area of the cross-section perpendicular to the longitudinal direction of the first bit lines is formed to increase as the distance from the end of the first side of the first bit line increases, Is formed to increase as the distance from the end of the second side of the second bit line increases.

Description

[0001] CROSS-POINT MEMORY DEVICE [0002]

The present invention relates to an intersection memory device in which the cross-sectional area of a metal line is adjusted and memory cells are alternately arranged.

The intersection memory cells are located between two sets of conductors extending in orthogonal directions above and below the memory cell. At this time, the first set of conductors located under the memory cells may be referred to as bit lines, while the second set of conductors located over the memory cells may be referred to as word lines. That is, each memory cell in the cross point memory array is located at the intersection of one word line and one bit line. Selecting one memory cell in the array to read or write a memory cell may be accomplished by activating the word lines and bit lines associated with that memory cell. Reading of the selected memory cell may be accomplished by applying a voltage to the word line to measure the resulting current through the selected memory cell.

In particular, the memory technology that is the subject of the intersection memory structure is mainly for resistance control memories such as phase change memory (PCM) and memristor. Such memories can be used as a multi-level cell (MLC) with a continuous cell characteristic. However, since the memory needs a delicate reading / writing process, the voltage level and the signal width of the reading and writing process must be precisely adjusted do.

In this regard, Korean Patent Laid-Open Publication No. 10-2014-0126503 (entitled " Semiconductor Device ") discloses a semiconductor device comprising first conductive patterns each connected to a common source and select lines of a memory block formed on a substrate, And third conductive patterns for transferring block selection signals for connecting the local lines and the global lines of the memory block, wherein the first to third conductive patterns Discloses a technique of disposing them on different layers at the top of a memory block.

On the other hand, in the case of a general cross point memory device, a controller is disposed on one side of a word line and a bit line, respectively. In such a case, an extra area is generated due to its structural characteristics, and the extra area at this time is not utilized as a blanket.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the conventional art described above, and it is an object of the present invention to provide a cross point memory storage device in which a word line and a bit line are additionally arranged in a space between word lines and bit lines, The present invention provides a method for providing a plurality of data streams.

It is another object of the present invention to provide a method for minimizing a difference between a voltage drop and a delay time generated in a metal line by adjusting a cross-sectional area of a metal line in an intersection memory storage device.

It is to be understood, however, that the technical scope of the present invention is not limited to the above-described technical problems, and other technical problems may exist.

According to a first aspect of the present invention, there is provided an intersection memory device including a plurality of first word lines arranged in parallel with each other, a plurality of first word lines arranged in parallel with each other between first word lines, A plurality of first bit lines orthogonal to the first word line and arranged parallel to each other, a plurality of second bit lines arranged parallel to each other between the first bit lines, A plurality of intersection memory cells (Cells) electrically connected between a word line and a first bit line, and a second word line and a second bit line. At this time, the cross-sectional area of the cross-section perpendicular to the longitudinal direction of the first bit lines is formed to increase as the distance from the end of the first side of the first bit line increases, Is formed to increase as the distance from the end of the second side of the second bit line increases.

The intersection memory device according to the second aspect of the present invention also includes a plurality of first word lines arranged in parallel to each other, a plurality of second word lines arranged in parallel with each other between the first word lines, A plurality of second bit lines arranged parallel to each other between the first bit lines and a plurality of first bit lines arranged in parallel with each other and a first bit line and a second bit line, And a plurality of memory cells (Cells) electrically connected between the word line and the second bit line. At this time, the cross-sectional area of the cross section perpendicular to the longitudinal direction of the first word lines is formed to increase as the distance from the end of the first side of the first word line increases, and the cross- Is formed to increase as the distance from the end of the first side of the second word line increases.

According to a third aspect of the present invention, there is provided a method of manufacturing an intersection memory device, comprising: forming a plurality of first bit lines arranged in parallel to one another; forming a plurality of second bits Forming a plurality of intersection memory cells at predetermined points of the first bit line and the second bit lines, forming a plurality of intersection memory cells at the top of which the intersection memory cells are formed, Forming a plurality of first word lines and forming a plurality of second word lines orthogonal to the second bit lines and arranged in parallel to each other at an upper end where the intersection memory cells are formed. At this time, the cross-sectional area of the cross-section perpendicular to the longitudinal direction of the first bit lines is formed to increase as the distance from the end of the first side of the first bit line increases, Is formed to increase as the distance from the end of the second side of the second bit line increases.

According to a fourth aspect of the present invention, there is provided a method of manufacturing an intersection memory device, comprising: forming a plurality of first bit lines arranged in parallel with each other; forming a plurality of second bits Forming a plurality of intersection memory cells at predetermined points of the first bit line and the second bit lines, forming a plurality of intersection memory cells at the top of which the intersection memory cells are formed, Forming a plurality of first word lines and forming a plurality of second word lines orthogonal to the second bit lines and arranged in parallel to each other at an upper end where the intersection memory cells are formed. At this time, the cross-sectional area of the cross section perpendicular to the longitudinal direction of the first word lines is formed to increase as the distance from the end of the first side of the first word line increases, and the cross- Is formed to increase as the distance from the end of the second side of the second word line increases.

The cross point memory device according to an embodiment of the present invention has the effect of disposing word lines and bit lines separately in an extra space created by arranging word lines and bit lines and integrating them.

In addition, since the resistance of the metal wire is inversely proportional to the cross-sectional area and is proportional to the length, the cross-sectional area of the metal wire is adjusted to solve the problem that the bias voltage is low due to a high voltage drop. From this, it is possible to minimize the difference in delay time of the electric signal.

1 is a block diagram of a general cross point memory device.
FIG. 2 is an exemplary view illustrating the components of an intersection memory device according to an exemplary embodiment of the present invention. Referring to FIG.
3 is a perspective view of an intersection memory cell according to an embodiment of the present invention.
4 is an exemplary diagram illustrating an intersection memory device according to another embodiment of the present invention.
5 is an exemplary view illustrating an intersection memory device according to another embodiment of the present invention.
6 is a configuration diagram of an intersection memory device according to an embodiment of the present invention.
7 is a flowchart of a method of manufacturing an intersection memory device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when an element is referred to as "comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.

The following examples are intended to further illustrate the present invention and are not intended to limit the scope of the present invention. Accordingly, the same scope of the invention performing the same function as the present invention will also fall within the scope of the present invention.

Prior to the specific description, the intersection memory cells are often implemented in an array form, such as a transistor that prevents the leakage current through a memory cell that is not normally selected from affecting the read or write of the selected memory cell Device.

For example, a transistor may be placed between a word line and a bit line in series with a memory cell to provide isolation by switching off the unselected device through a control gate (used herein as a controller) .

1 is a block diagram of a general cross point memory device.

Referring to FIG. 1, a typical cross point memory device may include a word line, a bit line, a first controller, a second controller, and a memory cell. Generally, in the memory cell array, n word lines and m bit lines for selective data input / output intersect each other vertically.

That is, the memory operates in such a manner that a word line and a bit line intersect and form a lattice, and a memory cell at an intersection of a specific word line and a bit line is called. This combination, called a unit memory cell, is the basic bit of data storage. Thus, the n x m cell array has n x m memory bits, which in turn determine the integrated capacitance of the memory device.

The word line is used to read and write actual data and can be extended and arranged in a first direction and the bit line carries the charge into the memory device or reads the transferred charge, And can be arranged extending in two directions.

The first controller may be connected to the word lines and may be disposed at the end of the first side of the bit lines and the second controller may be connected to the bit lines and may be disposed at the end of the first side of the word lines. have. Such a controller is composed of circuits which are located at the edge of the memory cell array and supply voltage or current necessary for data input / output.

In addition, such a memory structure is generally available in both a form in which the word lines are located on the upper surface (FIG. 1A) or a form in which the bit lines are located on the upper surface (FIG. 1B).

On the other hand, metal wires used in semiconductors have inherent resistance. This resistance is inversely proportional to the cross-sectional area and is proportional to the length. These features can cause problems due to the resistivity of the metal wire in the semiconductor.

For example, a cell located far from the row decoder and write driver in a memory structure has a problem that the bias voltage is low due to a voltage drop due to a high resistance in a long extended metal line.

Also, in the case of a cell far from the controller, the reaction time may be delayed due to the delay time occurring in the metal wire.

The present invention is able to evenly distribute the resistance value on the array of cross-point memory cells using the property that the resistance value of the metal is proportional to the length and inversely proportional to the cross-sectional area. Further, the problem of delaying the reaction time due to the delay time can be solved.

Generally, a high voltage drop occurs in memory cells far from the controller. The cross-point memory storage device according to an embodiment of the present invention can broaden the cross-sectional area of the word lines and the bit lines connected to the memory cells far from the controller to evenly distribute the voltage drop values.

Hereinafter, an intersection memory device proposed in the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is an exemplary view illustrating the components of an intersection memory device according to an exemplary embodiment of the present invention. Referring to FIG. 2 (a) and 2 (b) are components of an intersection memory device. FIG. 2 (b) is a cross-sectional view of a cross- Fig.

Ultimately, the cross-point memory device according to one embodiment of the present invention is shown in FIG. 2 (a) and FIG. 2 (b) the word lines of FIG. 2B may be arranged, and the bit lines of FIG. 2B may be arranged between each bit line arranged in FIG. 2A.

Hereinafter, an intersection memory device according to an embodiment of the present invention will be described with reference to the drawings.

First, the components of the intersection memory device according to an embodiment of the present invention will be described with reference to FIG. 2A, for example.

An intersection memory device 10 according to an embodiment of the present invention includes a word line 100, a bit line 200, an intersection memory cell 300, a first controller 400, and a second controller 500 do.

The intersection memory cell 300 is located at the intersection of the word line 100 and the bit line 200 in the figure, and therefore can be more clearly understood with reference to FIG.

3 is a perspective view of an intersection memory cell according to an embodiment of the present invention.

As shown in FIG. 3, the intersection memory cell 300 is located between the word line 100 and the bit line 200 and is electrically connected.

Also, although not shown in the figure, each component of the cross point memory device 10 may be implemented on a substrate. The substrate may be any semiconductor substrate such as monocrystalline silicon, an IV-IV compound such as silicon-germanium or silicon-germanium-carbon, a III-V compound, an II-VI compound, an epitaxial layer, , A plastic, a metal or a ceramic substrate. The substrate may comprise an integrated circuit fabricated thereon, such as a driver circuit for a memory device.

Referring again to Figure 2 (a), a set of conductive electrodes, referred to herein as word lines 100, are in contact with and connected to the upper surface of the memory cell 300, respectively. Each word line 100 is in electrical contact with a particular row of memory cells 300.

In particular, the word line 100 may be connected to the first controller 400, which will be described later, and may be disposed in parallel with the second controller 500. At this time, it can be seen that the cross-sectional area of the word line 100 is formed to increase as the distance from the end of the first side of the word line 100 increases. Here, the first side is the left side with reference to the drawing.

The cross sectional area of the word line 100 is increased as the distance from the first controller 400 located at the end of the first side of the word line 100 increases so that the distance between the word line 100 and the first controller 400 The increased resistance value can be adjusted.

Similarly, the bit line 200 may be connected to the second controller 500, which will be described later, and may be disposed in parallel with the first controller 400. At this time, it can be seen that the cross-sectional area of the bit line 200 is formed to increase as the distance from the end of the first side of the bit line 200 increases. Here, the first aspect is the lower side with reference to the drawings.

The cross sectional area of the bit line 200 is increased as it goes away from the second controller 500 located on the first side of the bit line 200 so that the distance between the bit line 200 and the second controller 500 It is possible to control the increased resistance value.

 Such a change in cross-sectional area may include a change in width (Width, W) or a change in thickness (Thickness, T). That is, the width or thickness of the word lines 100 may increase as the distance from the end of the first side of the word line 100 increases and the width or thickness of the bit lines 200 may increase as the first And may increase as the distance from the side end is increased.

For reference, the cross-sectional area of the word line 100 herein refers to the cross-sectional area of the cross-section perpendicular to the longitudinal direction of the word lines 100. In addition, the cross-sectional area of the bit line 200 means the cross-sectional area of the cross-section perpendicular to the longitudinal direction of the bit lines 200. Referring to Figs. 3 (b) and 3 (c), the change in cross-sectional area may include a change in width W or a change in thickness T. [

The end of the first side of the word line 100 may refer to the end of the word line 100 which is the connection portion of the word line 100 and the first controller 400, One end of the side surface may refer to an end portion of the bit line 200, which is a connection portion between the bit line 200 and the second controller 500.

In addition, a set of conductive electrodes, referred to herein as bit lines 200, are in contact with and connected to the bottom surface of the memory cell 300, respectively. Each bit line 200 is in electrical contact with a memory cell 300 located at a predetermined point.

2 (a) and 2 (b) so that the word line 100 of FIG. 2 (b) is located between the word lines 100 of FIG. 2 (a) And the bit line 200 of FIG. 2 (b) is located between the bit lines 200 of FIG. 2 (a), the bit lines 200 corresponding to the word lines 100 Sectional area of each bit line 200 increases as it moves away from the first controller 400 located at the end of the first side of each word line 100 and the cross- Can be increased as it moves away from the second controller 500 located at the lateral end. A detailed explanation will be given with reference to FIG. 6 which will be described later by way of example.

The present invention is not limited to the simultaneous adjustment of the cross-sectional areas of the word line 100 and the bit line 200, and the resistance value can be adjusted by adjusting the cross-sectional areas of the word line 100 or the bit line 200 have. The cross point memory device 10 according to another embodiment of the present invention will be described with reference to the case where the word line 100 and the bit line 200 are adjusted through FIG. 4 and FIG. 5 described later.

Also, such a memory structure is possible in a form in which the word line 100 is generally located on the upper surface, or the bit line 200 is located on the upper surface, as shown in FIG.

The delay time occurring in the word line 100 and the bit line 200 due to the width of the cross-sectional area can be explained by the following equation.

[Mathematical Expression]

Cj and Rk denote the capacitance and resistance of each equally divided conductor when N is equally divided. That is, the gap between the delay times can be adjusted by reducing the resistance value of the conductor by increasing the cross-sectional area.

Memory cell 300, on the other hand, may include resistive memory elements such as memristors, phase change material resistors, conductive bridge resistors, transition metal oxide based resistors, and any implementation of resistive change memory.

Each memory cell 300 is located at the intersection of one word line 100 and one bit line 200 associated with memory cell 300. Each memory cell 300 may be selected for writing or reading by activating the particular word line 100 and bit line 200 associated with that memory cell 300. [

The crosspoint memory device 10 is also coupled to a memory cell 300 via a respective wordline 100 and coupled to a particular wordline 100 for reading or writing a particular memory cell 300 associated with the wordline 100. [ And a first controller 400 configured to activate the first controller 400. For example, the first controller 400 may include a row decoder, and a multiplexer, etc., to select a particular word line 100 in the word line 100.

The intersection memory device 10 also includes a second controller 500 connected to the memory cell 300 via a respective bit line 200. The second controller 500 may include a memory sense amplifier, a write driver, a demultiplexer, and an input / output pad.

The first controller 400 and the second controller 500 cooperate to access the respective memory cell 300 by activating the corresponding word line 100 and bit line 200 connected to the selected memory cell 300 . Other configurations known to those skilled in the art for accessing memory cell 300 in accordance with the teachings of the present invention may also be used.

During a write operation, the first controller 400 writes information to a selected memory cell 300 by applying a voltage to a particular word line 100 corresponding to the selected memory cell 300. [ The second controller 500 activates the selected memory cell 300 by connecting the memory cell 300 to the ground. Thereafter, a current flows through the selected memory cell 300, affecting the characteristics of the memory cell 300 and actually storing a logic 1 or logic 0 in the memory cell 300. For example, if the memory element contained in the memory cell 300 is a memistor, the current flowing through the memristor changes the resistance of the memristor. This change in resistance can be detected during a subsequent read operation.

During a read operation, the first controller 400 activates the selected memory cell 300 by applying a specified voltage to the corresponding word line 100 and the second controller 500 activates the selected memory cell 300 The bit line 200 is connected. The resulting current detected by the second controller 500 indicates the state of the memory cell 200, e.g., whether the memory cell 300 corresponds to logic one or logic zero.

On the other hand, an active region may be disposed under the bit line 200.

Also, such a memory structure is generally available in a form in which a word line is located on the upper surface, or a bit line is located on the upper surface, as shown in Fig.

4 is an exemplary diagram illustrating an intersection memory device according to another embodiment of the present invention.

The cross point memory device 10 according to another embodiment of the present invention includes a plurality of first word lines 100 'arranged in parallel to each other, a plurality of parallel arranged first word lines 100' Two word lines 100 '', a plurality of first bit lines 200 'orthogonal to the first word lines 100' and arranged parallel to each other, and a plurality of first bit lines 200 ' A plurality of second bit lines 200 '' arranged in parallel, a first word line 100 'and a first bit line 200', a second word line 100 '' and a second bit line 200 ' Point memory cells electrically connected between the first and second memory cells 200 " and 200 ".

At this time, it can be seen that the cross-sectional area of the word lines 100 'and 100' 'is adjusted while the cross-sectional area of the bit lines 200' and 200 '' of FIG. 4 is constant. That is, the sectional area of the cross section perpendicular to the longitudinal direction of the first word lines 100 'is formed to increase as the distance from the end of the first side of the first word line 100' increases, and the cross- Sectional area of the cross section perpendicular to the longitudinal direction of the second word line 100 '' is increased from the end of the second side of the second word line 100 ''.

For reference, the first side indicated in the specification refers to the left side with reference to the drawing. Further, the second side means the right side with reference to the drawing.

Generally, the resistance of the first word line 100 'increases as it moves away from the first controller 400' located at the end of the first side of the first word line 100 ', so that the resistance of the first word line 100' And the first controller 400 ', the resistance value of the corresponding point can be adjusted by adjusting the size of the cross-sectional area of the first word line 100'.

Further, the resistance of the second word line 100 " is increased as it is away from the third controller 400 " located at the end of the second side of the second word line 100 " The size of the cross-sectional area of the second word line 100 '' may be adjusted to adjust the resistance of the corresponding point. have. Here, the function of the third controller 400 '' is the same as that of the first controller 400 ', but is referred to as the third controller 400' 'for convenience.

On the other hand, such a change in cross-sectional area may include a change in width or a change in thickness. That is, the width W or the thickness T of the first word line 100 'may increase as the distance from the end of the first side increases, and the width or thickness of the second word line 100' The distance from the two side ends can be increased.

For reference, the cross-sectional area referred to herein means a cross-sectional area of a cross section perpendicular to the longitudinal direction of the first and second word lines 100 'and 100' '. Referring to FIG. 3 (b), the change in cross-sectional area may include a change in width W or a change in thickness T. FIG.

Also, the ends of the first and second sides of the first and second word lines 100 'and 100 " are connected to the first and second word lines 100' and 100 " May refer to the end portions of the first and second word lines 100 'and 100 " as connection portions of the first and second word lines 400' and 400 ".

That is, the width or thickness of the first word line 100 'increases as the distance from the first controller 400' increases and the width or thickness of the second word line 100 '' increases as the third controller 400 ''. As shown in FIG.

Also, such a memory structure is possible in a form in which the word line 100 is generally located on the upper surface, or the bit line 200 is located on the upper surface, as shown in FIG.

In some cases, the position of each controller may be changed from the first side to the other side. It is not limited to the directions shown in the drawings unless the connection relationship between the word line 100 and the bit line 200 is changed.

5 is an exemplary diagram illustrating an intersection memory device 10 in accordance with another embodiment of the present invention.

The cross point memory device 10 according to another embodiment of the present invention includes a plurality of first word lines 100 'arranged in parallel to each other, a plurality of parallel arranged first word lines 100' Two word lines 100 '', a plurality of first bit lines 200 'orthogonal to the first word lines 100' and arranged parallel to each other, and a plurality of first bit lines 200 ' A plurality of second bit lines 200 '' arranged in parallel, a first word line 100 'and a first bit line 200', a second word line 100 '' and a second bit line 200 ' Point memory cells electrically connected between the first and second memory cells 200 " and 200 ".

At this time, FIG. 5 shows that the cross-sectional area of the bit lines 200 'and 200' 'is adjusted while the cross-sectional area of the word lines 100' and 100 '' is constant. That is, the sectional area of the cross section perpendicular to the longitudinal direction of the first bit lines 200 'is formed to increase as the distance from the end of the first side of the first bit line 200' increases, '' Are formed such that the cross-sectional area of the cross-section perpendicular to the longitudinal direction of the second bit line 200 '' increases from the end of the second side of the second bit line 200 ''.

For reference, the first aspect shown in the specification refers to the lower side with reference to the drawings. In addition, the second aspect refers to the upper side with reference to the drawings.

In general, the resistance of the first bit line 200 'increases as it moves away from the second controller 500' located at the end of the first side of the first bit line 200 ' And the second controller 500 ', the resistance value of the corresponding point can be adjusted by adjusting the size of the cross-sectional area of the first bit line 200'.

Also, the resistance of the second bit line 200 " is increased as it is away from the fourth controller 500 " located at the end of the second side of the second bit line 200 " The size of the cross-sectional area of the second bit line 200 '' may be adjusted to adjust the resistance value of the corresponding bit line 200 '' and the fourth controller 500 ''. have.

Such a change in cross-sectional area may include a change in width or a change in thickness. That is, the width W or the thickness T of the first bit line 200 'may increase as the distance from the end of the first side increases, and the width or thickness of the second bit line 200' The distance from the two side ends can be increased.

For reference, the cross-sectional area referred to herein means a cross-sectional area of a cross section perpendicular to the longitudinal direction of the first and second bit lines 200 'and 200' '. Referring to FIG. 3 (c), the change in the cross-sectional area may include a change in width W or a change in thickness T. FIG.

Also, the ends of the first and second sides of the first and second bit lines 200 ', 200 " are connected to the first and second bit lines 200' and 200 " May refer to the end portions of the first and second bit lines 200 'and 200 " that are connection portions of the first and second bit lines 500' and 500 ".

That is, the width or thickness of the first bit line 200 'increases as the distance from the second controller 500' increases and the width or thickness of the second bit line 200 '' increases as the distance from the fourth controller 500 '' increases. As shown in FIG.

Also, such a memory structure is possible in a form in which the word line 100 is generally located on the upper surface, or the bit line 200 is located on the upper surface, as shown in FIG.

In some cases, the position of each controller may be changed from the first side to the other side. It is not limited to the directions shown in the drawings unless the connection relationship between the word line 100 and the bit line 200 is changed.

6 is a configuration diagram of an intersection memory device according to an embodiment of the present invention.

In the case of FIG. 6 (a), FIG. 2 (a) and FIG. 2 (b) are superposed and FIG. 6 (b) is a perspective view of FIG. 6 (a).

The cross point memory device 10 according to one embodiment of the present invention includes a plurality of first word lines 100 'arranged in parallel to one another, a plurality of first word lines 100' arranged in parallel with each other between first word lines 100 ' A plurality of first bit lines 200 'orthogonal to the first word lines 100' and arranged parallel to each other, and a plurality of first bit lines 200 ' A plurality of second bit lines 200 '' arranged in parallel and a first bit line 200 'and a first bit line 200', a second word line 100 ' And a plurality of intersection memory cells 300 electrically connected between the memory cells 200 ".

At this time, the cross-sectional area of the cross section perpendicular to the longitudinal direction of the first bit lines 200 'is formed to increase as the distance from the end of the first side of the first bit line 200' '' Are formed to increase as the distance from the end of the second side of the second bit line 200 '' increases.

Here, an increase in cross-sectional area can be caused by a change in width or thickness. That is, the width of the first bit lines 200 'may increase as they are away from the ends of the first sides of the first bit lines 200'. Likewise, the thickness of the first bit line 200 'may increase as it is away from the end of the first side of the first bit line 200'.

As such, the width of the second bit line 200 " may increase as it is away from the end of the second side of the second bit line 200 ". Likewise, the thickness of the second bit line 200 " may increase as it is away from the end of the second side of the second bit line 200 ".

In addition, the cross-sectional area of the cross section perpendicular to the longitudinal direction of the first word lines 100 'may be formed to increase as the distance from the end of the first side of the first word line 100' increases.

The increase in cross-sectional area of the first word line 100 'may be due to a change in width or thickness, as described above. That is, the width of the first word lines 100 'may increase as they are away from the end of the first side of the first word line 100'. Also, the thickness of the first word lines 100 'may increase as they are away from the end of the first side of the first word line 100'.

Also, the cross-sectional area of the cross section perpendicular to the longitudinal direction of the second word lines 100 " may be formed to increase as the distance from the end of the second side of the second word line 100 " That is, the width of the second word lines 100 " may increase as they are away from the end of the second side of the first word line 100 ". Likewise, the thickness of the second word line 100 " may increase as it is away from the end of the second side of the second word line 100 ".

7 is a flowchart illustrating a method of manufacturing an intersection memory device according to an embodiment of the present invention.

A method of fabricating an intersection memory device 10 according to an embodiment of the present invention includes forming a plurality of first bit lines 200 '' parallel to each other (S710), forming a first bit line 200 ' (S720) forming a plurality of second bit lines 200 '' so as to be parallel to each other between a first bit line 200 'and a second bit line 200' Forming a plurality of intersection memory cells 300 at the top of the intersection memory cell 300 at the top of which the intersection memory cells 300 are formed and forming a plurality of first word lines And forming a plurality of second word lines 100 '' that are orthogonal to the second bit line 200 '' at the top of which the intersection memory cell 300 is formed and are disposed parallel to each other. (S750).

When the cross point memory device 10 according to an embodiment of the present invention is implemented in the same manner as in FIG. 6, it is determined whether or not the first (1, 2, 3, 4, 5, 6, 7, 8, Sectional area perpendicular to the longitudinal direction of each of the first and second bit lines 200 'and 200' 'and the first and second word lines 100' and 100 ' As shown in Fig.

4, the cross-sectional area of the cross section perpendicular to the longitudinal direction of the first and second word lines 100 'and 100' 'in the step S740 and the step S750 corresponds to the first and second Are formed to increase as they are away from the ends of the first and second sides of the word lines 100 ', 100 ". At this time, the bit lines 200 are formed so as to be parallel to each other with a predetermined thickness (S710, S720).

5, the cross-sectional area of the cross section perpendicular to the longitudinal direction of the first and second bit lines 200 'and 200' 'in the steps S710 and S720 is larger than the cross-sectional area of the first and second bit lines 200' 200 ', 200' ') of the first and second side surfaces. At this time, the word lines 100 are formed so as to be parallel to each other with a predetermined thickness (S740, S750).

Each component can be fabricated three-dimensionally on a single crystal silicon substrate through a semiconductor manufacturing process such as a known thin film deposition, lithography, etching, and packaging.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10: Intersection memory device
100: Word line
100 ': first word line
100 ": second word line
200: bit line
200 ': first bit line
200 ": second bit line
300: memory cell
400: first controller
500: Second controller

Claims (9)

In an intersection memory device,
A plurality of first word lines arranged parallel to each other;
A plurality of second word lines disposed between the first word lines in parallel with each other;
A plurality of first bit lines orthogonal to the first word lines and arranged parallel to each other;
A plurality of second bit lines disposed between the first bit lines in parallel with each other; And
A plurality of intersection memory cells (Cells) electrically connected between the first word line and the first bit line, the second word line and the second bit line,
Sectional area of a cross section perpendicular to the longitudinal direction of the first bit lines is formed to increase as the distance from the end of the first side of the first bit line increases,
Sectional area of a cross section perpendicular to the longitudinal direction of the second bit lines is formed to increase as the distance from the end of the second side of the second bit line increases,
Wherein the end of the first side face and the end of the second side face are spaced apart from each other by a predetermined distance. The method according to claim 1,
The width or thickness of the first bit lines increases as the distance from the end of the first side of the first bit line increases,
And wherein the width or thickness of the second bit lines increases as the distance from the end of the second side of the second bit line increases. The method according to claim 1,
Sectional area of the cross section perpendicular to the longitudinal direction of the first word lines increases as the distance from the end of the first side of the first word line increases,
Sectional area of the cross section perpendicular to the longitudinal direction of the second word lines increases as the distance from the end of the second side of the second word line increases. The method of claim 3,
The width or thickness of the first word lines increases as the distance from the end of the first side of the first word line increases,
And wherein the width or thickness of the second word lines increases as the distance from the end of the second side of the second word line increases. In an intersection memory device,
A plurality of first word lines arranged parallel to each other;
A plurality of second word lines disposed between the first word lines in parallel with each other;
A plurality of first bit lines orthogonal to the first word lines and arranged parallel to each other;
A plurality of second bit lines disposed between the first bit lines in parallel with each other; And
And a plurality of memory cells (Cells) electrically connected between the first word line and the first bit line, between the second word line and the second bit line,
Sectional area of the cross section perpendicular to the longitudinal direction of the first word lines is formed to increase as the distance from the end of the first side of the first word line increases,
Sectional area of a cross section perpendicular to the longitudinal direction of the second word lines is formed to increase as the distance from the end of the first side of the second word line increases,
Wherein the end of the first side face and the end of the second side face are spaced apart from each other by a predetermined distance. 6. The method of claim 5,
The width or thickness of the first word lines increases as the distance from the end of the first side of the first word line increases,
And wherein the width or thickness of the second word lines increases as the distance from the end of the second side of the second word line increases. A method of manufacturing an intersection memory device,
Forming a plurality of first bit lines arranged parallel to each other;
Forming a plurality of second bit lines disposed between the first bit lines in parallel with each other;
Forming a plurality of intersection memory cells at predetermined points of the first bit line and the second bit lines;
Forming a plurality of first word lines orthogonal to the first bit lines and disposed in parallel to each other at an upper end of the memory cell array; And
And forming a plurality of second word lines orthogonal to the second bit lines and arranged in parallel to each other at an upper end of the memory cell where the intersection memory cells are formed,
Sectional area of a cross section perpendicular to the longitudinal direction of the first bit lines is formed to increase as the distance from the end of the first side of the first bit line increases,
Sectional area of a cross section perpendicular to the longitudinal direction of the second bit lines is formed to increase as the distance from the end of the second side of the second bit line increases,
Wherein the end of the first side face and the end of the second side face are spaced apart from each other by a predetermined distance. 8. The method of claim 7,
The step of forming the first word lines to be arranged
Sectional area of a cross section perpendicular to the longitudinal direction of the first word lines increases as the distance from the end of the first side of the first word line increases,
The step of forming the second word lines to be arranged
Sectional area of the cross section perpendicular to the longitudinal direction of the second word lines increases as the distance from the end of the second side of the second word line increases. A method of manufacturing an intersection memory device,
Forming a plurality of first bit lines arranged parallel to each other;
Forming a plurality of second bit lines disposed between the first bit lines in parallel with each other;
Forming a plurality of intersection memory cells at predetermined points of the first bit line and the second bit lines;
Forming a plurality of first word lines orthogonal to the first bit lines and disposed in parallel to each other at an upper end of the memory cell array; And
And forming a plurality of second word lines so as to be orthogonal to the second bit line and parallel to each other at an upper end where the intersection memory cell is formed,
Sectional area of the cross section perpendicular to the longitudinal direction of the first word lines is formed to increase as the distance from the end of the first side of the first word line increases,
Sectional area of the cross section perpendicular to the longitudinal direction of the second word lines is formed to increase as the distance from the end of the second side of the second word line increases,
Wherein the end of the first side face and the end of the second side face are spaced apart from each other by a predetermined distance.

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