KR101669013B1 - Cross point memory device - Google Patents

Cross point memory device Download PDF

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Publication number
KR101669013B1
KR101669013B1 KR1020150090379A KR20150090379A KR101669013B1 KR 101669013 B1 KR101669013 B1 KR 101669013B1 KR 1020150090379 A KR1020150090379 A KR 1020150090379A KR 20150090379 A KR20150090379 A KR 20150090379A KR 101669013 B1 KR101669013 B1 KR 101669013B1
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cross
lines
bit
word
increases
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KR1020150090379A
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Korean (ko)
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양준성
한현승
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성균관대학교산학협력단
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Priority to US15/191,983 priority patent/US20160379707A1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/12—Apparatus or processes for interconnecting storage elements, e.g. for threading magnetic cores

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Abstract

The cross-point memory device of the present invention includes a plurality of word lines arranged in parallel to each other, a plurality of bit lines orthogonal to the word lines and arranged parallel to each other, and a plurality of bit lines electrically connected between the respective word lines and the bit lines Intersection memory cells (Cells). At this time, the cross-sectional area of the cross section perpendicular to the longitudinal direction of the bit lines is formed to increase as the distance from the first end of the word line increases.

Description

[0001] CROSS-POINT MEMORY DEVICE [0002]

The present invention relates to an intersection memory device in which the cross-sectional area of a metal line is adjusted.

The intersection memory cells are located between two sets of conductors extending in orthogonal directions above and below the memory cell. At this time, the first set of conductors located under the memory cells may be referred to as bit lines, while the second set of conductors located over the memory cells may be referred to as word lines. That is, each memory cell in the cross point memory array is located at the intersection of one word line and one bit line. Selecting one memory cell in the array to read or write a memory cell may be accomplished by activating the word lines and bit lines associated with that memory cell. Reading of the selected memory cell may be accomplished by applying a voltage to the word line to measure the resulting current through the selected memory cell.

In particular, the memory technology that is the subject of the intersection memory structure is mainly for resistance control memories such as phase change memory (PCM) and memristor. Such memories can be used as a multi-level cell (MLC) with a continuous cell characteristic. However, since the memory needs a delicate reading / writing process, the voltage level and the signal width of the reading and writing process must be precisely adjusted do.

In this regard, Korean Patent Laid-Open Publication No. 10-2014-0126503 (entitled " Semiconductor Device ") discloses a semiconductor device comprising first conductive patterns each connected to a common source and select lines of a memory block formed on a substrate, And third conductive patterns for transferring block selection signals for connecting the local lines and the global lines of the memory block, wherein the first to third conductive patterns Discloses a technique of disposing them on different layers at the top of a memory block.

On the other hand, metal wires used in semiconductors have inherent resistance. This resistance is inversely proportional to the cross-sectional area and is proportional to the length. These features can cause problems due to the resistivity of the metal wire in the semiconductor. For example, a cell located far from the row decoder and write driver in a memory structure has a problem that the bias voltage is low due to a voltage drop due to a high resistance in a long extended metal line.

Also, in the case of a cell far from the controller, the reaction time may be delayed due to the delay time occurring in the metal wire.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for minimizing a difference between a voltage drop and a delay time generated in a metal line by adjusting a cross-sectional area of a metal line in an intersection memory storage device .

It is to be understood, however, that the technical scope of the present invention is not limited to the above-described technical problems, and other technical problems may exist.

According to a first aspect of the present invention, there is provided an intersection memory device including a plurality of word lines arranged in parallel with each other, a plurality of bit lines arranged orthogonal to a word line and arranged parallel to each other, And a plurality of intersection memory cells (Cells) electrically connected between each word line and the bit line. At this time, the cross-sectional area of the cross section perpendicular to the longitudinal direction of the bit lines is formed to increase as the distance from the first end of the word line increases.

The cross point memory device according to the second aspect of the present invention also includes a plurality of word lines arranged in parallel with each other, a plurality of bit lines orthogonal to the word lines and arranged parallel to each other, And a plurality of intersection memory cells (Cells) electrically connected to each other. At this time, the cross-sectional area of the cross section perpendicular to the longitudinal direction of the word lines is formed so as to increase as the distance from the first end of the bit line increases.

A method of manufacturing an intersection memory device according to a third aspect of the present invention includes the steps of forming a plurality of bit lines to be arranged parallel to each other, forming a plurality of intersection memory cells at a predetermined point of bit lines, And forming a plurality of word lines arranged at right angles and parallel to the bit lines at the upper end where the memory cells are formed. At this time, the cross-sectional area of the cross section perpendicular to the longitudinal direction of the bit lines is formed to increase as the distance from the first end of the word line increases.

According to a fourth aspect of the present invention, a method of manufacturing an intersection memory device includes forming a plurality of bit lines to be arranged parallel to each other, forming a plurality of intersection memory cells at a predetermined point of bit lines, And forming a plurality of word lines arranged at right angles and parallel to the bit lines at the upper end where the memory cells are formed. At this time, the cross-sectional area of the cross section perpendicular to the longitudinal direction of the word lines is formed so as to increase as the distance from the first end of the bit line increases.

The cross point memory device according to an embodiment of the present invention has an effect of solving the problem that the bias voltage is low due to a high voltage drop by controlling the cross-sectional area of the metal line by using the characteristic that the resistance of the metal line is inversely proportional to the cross- have. From this, it is possible to minimize the difference in delay time of the electric signal.

1 is a block diagram of a general cross point memory device.
2 is an exemplary diagram of an intersection memory device according to an embodiment of the present invention.
3 is a perspective view of an intersection memory cell according to an embodiment of the present invention.
4 is an exemplary diagram of an intersection memory device according to another embodiment of the present invention.
5 is an illustration of an intersection memory device according to another embodiment of the present invention.
6 is a flowchart of a method of manufacturing an intersection memory device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when an element is referred to as "comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.

The following examples are intended to further illustrate the present invention and are not intended to limit the scope of the present invention. Accordingly, the same scope of the invention performing the same function as the present invention will also fall within the scope of the present invention.

Prior to the specific description, the intersection memory cells are often implemented in an array form, such as a transistor that prevents the leakage current through a memory cell that is not normally selected from affecting the read or write of the selected memory cell Device. For example, a transistor may be placed between a word line and a bit line in series with a memory cell to provide isolation by switching off the unselected device through a control gate (used herein as a controller) .

1 is a block diagram of a general cross point memory device.

Referring to FIG. 1, a typical cross point memory device may include a word line, a bit line, a first controller, a second controller, and a memory cell. Generally, in the memory cell array, n word lines and m bit lines for selective data input / output intersect each other vertically. That is, the memory operates in such a manner that a word line and a bit line intersect and form a lattice, and a memory cell at an intersection of a specific word line and a bit line is called. This combination, called a unit memory cell, is the basic bit of data storage. Thus, the n x m cell array has n x m memory bits, which in turn determine the integrated capacitance of the memory device.

The word line is used to read and write actual data and can be extended and arranged in a first direction and the bit line carries the charge into the memory device or reads the transferred charge, And can be arranged extending in two directions.

Also, the first controller may be connected to the word lines, the first controller may be disposed at the first end of the bit lines, the second controller may be connected to the bit lines, and the first controller may be disposed at the first end of the word lines. Such a controller is composed of circuits which are located at the edge of the memory cell array and supply voltage or current necessary for data input / output.

In addition, such a memory structure is generally available in both a form in which the word lines are located on the upper surface (FIG. 1A) or a form in which the bit lines are located on the upper surface (FIG. 1B).

On the other hand, metal wires used in semiconductors have inherent resistance. This resistance is inversely proportional to the cross-sectional area and is proportional to the length. These features can cause problems due to the resistivity of the metal wire in the semiconductor. For example, a cell located far from the row decoder and write driver in a memory structure has a problem that the bias voltage is low due to a voltage drop due to a high resistance in a long extended metal line.

Also, in the case of a cell far from the controller, the reaction time may be delayed due to the delay time occurring in the metal wire.

The present invention is able to evenly distribute the resistance value on the array of cross-point memory cells using the property that the resistance value of the metal is proportional to the length and inversely proportional to the cross-sectional area. Further, the problem of delaying the reaction time due to the delay time can be solved. Generally, a high voltage drop occurs in memory cells far from the controller. The cross-point memory storage device according to an embodiment of the present invention can broaden the cross-sectional area of the word lines and the bit lines connected to the memory cells far from the controller to evenly distribute the voltage drop values.

Hereinafter, an intersection memory device proposed in the present invention will be described in detail with reference to the accompanying drawings.

2 is a configuration diagram of an intersection memory device according to an embodiment of the present invention.

An intersection memory device 10 according to an embodiment of the present invention includes a word line 100, a bit line 200, an intersection memory cell 300, a first controller 400, and a second controller 500 do.

The intersection memory cell 300 is located at the intersection of the word line 100 and the bit line 200 in the figure, and therefore can be more clearly understood with reference to FIG.

3 is a perspective view of an intersection memory cell according to an embodiment of the present invention.

As shown in FIG. 3, the intersection memory cell 300 is located between the word line 100 and the bit line 200 and is electrically connected.

Also, although not shown in the figure, each component of the cross point memory device 10 may be implemented on a substrate. The substrate may be any semiconductor substrate such as monocrystalline silicon, an IV-IV compound such as silicon-germanium or silicon-germanium-carbon, a III-V compound, an II-VI compound, an epitaxial layer, , A plastic, a metal or a ceramic substrate. The substrate may comprise an integrated circuit fabricated thereon, such as a driver circuit for a memory device.

Referring again to FIG. 2, a set of conductive electrodes, referred to herein as word lines 100, extend over one side of memory cell 300. Each word line 100 is in electrical contact with a particular row of memory cells 300.

In particular, the word line 100 may be connected to the first controller 400, which will be described later, and may be disposed in parallel with the second controller 500. At this time, it can be seen that the cross-sectional area of the word line 100 is increased as the distance from the first end of the bit line 200 increases. Here, the cross-sectional area of the word line 100 increases as it moves away from the second controller 500 located at the first end of the bit line 200, and increases as the spacing between the word line 100 and the controller increases The resistance value can be adjusted. Such a change in cross-sectional area may include a change in width (Width, W) or a change in thickness (Thickness, T). More specifically, the width or thickness of the word lines 100 may increase as the distance from the first end of the bit line 200 increases.

For reference, the cross-sectional area referred to here means the cross-sectional area of the cross section perpendicular to the longitudinal direction of the word lines. Referring to FIG. 3 (b), the change in cross-sectional area may include a change in width W or a change in thickness T. FIG.

The first end of the bit line 200 may refer to the end of the bit line 200, which is the connection portion of the bit line 200 and the second controller 500.

On the other hand, a set of conductive electrodes, referred to herein as a bit line 200, extends over the other side of the memory cell 300. Each bit line 200 is in electrical contact with a particular row of memory cells 300.

In particular, the bit line 200 may be connected to a second controller 500, which will be described later, and may be disposed in parallel with the first controller 400. In the case of FIG. 2, the resistance value generated in the word line 100 is adjusted by adjusting only the cross-sectional area of the word line 100, but the embodiment of the present invention is not limited thereto and the cross- It is also possible to adjust the resistance value by adjusting. A detailed description will be given with reference to FIG. 4 and FIG. 5 which will be described later by way of example.

The delay time occurring in the word line 100 and the bit line 200 due to the width of the cross-sectional area can be explained by the following equation.

[Mathematical Expression]

Figure 112015061615841-pat00001

Cj and Rk denote the capacitance and resistance of each equally divided conductor when N is equally divided. Here, the gap of the delay time can be adjusted by increasing the cross-sectional area and reducing the resistance value of the conductor.

Memory cell 300, on the other hand, may include resistive memory elements such as memristors, phase change material resistors, conductive bridge resistors, transition metal oxide based resistors, and any implementation of resistive change memory.

Each memory cell 300 is located at the intersection of one word line 100 and one bit line 200 associated with memory cell 300. Each memory cell 300 may be selected for writing or reading by activating the particular word line 100 and bit line 200 associated with that memory cell 300. [

The crosspoint memory device 10 is also coupled to a memory cell 300 via a respective wordline 100 and coupled to a particular wordline 100 for reading or writing a particular memory cell 300 associated with the wordline 100. [ And a first controller 400 configured to activate the first controller 400. For example, the first controller 400 may include a row decoder, and a multiplexer, etc., to select a particular word line 100 in the word line 100.

The intersection memory device 10 also includes a second controller 500 connected to the memory cell 300 via a respective bit line 200. The second controller 500 may include a memory sense amplifier, a write driver, a demultiplexer, and an input / output pad.

The first controller 400 and the second controller 500 cooperate to access the respective memory cell 300 by activating the corresponding word line 100 and bit line 200 connected to the selected memory cell 300 . Other configurations known to those skilled in the art for accessing memory cell 300 in accordance with the teachings of the present invention may also be used.

During a write operation, the first controller 400 writes information to a selected memory cell 300 by applying a voltage to a particular word line 100 corresponding to the selected memory cell 300. [ The second controller 500 activates the selected memory cell 300 by connecting the memory cell 300 to the ground. Thereafter, a current flows through the selected memory cell 300, affecting the characteristics of the memory cell 300 and actually storing a logic 1 or logic 0 in the memory cell 300. For example, if the memory element contained in the memory cell 300 is a memistor, the current flowing through the memristor changes the resistance of the memristor. This change in resistance can be detected during a subsequent read operation.

During a read operation, the first controller 400 activates the selected memory cell 300 by applying a specified voltage to the corresponding word line 100 and the second controller 500 activates the selected memory cell 300 The bit line 200 is connected. The resulting current detected by the second controller 500 indicates the state of the memory cell 200, e.g., whether the memory cell 300 corresponds to logic one or logic zero.

On the other hand, an active region may be disposed under the bit line 200.

Also, such a memory structure is generally available in a form in which a word line is located on the upper surface, or a bit line is located on the upper surface, as shown in Fig.

4 is an exemplary diagram of an intersection memory device according to another embodiment of the present invention.

An intersection memory device 10 according to another embodiment of the present invention includes a plurality of word lines 100 arranged in parallel with each other, a plurality of bit lines 200 orthogonal to the word line 100 and arranged parallel to each other . Although not shown in the figure, a plurality of intersection memory cells (Cells) electrically connected between each word line 100 and the bit line 200 are connected to the word lines 100, A first controller 400 disposed on the first side of the bit lines 200 and a second controller 500 coupled to the bit lines 200 and disposed on a first side of the bit lines 200.

4, the cross-sectional area of the word lines 100 is constant, but the cross-sectional area of the bit lines 200 is increased as the distance from the first end of the word line 100 increases. Here, the cross-sectional area of the bit line 200 is increased as it moves away from the first controller 400 located at the first end of the word line 100, and increases as the distance between the bit line 200 and the controller increases The resistance value can be adjusted. Such a change in cross-sectional area may include a change in width or a change in thickness. More specifically, the width W or thickness T of the bit lines 200 may increase as the distance from the first end of the word line 100 increases.

For reference, the cross-sectional area referred to herein refers to the cross-sectional area of the cross-section perpendicular to the longitudinal direction of the bit lines 200. Referring to FIG. 3 (c), the change in the cross-sectional area may include a change in width W or a change in thickness T. FIG.

The first end of the word line 100 may refer to the end of the word line 100, which is a connection portion between the word line 100 and the first controller 400.

That is, the width of the bit lines 200 increases as the distance from the first controller 400 increases, and the thickness of the bit lines 200 increases as the distance from the first controller 400 increases.

Also, such a memory structure is generally available in a form in which a word line is located on the upper surface, or a bit line is located on the upper surface, as shown in Fig.

5 is an illustration of an intersection memory device according to another embodiment of the present invention.

An intersection memory device 10 according to another embodiment of the present invention includes a plurality of word lines 100 arranged in parallel with each other, a plurality of bit lines 200 orthogonal to the word line 100 and arranged parallel to each other . Although not shown in the figure, a plurality of intersection memory cells (Cells) electrically connected between each word line 100 and the bit line 200 are connected to the word lines 100, A first controller 400 disposed on the first side of the bit lines 200 and a second controller 500 coupled to the bit lines 200 and disposed on a first side of the bit lines 200.

In some cases, the position of each controller may be changed from the first side to the other side. It is not limited to the directions shown in the drawings unless the connection relationship between the word line 100 and the bit line 200 is changed.

5 shows a case where the cross-sectional area of the word lines 100 and the cross-sectional area of the bit lines 200 are both changed. That is, as described above, it can be seen that the cross-sectional area of the bit line 200 is formed to increase as the distance from the first end of the word line 100 increases. Similarly, it can be seen that the cross-sectional area of the word line 100 is formed to increase as it goes away from the first end of the bit line 200. The cross-sectional area of each word line 100 and the bit line 200 increases as the degree of spacing from the reference controller increases, thereby adjusting the resistance value. Such a change in cross-sectional area may include a change in width or a change in thickness.

Also, such a memory structure is generally available in a form in which a word line is located on the upper surface, or a bit line is located on the upper surface, as shown in Fig.

6 is a flowchart illustrating a method of manufacturing an intersection memory device according to an embodiment of the present invention.

A method of fabricating an intersection memory device according to an embodiment of the present invention includes forming (S610) a plurality of bit lines (200) to be arranged parallel to each other, forming a plurality of intersection memory A step S620 of forming a cell 300 and a step S630 of forming a plurality of word lines 100 arranged in parallel and perpendicular to the bit line 200 at an upper end where the intersection memory cell 300 is formed, .

At this time, the cross-sectional area of the cross section perpendicular to the longitudinal direction of the word lines 100 is formed to increase as the distance from the first end of the bit line increases (FIG. 2).

Next, a method of fabricating an intersection memory device according to another embodiment of the present invention includes forming (S610) a plurality of bit lines 200 to be arranged parallel to each other, forming a plurality A step S620 of forming an intersection memory cell 300 of the intersection memory cell 300 and a step of forming a plurality of word lines 100 disposed at the top of the intersection memory cell 300 and arranged orthogonally and parallel to the bit line 200 (S630).

At this time, the cross-sectional area of the cross-section perpendicular to the longitudinal direction of the bit lines 200 is formed to increase as the distance from the first end of the word line increases (FIG. 4).

Next, a method of fabricating an intersection memory device according to another embodiment of the present invention includes forming (S610) a plurality of bit lines 200 to be arranged parallel to each other, forming a plurality A step S620 of forming an intersection memory cell 300 of the intersection memory cell 300 and a step of forming a plurality of word lines 100 disposed at the top of the intersection memory cell 300 and arranged orthogonally and parallel to the bit line 200 (S630).

At this time, the cross-sectional area of the cross-section perpendicular to the longitudinal direction of the bit line 200 and the word line 100 increases as the distance from the first end of the word line 100 and the first end of the bit line 200 increases (Fig. 5).

Each component can be fabricated three-dimensionally on a single crystal silicon substrate through a semiconductor manufacturing process such as a known thin film deposition, lithography, etching, and packaging.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10: Intersection memory device
100: Word line
200: bit line
300: memory cell
400: first controller
500: Second controller

Claims (10)

In an intersection memory device,
A plurality of word lines arranged in parallel with each other;
A plurality of bit lines orthogonal to the word lines and arranged parallel to each other; And
And a plurality of intersection memory cells (Cells) electrically connected between each word line and the bit line,
Sectional area of the cross-section perpendicular to the longitudinal direction of the bit lines increases as the distance from the first end of the word line increases. The method according to claim 1,
And the width of the bit lines increases as the distance from the first end of the word line increases. The method according to claim 1,
And wherein the thickness of the bit lines increases as the distance from the first end of the word line increases. The method according to claim 1,
The cross-sectional area of the cross-section perpendicular to the longitudinal direction of the word lines increases as the distance from the first end of the bit line increases. In an intersection memory device,
A plurality of word lines arranged in parallel with each other;
A plurality of bit lines orthogonal to the word lines and arranged parallel to each other; And
And a plurality of intersection memory cells (Cells) electrically connected between each word line and the bit line,
And a cross-sectional area of the cross-section perpendicular to the longitudinal direction of the word lines is formed to increase as the distance from the first end of the bit line increases. 6. The method of claim 5,
And the width of the word lines increases as the distance from the first end of the bit line increases. 6. The method of claim 5,
And the thickness of the word lines increases as the distance from the first end of the bit line increases. A method of manufacturing an intersection memory device,
Forming a plurality of bit lines to be arranged in parallel with each other;
Forming a plurality of intersection memory cells at predetermined points of the bit lines; And
And forming a plurality of word lines arranged at right angles and parallel to the bit lines at an upper end where the intersection memory cells are formed,
The cross-sectional area of the cross-section perpendicular to the longitudinal direction of the bit lines is increased as the distance from the first end of the word line increases. 9. The method of claim 8,
The step of forming the word lines to be arranged
Wherein a cross-sectional area of the cross-section perpendicular to the longitudinal direction of the word lines is increased as the distance from the first end of the bit line increases. A method of manufacturing an intersection memory device,
Forming a plurality of bit lines to be arranged in parallel with each other;
Forming a plurality of intersection memory cells at predetermined points of the bit lines; And
And forming a plurality of word lines arranged at right angles and parallel to the bit lines at an upper end where the intersection memory cells are formed,
Wherein the cross-sectional area of the cross-section perpendicular to the longitudinal direction of the word lines increases as the distance from the first end of the bit line increases.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100499635B1 (en) * 2002-12-31 2005-07-07 주식회사 하이닉스반도체 Method for patternning of wordline
US8437166B1 (en) 2011-11-16 2013-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Word line driver cell layout for SRAM and other semiconductor devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100499635B1 (en) * 2002-12-31 2005-07-07 주식회사 하이닉스반도체 Method for patternning of wordline
US8437166B1 (en) 2011-11-16 2013-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Word line driver cell layout for SRAM and other semiconductor devices

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