JP6045983B2 - Semiconductor memory device - Google Patents

Description

  The present embodiment relates to a semiconductor memory device.

  In recent years, with the high integration of semiconductor memory devices, LSI elements constituting the semiconductor memory devices have been increasingly miniaturized. The miniaturization of the LSI element requires not only a reduction in line width but also improvement in circuit pattern dimensional accuracy and position accuracy. As a technique for overcoming such a problem, ReRAM (Resistive RAM) using a variable resistance element that reversibly changes a resistance value as a memory has been proposed. In this ReRAM, the variable resistance element is provided between the side wall of the word line extending parallel to the substrate and the side wall of the bit line extending perpendicular to the substrate, so that the memory cell array can be further highly integrated. It is said that. However, the characteristics of the memory cells connected to the bit lines may vary.

JP 2009-88446 A

  The present embodiment provides a semiconductor memory device in which variation in characteristics of memory cells is suppressed.

  A semiconductor memory device according to an embodiment includes a memory cell array having a plurality of memory cells. The memory cell array has a plurality of first conductive layers, memory layers, and second conductive layers. The plurality of first conductive layers are stacked with a predetermined pitch in a first direction perpendicular to the substrate, and extend in a second direction parallel to the substrate. The memory layer is provided in common on the side surfaces of the plurality of first conductive layers and functions as a memory cell. The second conductive layer has a first side surface in contact with the side surfaces of the plurality of first conductive layers through the memory layer, and extends in the first direction. The width in the second direction of the first side surface at the first position is narrower than the width in the second direction of the first side surface at the second position below the first position. The thickness in the first direction of the first conductive layer disposed at the first position is thicker than the thickness in the first direction of the first conductive layer disposed at the second position.

1 is an example of a block diagram of a semiconductor memory device according to a first embodiment. 1 is an example of a circuit diagram of a memory cell array 11 according to a first embodiment. 1 is an example of a perspective view showing a stacked structure of a memory cell array 11 according to a first embodiment. It is the figure which looked at FIG. 3 from the X direction. FIG. 4 is a top view of FIG. 3. It is the figure which looked at FIG. 3 from the Y direction. 1 is an example of a perspective view showing a method for manufacturing a memory cell array 11 according to a first embodiment. 1 is an example of a perspective view showing a method for manufacturing a memory cell array 11 according to a first embodiment. 1 is an example of a perspective view showing a method for manufacturing a memory cell array 11 according to a first embodiment. 1 is an example of a perspective view showing a method for manufacturing a memory cell array 11 according to a first embodiment. It is the figure which looked at the memory layer 40 concerning 2nd Embodiment from the X direction. It is the figure which looked at the memory layer 40 which concerns on 3rd Embodiment from the X direction. It is the figure which looked at the memory layer 40 concerning 3rd Embodiment from the Y direction. It is an example of the perspective view which shows the manufacturing method of the memory cell array 11 concerning 3rd Embodiment. It is an example of the perspective view which shows the manufacturing method of the memory cell array 11 concerning 3rd Embodiment. It is an example of the perspective view which shows the manufacturing method of the memory cell array 11 concerning 3rd Embodiment. It is an example of the perspective view which shows the manufacturing method of the memory cell array 11 concerning 3rd Embodiment. It is the figure which looked at the memory layer 40 concerning 4th Embodiment from the X direction. It is the figure which looked at the memory layer 40 which concerns on other embodiment from the X direction. It is the figure which looked at the memory layer 40 which concerns on other embodiment from the Y direction.

[First Embodiment]
[Constitution]
First, the overall configuration of the semiconductor memory device according to the first embodiment will be described. FIG. 1 is an example of a block diagram of the semiconductor memory device according to the first embodiment. As shown in FIG. 1, the semiconductor memory device includes a memory cell array 11, a row decoder 12, a column decoder 13, an upper block 14, a power supply 15, and a control circuit 16.

  The memory cell array 11 includes a plurality of word lines WL and bit lines BL that intersect with each other, and memory cells MC that are arranged at each intersection. The row decoder 12 selects the word line WL at the time of access (data erase / write / read). The column decoder 13 includes a driver that selects a bit line BL and controls an access operation during access.

  The upper block 14 selects a memory cell MC to be accessed in the memory cell array 11. The upper block 14 gives a row address and a column address to the row decoder 12 and the column decoder 13, respectively. The power supply 15 generates a predetermined voltage combination corresponding to each operation of data erasing / writing / reading, and supplies it to the row decoder 12 and the column decoder 13. The control circuit 16 performs control such as sending an address to the upper block 14 according to a command from the outside, and also controls the power supply 15.

  Next, the memory cell array 11 according to the first embodiment will be described in detail with reference to FIGS. FIG. 2 is an example of a circuit diagram of the memory cell array 11. FIG. 3 is an example of a perspective view showing a stacked structure of the memory cell array 11. In FIG. 2, the X direction, the Y direction, and the Z direction are orthogonal to each other, and the X direction is a direction perpendicular to the paper surface. The structure shown in FIG. 2 is repeatedly provided in the X direction.

  As shown in FIG. 2, the memory cell array 11 includes a selection transistor STr, a global bit line GBL, and a selection gate line SG in addition to the above-described word line WL, bit line BL, and memory cell MC.

  As shown in FIGS. 2 and 3, the word lines WL1 to WL4 are arranged in the Z direction with a predetermined pitch and extend in the X direction. The bit lines BL are arranged in a matrix in the X direction and the Y direction, and extend in the Z direction. The memory cell MC is disposed at a location where the word line WL and the bit line BL intersect. Therefore, the memory cells MC are arranged in a three-dimensional matrix in the X, Y, and Z directions. In various operations, the same voltage can be applied to the selected word line WL among the word lines WL1 to WL4 regardless of the position in the Z direction. Further, the same voltage can be applied to unselected word lines WL in the word lines WL1 to WL4 regardless of their positions in the Z direction.

  As shown in FIG. 2, the memory cell MC includes a variable resistance element VR. The variable resistance element VR is electrically rewritable and stores data in a nonvolatile manner based on the resistance value. The variable resistance element VR changes from a high resistance state (reset state) to a low resistance state (set state) by a set operation in which a voltage above a certain level is applied to both ends thereof, and a voltage above a certain level is applied to both ends thereof. The reset operation changes from the low resistance state (set state) to the high resistance state (reset state). Further, the variable resistance element VR is in a state where the resistance state is not easily changed immediately after manufacture and is in a high resistance state. Therefore, a forming operation is performed in which a high voltage higher than the set operation and the reset operation is applied to both ends of the variable resistance element VR. By this forming operation, a region (filament path) where a current easily flows locally is formed in the variable resistance element VR, and the resistance state of the variable resistance element VR can be easily changed and can operate as a memory element. It becomes.

  As shown in FIG. 2, the select transistor STr is provided between one end of the bit line BL and the global bit line GBL. The global bit lines GBL are arranged with a predetermined pitch in the X direction and extend in the Y direction. One global bit line GBL is commonly connected to one ends of a plurality of select transistors STr arranged in a line in the Y direction. The gate electrodes of two select transistors STr arranged adjacent to each other in the Y direction are commonly connected. The selection gate lines SG are arranged with a predetermined pitch in the Y direction and extend in the X direction. One selection gate line SG is commonly connected to the gates of a plurality of selection transistors STr arranged in a line in the X direction. Note that the gate electrodes of the two selection transistors STr arranged adjacent to each other in the Y direction can be separated to operate the two selection transistors STr independently.

  Next, a stacked structure of the memory cell array 11 according to the first embodiment will be described with reference to FIG. 3, FIG. 4, and FIG. 4 is a view (ZY plan view) of the F4-F4 plane of FIG. 3 viewed from the X direction, and FIG. 5 is a top view of FIG. In FIGS. 3 and 5, the interlayer insulating layer is omitted.

  As shown in FIGS. 3 and 4, the memory cell array 11 includes a select transistor layer 30 and a memory layer 40 stacked on the substrate 20. The selection transistor layer 30 functions as a selection transistor STr, and the memory layer 40 functions as a memory cell MC.

  As shown in FIGS. 3 and 4, the select transistor layer 30 includes a conductive layer 31, an interlayer insulating layer 32, a conductive layer 33, and an interlayer insulating layer 34. The conductive layer 31, the interlayer insulating layer 32, the conductive layer 33, and the interlayer insulating layer 34 are stacked in the Z direction perpendicular to the substrate 20. The conductive layer 31 functions as the global bit line GBL, and the conductive layer 33 functions as the selection gate line SG and the gate of the selection transistor STr.

The conductive layers 31 are arranged with a predetermined pitch in the X direction parallel to the substrate 20 and extend in the Y direction (see FIG. 5). The interlayer insulating layer 32 covers the upper surface of the conductive layer 31. The conductive layers 33 are arranged at a predetermined pitch in the Y direction and extend in the X direction (see FIG. 5). The interlayer insulating layer 34 covers the side surface and the upper surface of the conductive layer 33. For example, the conductive layers 31 and 33 are made of polysilicon. The interlayer insulating layers 32 and 34 are made of silicon oxide (SiO ₂ ).

  The select transistor layer 30 includes a columnar semiconductor layer 35 and a gate insulating layer 36 as shown in FIGS. The columnar semiconductor layer 35 functions as a body (channel) of the selection transistor STr, and the gate insulating layer 36 functions as a gate insulating film of the selection transistor STr.

  The columnar semiconductor layers 35 are arranged in a matrix in the X and Y directions and extend in a column shape in the Z direction. The columnar semiconductor layer 35 is in contact with the upper surface of the conductive layer 31 and is in contact with the side surface in the Y direction of the conductive layer 33 through the gate insulating layer 36. The columnar semiconductor layer 35 includes a stacked N + type semiconductor layer 35a, P + type semiconductor layer 35b, and N + type semiconductor layer 35c.

As shown in FIGS. 3 and 4, the N + type semiconductor layer 35 a is in contact with the interlayer insulating layer 32 on the side surface in the Y direction. The P + type semiconductor layer 35b is in contact with the side surface of the conductive layer 33 at the side surface in the Y direction. The N + type semiconductor layer 35c is in contact with the interlayer insulating layer 34 on the side surface in the Y direction. The N + type semiconductor layers 35a and 35c are made of polysilicon implanted with N + type impurities, and the P + type semiconductor layer 35b is made of polysilicon implanted with P + type impurities. The gate insulating layer 36 is made of, for example, silicon oxide (SiO ₂ ).

As illustrated in FIGS. 3 and 4, the memory layer 40 includes interlayer insulating layers 41 a to 41 d and conductive layers 42 a to 42 d that are alternately stacked in the Z direction. Conductive layers 42a-42d function as word lines WL1-WL4, respectively. When viewed from the Z direction, the conductive layers 42a to 42d have a pair of comb-tooth shapes that face each other in the X direction (see FIG. 5). The interlayer insulating layers 41a to 41d are made of, for example, silicon oxide (SiO ₂ ), and the conductive layers 42a to 42d are made of, for example, polysilicon.

  Further, as shown in FIG. 4, the upper conductive layers 42a to 42d are thicker in the Z direction. That is, the thickness La4 in the Z direction of the conductive layer 42d is thicker than the thickness La3 in the Z direction of the lower conductive layer 42c. Similarly, the thickness La3 in the Z direction of the conductive layer 42c is thicker than the thickness La2 in the Z direction of the lower conductive layer 42b, and the thickness La2 in the Z direction of the conductive layer 42b is equal to the Z direction of the lower conductive layer 42a. It is thicker than the thickness La1. Here, it can be said that the film thickness of the conductive layers 42a to 42d is gradually increased in the Z direction.

  Further, the memory layer 40 includes a columnar conductive layer 43 and a variable resistance layer 44 as shown in FIGS. The columnar conductive layer 43 functions as the bit line BL. The variable resistance layer 44 functions as a variable resistance element VR.

The columnar conductive layers 43 are arranged in a matrix in the X and Y directions, are in contact with the upper surface of the columnar semiconductor layer 35, and extend in a column shape in the Z direction. The variable resistance layer 44 is provided between the side surface in the Y direction of the columnar conductive layer 43 and the side surface in the Y direction of the interlayer insulating layers 41a to 41d. The variable resistance layer 44 is provided between the side surface in the Y direction of the columnar conductive layer 43 and the side surface in the Y direction of the conductive layers 42a to 42d. The columnar conductive layer 43 is made of, for example, polysilicon, and the variable resistance layer 44 is made of, for example, a metal oxide (for example, HfO _X , Al ₂ O _X , TiO _X , NiO _X , WO _X , Ta ₂ O _X, etc.). The

  Next, the shape of the columnar semiconductor layer 43 and the conductive layers 42a to 42d will be described more specifically with reference to FIG. FIG. 6 is a view (ZX plan view) of the F6-F6 plane of FIG. 3 viewed from the Y direction. In FIG. 6, the interlayer insulating layers 41a to 41d and the variable resistance layer 44 are omitted.

  As shown in FIG. 6, the columnar semiconductor layer 43 is formed in a taper shape as viewed from the Y direction, and the width in the X direction of the side surface in the Y direction of the columnar semiconductor layer 43 proceeds in the + Z direction (upward direction in FIG. 6). It becomes narrower as it goes. That is, the width in the X direction of the side surface in the Y direction of the columnar semiconductor layer 43 at the first position is narrower than the width in the X direction of the side surface in the Y direction of the columnar semiconductor layer 43 at the second position below the first position. . The tapered shape of the columnar semiconductor layer 43 can be formed by adjusting the etching conditions during manufacturing, which will be described later. As described above, in this embodiment, the upper conductive layers 42a to 42d are made thicker in the Z direction. Here, assuming that the thickness of the conductive layers 42a to 42d in the Z direction is uniform, the opposing area between the conductive layer 42a and the columnar semiconductor layer 43 is the largest, and the opposing area between the conductive layer 42d and the columnar semiconductor layer 43 is The smallest. As a result, the characteristics of the variable resistance element VR formed between the conductive layers 42a to 42d (word lines WL1 to WL4) and the columnar semiconductor layer 43 (bit line BL) vary.

  Therefore, in the present embodiment, as shown in FIG. 6, the thicknesses La1 to La4 in the Z direction are made thicker in the upper conductive layers 42a to 42d corresponding to the shape of the columnar semiconductor layer 43. . Therefore, the facing area between the conductive layers 42 a to 42 d and the columnar semiconductor layer 43 can be made substantially constant. Thereby, this Embodiment can suppress the dispersion | variation in the characteristic of the variable resistance element VR.

[Production method]
A method for manufacturing the semiconductor memory device according to the first embodiment will now be described with reference to FIGS. 7 to 10 are examples of perspective views showing a method for manufacturing the memory cell array 11. In the manufacturing method described below, only the manufacturing method of the memory layer 40 is shown.

As shown in FIG. 7, silicon oxide (SiO ₂ ) and polysilicon (Si) are alternately stacked on the upper surface of the select transistor layer 30, and the interlayer insulating layers 41 a ′ to 41 d ′ extending in the X direction and the Y direction are electrically conductive. Layers 42a′-42d ′ are formed. In addition, a protective layer 51 ′ is formed on the conductive layer 42d ′. Here, the thickness La4 in the Z direction of the conductive layer 42d ′ is thicker than the thickness La3 in the Z direction of the conductive layer 42c ′ underneath. Similarly, the thickness La3 in the Z direction of the conductive layer 42c ′ is thicker than the thickness La2 in the Z direction of the lower conductive layer 42b ′, and the thickness La2 in the Z direction of the conductive layer 42b ′ is equal to the lower conductive layer 42a. It is thicker than the thickness La1 in the Z direction. Here, it can be said that the film thickness of the conductive layers 42a ′ to 42d ′ gradually increases in the Z direction. It should be noted that various changes can be made, for example, by making the film thickness of the two conductive layers the same and increasing the film thickness of the conductive layer every two layers.

  As shown in FIG. 8, a trench T1 penetrating the interlayer insulating layers 41a 'to 41d', the conductive layers 42a 'to 42d', and the protective layer 51 'is formed. The trenches T1 are arranged with a predetermined pitch in the Y direction and extend in the X direction. Due to the trench T1, the interlayer insulating layers 41a ′ to 41d ′, the conductive layers 42a ′ to 42d ′, and the protective layer 51 ′ are formed into the interlayer insulating layers 41a to 41d, the conductive layers 42a to 42d, and the protective layer 51 that extend in the X direction. It becomes.

  As shown in FIG. 9, the variable resistance layer 44 is formed on the side surface of the trench T1. Then, a columnar semiconductor layer 43 'is formed so as to fill the trench T1. For example, the variable resistance layer 44 is formed by depositing a metal oxide by atomic layer deposition (ALD). Here, the variable resistance layer 44 is formed in a planar shape on all side surfaces of the trench T1.

  As shown in FIG. 10, a trench T2 penetrating the columnar semiconductor layer 43 'is formed. The trenches T2 are arranged with a predetermined pitch in the X direction. Due to the trench T <b> 2, the columnar semiconductor layer 43 ′ is processed into a tapered shape when viewed in the XZ plane, and becomes the columnar semiconductor layer 43. Then, the trench T2 is filled with silicon oxide, and an interlayer insulating layer is formed in the trench T2.

[Second Embodiment]
[Constitution]
Next, a semiconductor memory device according to the second embodiment will be described with reference to FIG. FIG. 11 illustrates an example of the memory layer 40 viewed from the X direction according to the second embodiment. As shown in FIG. 11, in the memory layer 40 of the second embodiment, the thickness of the variable resistance layer 44 in the Y direction decreases as it proceeds in the −Z direction (downward in FIG. 11). Accordingly, the voltage required to change the resistance value of the variable resistance layer 44 in contact with the conductive layers 42a to 42d positioned higher is higher. Therefore, in the second embodiment, similarly to the first embodiment, the thicknesses La1 to La4 in the Z direction are increased in the upper conductive layers 42a to 42d. With this thickness, the wiring resistance becomes lower in the conductive layers 42a to 42d located in the upper layers. Therefore, when the same voltage is applied to one end of the conductive layers 42 a to 42 d to transfer the voltage to the variable resistance layer 44, the higher voltage is applied to the variable resistance layer 44 located in the upper layer. Thereby, 2nd Embodiment can change the resistance value of the some variable resistance layer 44 uniformly.

  In addition, the contact area between the conductive layer 42 d located in the upper layer and the variable resistance layer 44 is larger than the contact area between the conductive layer 42 c located in the lower layer and the variable resistance layer 44. Here, when the film thickness of the variable resistance layer 44 is increased, the forming voltage is increased, and when the contact area between the conductive layer 42 and the variable resistance layer 44 is increased, the forming voltage tends to be decreased. Therefore, even when the thickness of the upper variable resistance layer 44 is increased, the contact area between the conductive layer 42d and the variable resistance layer 44 is increased, so that the forming voltage does not increase. Thus, in the second embodiment, even when the same forming voltage is used from the upper layer to the lower layer, the lower variable resistance layer 44 can be reliably formed.

[Third Embodiment]
[Constitution]
Next, a semiconductor memory device according to the third embodiment will be described with reference to FIGS. 12 shows the memory layer 40 viewed from the X direction, and FIG. 13 shows the memory layer 40 viewed from the Y direction. In FIG. 13, the interlayer insulating layers 41a to 41d and the variable resistance layer 44 are omitted. 12 corresponds to the F4-F4 cross section in FIG. 3, and the plane in FIG. 13 corresponds to the F6-F6 cross section in FIG.

  In the third embodiment, as shown in FIG. 13, the columnar semiconductor layer 43 is formed in an inversely tapered shape when viewed from the Y direction, and the width in the X direction of the side surface of the columnar semiconductor layer 43 in the Y direction is −Z. It narrows gradually as it proceeds in the direction (downward in FIG. 13). That is, the width in the X direction of the side surface in the Y direction of the columnar semiconductor layer 43 at the first position is narrower than the width in the X direction of the side surface in the Y direction of the columnar semiconductor layer 43 at the second position above the first position. . In addition, the reverse taper shape of this columnar semiconductor layer 43 can be formed by adjusting the etching conditions at the time of manufacture mentioned later. Here, if the thickness of the conductive layers 42a to 42d in the Z direction is uniform, the opposing area between the conductive layer 42d and the columnar semiconductor layer 43 is the largest, and the opposing area between the conductive layer 42a and the columnar semiconductor layer 43 is The smallest. As a result, the characteristics of the variable resistance element VR formed between the conductive layers 42a to 42d (word lines WL1 to WL4) and the columnar semiconductor layer 43 (bit line BL) vary.

  Therefore, in the present embodiment, as shown in FIGS. 12 and 13, corresponding to the shape of the columnar semiconductor layer 43, the lower conductive layers 42a to 42d have thicker thicknesses Lb1 to Lb4 in the Z direction. doing. Specifically, the thickness Lb1 in the Z direction of the conductive layer 42a is thicker than the thickness Lb2 in the Z direction of the upper conductive layer 42b. Similarly, the thickness Lb2 in the Z direction of the conductive layer 42b is thicker than the thickness Lb3 in the Z direction of the upper conductive layer 42c, and the thickness Lb3 in the Z direction of the conductive layer 42c is the Z direction of the upper conductive layer 42d. It is thicker than the thickness Lb4. Therefore, the facing area between the conductive layers 42 a to 42 d and the columnar semiconductor layer 43 can be made substantially constant. Thereby, this Embodiment can suppress the dispersion | variation in the characteristic of the variable resistance element VR.

[Production method]
Next, an example of a method of manufacturing the semiconductor memory device according to the third embodiment will be described with reference to FIGS. 14 to 17 are perspective views showing a method for manufacturing the memory cell array 11. FIG. In the manufacturing method described below, only the manufacturing method of the memory layer 40 is shown.

  As shown in FIG. 14, interlayer insulating layers 41a 'to 41d', conductive layers 42a 'to 42d', and protective layer 51 'are formed as in the first embodiment. Here, the thickness Lb1 in the Z direction of the conductive layer 42a 'is thicker than the thickness Lb2 in the Z direction of the upper conductive layer 42b'. Similarly, the thickness Lb2 in the Z direction of the conductive layer 42b ′ is thicker than the thickness Lb3 in the Z direction of the upper conductive layer 42c ′, and the thickness Lb3 in the Z direction of the conductive layer 42c ′ is equal to the upper conductive layer 42d. It is thicker than the thickness Lb4 in the Z direction. Here, it can be said that the film thickness of the conductive layers 42a 'to 42d' is gradually reduced in the Z direction. It should be noted that various changes can be made, for example, by making the film thicknesses of the two conductive layers the same and reducing the film thickness of the conductive layers every two layers.

  As shown in FIG. 15, the trench T3 penetrating the interlayer insulating layers 41a ′ to 41d ′, the conductive layers 42a ′ to 42d ′, and the protective layer 51 ′ is formed in the same manner as the trench T1 of the first embodiment. . The trenches T3 are arranged with a predetermined pitch in the X direction. Due to the trench T3, the interlayer insulating layers 41a ′ to 41d ′, the conductive layers 42a ′ to 42d ′, and the protective layer 51 ′ are formed into the interlayer insulating layers 41a to 41d, the conductive layers 42a to 42d, and the protective layer 51 that extend in the X direction. It becomes.

  As shown in FIG. 16, the variable resistance layer 44 is formed on the side surface of the trench T3. Then, an interlayer insulating layer 45 'is formed so as to fill the trench T3.

  Subsequently, as shown in FIG. 17, a trench T4 penetrating the interlayer insulating layer 45 'is formed. The trenches T4 are arranged with a predetermined pitch in the X direction. When viewed in the XZ plane, the interlayer insulating layer 45 ′ is processed into a tapered shape by the trench T <b> 4 and becomes the interlayer insulating layer 45. Then, the trench T4 is filled with polysilicon, and the columnar semiconductor layer 43 is formed in the trench T4.

[Fourth Embodiment]
[Constitution]
Next, an example of a semiconductor memory device according to the fourth embodiment will be described with reference to FIG. FIG. 18 shows the memory layer 40 as viewed from the X direction. As shown in FIG. 18, in the memory layer 40 of the fourth embodiment, the thickness of the variable resistance layer 44 in the Y direction increases as it proceeds in the −Z direction (downward in FIG. 11). Therefore, the voltage required for changing the resistance value of the variable resistance layer 44 in contact with the conductive layers 42d to 42b located in the lower layer becomes higher. Therefore, in the fourth embodiment, similarly to the third embodiment, the lower conductive layers 42a to 42dLb1 to Lb4 are made thicker in the Z direction. With this thickness, the conductive resistances 42a to 42d located at lower layers become lower in wiring resistance. Therefore, when the same voltage is applied to one end of the conductive layers 42 a to 42 d to transfer the voltage to the variable resistance layer 44, a higher voltage is applied to the variable resistance layer 44 located in a lower layer. Thereby, in the fourth embodiment, the resistance values of the plurality of variable resistance layers 44 can be changed uniformly.

  Further, the contact area between the conductive layer 42 a located in the lower layer and the variable resistance layer 44 is larger than the contact area between the conductive layer 42 b located in the upper layer and the variable resistance layer 44. Here, when the film thickness of the variable resistance layer 44 is increased, the forming voltage is increased, and when the contact area between the conductive layer 42 and the variable resistance layer 44 is increased, the forming voltage tends to be decreased. Therefore, even when the thickness of the lower variable resistance layer 44 is increased, the contact area between the conductive layer 42a and the variable resistance layer 44 is increased, so that the forming voltage does not increase. Thus, in the fourth embodiment, the lower variable resistance layer 44 can be reliably formed even when the same forming voltage is used from the upper layer to the lower layer.

[Others]
Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, as shown in FIGS. 19 and 20, when the resistance values of the plurality of variable resistance elements VR can be changed uniformly in the fourth embodiment, the thickness Lc in the Z direction of the conductive layers 42a to 42d is constant. Also good.

  DESCRIPTION OF SYMBOLS 11 ... Memory cell array, 12 ... Row decoder, 13 ... Column decoder, 14 ... Upper block, 15 ... Power supply, 16 ... Control circuit, 20 ... Substrate, 30 ... Selection transistor layer, 40 ... Memory layer

Claims (11)

Comprising a memory cell array having a plurality of memory cells;
The memory cell array includes:
A plurality of first conductive layers stacked at a predetermined pitch in a first direction perpendicular to the substrate and extending in a second direction parallel to the substrate;
A memory layer provided in common on the side surfaces of the plurality of first conductive layers and functioning as the memory cell;
A second conductive layer having a first side surface in contact with the side surfaces of the plurality of first conductive layers through the memory layer and extending in the first direction;
The width in the second direction of the first side surface at the first position is narrower than the width in the second direction of the first side surface at the second position below the first position,
Wherein the first direction of the thickness of the first first conductive layer disposed on the position, rather than thickness than the first direction of the thickness of the first conductive layer disposed on the second position,
The facing area between the first conductive layer and the second conductive layer at the first position and the facing area between the first conductive layer and the second conductive layer at the second position are substantially constant. A semiconductor memory device. A direction perpendicular to the first direction and the second direction is a third direction,
2. The semiconductor memory device according to claim 1, wherein a thickness of the memory layer in the first position in the third direction is larger than a thickness of the memory layer in the second position in the third direction. The memory layer is a variable resistance layer;
The semiconductor memory device according to claim 1, wherein the semiconductor memory device is arranged in a planar shape constituted by the first direction and the second direction. The semiconductor memory device according to claim 1, wherein the first conductive layer is formed in a comb shape when viewed in the first direction. Comprising a memory cell array having a plurality of memory cells;
The memory cell array includes:
A plurality of first conductive layers stacked at a predetermined pitch in a first direction perpendicular to the substrate and extending in a second direction parallel to the substrate;
A memory layer provided in common on the side surfaces of the plurality of first conductive layers and functioning as the memory cell;
A second conductive layer having a first side surface in contact with the side surfaces of the plurality of first conductive layers through the memory layer and extending in the first direction;
The width in the second direction of the first side surface at the first position is narrower than the width in the second direction of the first side surface at the second position above the first position,
Wherein the first direction of the thickness of the first first conductive layer disposed on the position, rather than thickness than the first direction of the thickness of the first conductive layer disposed on the second position,
The facing area between the first conductive layer and the conductive layer at the first position and the facing area between the first conductive layer and the second conductive layer at the second position are substantially constant. Semiconductor memory device. A direction perpendicular to the first direction and the second direction is a third direction,
6. The semiconductor memory device according to claim 5, wherein a thickness of the memory layer in the first position in the third direction is thicker than a thickness of the memory layer in the second position in the third direction. The memory layer is a variable resistance layer;
The semiconductor memory device according to claim 5, wherein the semiconductor memory device is arranged in a planar shape constituted by the first direction and the second direction. The semiconductor memory device according to claim 5, wherein the first conductive layer is formed in a comb shape when viewed in the first direction. Comprising a memory cell array having a plurality of memory cells;
The memory cell array includes:
A plurality of first conductive layers stacked at a predetermined pitch in a first direction perpendicular to the substrate and extending in a second direction parallel to the substrate;
A memory layer provided in common on the side surfaces of the plurality of first conductive layers and functioning as the memory cell;
A second conductive layer having a first side surface in contact with the side surfaces of the plurality of first conductive layers through the memory layer and extending in the first direction;
The width in the second direction of the first side surface at the first position is narrower than the width in the second direction of the first side surface at the second position above the first position,
A direction perpendicular to the first direction and the second direction is a third direction,
The third direction of thickness of the memory layer in the first position, rather thick than said third direction of thickness of the memory layer in the second position,
A thickness of the first conductive layer disposed at the first position in the first direction is equal to or greater than a thickness of the first conductive layer disposed at the second position in the first direction. apparatus. The memory layer is a variable resistance layer;
The semiconductor memory device according to claim 9, wherein the semiconductor memory device is arranged in a planar shape constituted by the first direction and the second direction. The semiconductor memory device according to claim 9, wherein the first conductive layer is formed in a comb shape when viewed in the first direction.

Images