KR100490043B1 - Planar drive type liquid crystal display device and its manufacturing method - Google Patents

Abstract

After depositing and patterning a chromium film and an aluminum-neodymium alloy film in sequence, a gate line, a gate pad, a common electrode line, and a common electrode are formed. Then, a gate insulating film, an amorphous silicon layer, and a doped amorphous silicon layer are laminated and the above two layers are stacked. Pattern. Next, the gate insulating film on the gate pad is removed and a molybdenum-tungsten alloy film is deposited and patterned to form a lower data line and a lower data pad and a metal layer over the exposed gate pad. An ITO layer is deposited and patterned thereon to form an upper data line and an upper data pad covering the lower data line and the lower data pad, an ITO film and a pixel electrode on the metal layer on the gate pad, and then a protective film that exposes each pad. Form.

In the planar drive type liquid crystal display device manufactured by this method, since the ITO film is formed on the top of the gate pad and the data pad part, the adhesive force of the pad part is improved, and thus the pad part reliability is increased. In addition, since the pixel electrode is formed of ITO having a small thickness to minimize the step, the liquid crystal alignment can be smoothly performed, and since the ITO film covers the data line, disconnection of the data line can be prevented.

Description

Planar drive type liquid crystal display device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a liquid crystal display device using an in-plane-switching method and a method for manufacturing the same.

An IPS type liquid crystal display has a pixel electrode and a common electrode on a substrate, and wirings such as the electrode, the gate line, and the data line are made of metal.

Electrodes and wires may be made of an alloy of molybdenum (Mo) and tungsten (W), or a single film such as chromium (Cr) or titanium (Ti), but have a disadvantage in that repair may not be possible in case of disconnection.

In order to solve this problem, a wiring and an electrode having a double layer structure in which an alloy layer of aluminum (Al) and neodymium (Nd) are placed on the chromium layer are formed.

In such a liquid crystal display device, an aluminum-neodymium alloy layer or a chromium layer is exposed on the gate pad and the data pad part so that the driving element is formed in contact with the aluminum-neodymium alloy layer or the chromium layer. The adhesive force of the portion may be degraded, and thus, the reliability of the pad portion may be deteriorated.

In addition, since the pixel electrode is made of a thick metal layer, the step height is large, so that the alignment of the pulses tends to be poor.

The problem to be solved by the present invention is to improve the reliability of the pad portion of the liquid crystal display device and to reduce the orientation defect of the liquid crystal.

In order to achieve the object of the present invention, in the step of forming the data line and the pixel electrode, an alloy of molybdenum and tungsten is deposited and patterned to form a lower layer of the data line, and then an ITO layer is deposited and patterned to a thickness of 500 kV to form the data line. An upper film and a pixel electrode are formed.

In this way, ITO having good adhesion to the pad part is positioned at the top to contact the driving element. Therefore, the pad part can be increased in reliability, and the pixel electrode is formed to a thickness of 500 kV to minimize the relative step so that the liquid crystal alignment is smooth. Can be done. In addition, since the data line is formed of a double layer, in particular, the ITO can be formed to cover the lower layer because the ITO can easily pass over the step portion, which is advantageous in preventing short circuit of the data line.

Next, a liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings so that a person skilled in the art may easily implement the present invention.

1 is a layout view of a planar driving type thin film transistor substrate according to the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1. First, an embodiment of the present invention will be described with reference to FIGS. 1 and 2. The structure of the liquid crystal display device which concerns on an example is demonstrated.

The gate line 10 and the gate pad 15 connected to the end thereof are formed on the transparent insulating substrate 1 in one direction, and a pair of common electrode lines 20 formed in parallel with the gate line 10 are formed. A plurality of common electrodes 23 connecting the common electrode lines and parallel to each other are formed on the substrate 1. The gate line 10, the gate pad 15, and the common electrode line 20 may be formed of a lower chromium layer 11, 16, 21, and an upper aluminum-neodymium alloy layer 12, 17, 22. Although not shown, the common electrode 23 also consists of these double films.

The gate line 10, the gate pad 15, the common electrode line 20, and the common electrode 23 are covered with the gate insulating film 20, and the gate insulating film 20 has a contact hole 18 exposing the gate pad 15. Have

The lower data line 51 crossing the gate line 10 and the common electrode line 20 and the lower data pad 510 extending from the lower data line 51 are formed on the gate insulating layer 30. The lower data line 51 and the lower gate pad 510 are formed of a molybdenum-tungsten alloy layer, and an upper data line 52 and an upper data pad 520 which are an ITO layer are formed thereon.

An amorphous silicon layer 61 serving as an active layer is formed on the gate insulating film 30 at a portion corresponding to the gate electrode of the gate line 10, and source electrodes 63 extending from the data line 51 on both sides thereof. ), A drain electrode 64 is formed therebetween. A doped amorphous silicon layer 62 is formed between the source electrode 63 and the drain electrode 64 and the amorphous silicon layer 61 to improve electrical contact characteristics, and the drain electrode 64 extends to the common electrode. A plurality of pixel electrodes 40 positioned between the 23 and connected to each other are formed.

Meanwhile, a molybdenum-tungsten alloy layer 53 and an ITO film 54 are formed on the contact hole 18 exposing the gate pad 15, except for the part of the ITO film 54 and the upper data pad 520. The rest is covered with a protective shield.

As described above, since the uppermost layers of the gate pad portion A and the data pad portion B are each made of ITO, the driving element is in contact with the ITO layers 54 and 520 instead of the aluminum alloy layer or the chromium layer, so that the adhesive force of the pad portion The reliability of the pad part can be improved.

Next, a method of manufacturing a planar driving type thin film transistor substrate having such a structure will be described with reference to FIGS. 2 and 3A to 3C. 3A to 3C sequentially show cross sections of the cutting line II-II 'in FIG. 1.

First, the chromium layer 11 and the aluminum-neodymium alloy layer 12 are deposited on the insulating substrate 1 to a thickness of 500 kPa and 2,500 kPa, respectively, and then patterned using a first mask, as shown in FIGS. 2 and 3A. As described above, the gate line 10, the gate pad 15, the common electrode line 20, and the common electrode 20 are formed.

Next, as shown in FIGS. 2 and 3B, the gate insulating film 30, the amorphous silicon layer 61, and the doped amorphous silicon layer 62 are sequentially stacked in a thickness of 4,500 kPa, 200 kPa, and 500 kPa. The doped amorphous silicon layer 61 and the amorphous silicon layer 62 are patterned using the first mask. The gate insulating layer 30 on the gate pad 15 is etched using the third mask.

After depositing the molybdenum-tungsten alloy layer to a thickness of 4,000 Å, the lower data line 51, the lower data pad 510 and the molybdenum-neodymium alloy layer 53 are formed using a fourth mask, as shown in FIG. 3C. As can be seen, the upper data line 52 and the upper data pad 520, the pixel electrode 40, the source, the drain electrodes 63 and 64, and the ITO film are deposited using a fifth mask after depositing an ITO film of 500 Å. Form 54. Through this manufacturing method, the pixel electrode 40 has a thickness different from that of the data line 51. Since the thickness of the pixel electrode 40 having a thickness thinner than that of the data line 51 is about 500 μs, the step can be reduced. .

Next, the doped amorphous silicon layer 62 exposed using the source and drain electrodes 63 and 64 as a mask is etched, and then the protective film 70 is deposited to a thickness of 2,000 Å and patterned using a sixth mask to form a pad. Expose wealth (A, B).

In this case, the ITO film 52 deposited on the lower data line 51 formed as a double layer can easily pass over the step portion of the data line so that the ITO film 52 is formed to surround the lower film, thereby preventing disconnection of the data line. have.

As mentioned above, since the ITO layer is formed on the pad, the adhesive force of the pad part can be increased, and the pixel electrode is formed of thin ITO to minimize the step difference, so that the liquid crystal alignment can be smoothly performed. In addition, since the data line is formed of a double film, and in particular, the ITO film, which is an upper layer film, covers the lower film, disconnection of the data line can be prevented.

1 is a layout view of a planar driving type thin film transistor substrate according to the present invention;

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1,

3A to 3C are cross-sectional views sequentially illustrating the cross section of the cutting line II-II 'in FIG. 1 according to the manufacturing method.

Claims (9)

A gate wiring including a gate line formed on the insulating substrate and a gate pad connected thereto; A common electrode line formed in parallel with the gate line; A plurality of common electrodes connected to the common electrode line, A gate insulating film formed on the gate wiring, the common electrode line, and the common electrode and having a contact hole for exposing the gate pad; A plurality of pixel electrodes formed on the gate insulating layer between the common electrodes; A data line formed on the gate insulating layer and connected to the pixel electrode, the data line having a thickness different from that of the pixel electrode, and a data pad connected thereto; An ITO film formed on the gate pad exposed through the contact hole Flat drive type liquid crystal display device comprising a. In claim 1, The data line and the data pad may include a lower metal layer and an upper ITO layer. In claim 2, The gate line and the gate pad may include a lower chromium layer and an upper aluminum-neodymium layer. In claim 2, The ITO film of the data line completely covers the metal film. In claim 2, And a lower metal layer of the data line is formed of molybdenum-tungsten alloy. Forming a gate line, a gate pad connected to the gate electrode, and a common electrode on the transparent insulating substrate; Stacking the gate insulating film and the semiconductor layer one after another, Patterning the semiconductor layer, Etching a gate insulating film on the gate pad to form a contact hole; Depositing and patterning an alloy of molybdenum and tungsten to form a lower data line and a lower data pad, Depositing an ITO layer, Patterning the ITO layer to form a first layer covering the upper data line and the upper data pad and the pixel electrode on the lower data line and the lower data pad and the gate pad exposed through the contact hole; And forming a passivation layer exposing the first layer and the upper data pad. In claim 6, The gate line and the gate pad are formed of a lower chromium layer and an upper aluminum-neodymium layer. In claim 6, The upper data line is formed to completely cover the lower data line. In claim 6, The lower data line is formed of molybdenum-tungsten alloy.