JPH09293877A - Wiring structure and formation thereof - Google Patents

Wiring structure and formation thereof

Info

Publication number
JPH09293877A
JPH09293877A JP12926496A JP12926496A JPH09293877A JP H09293877 A JPH09293877 A JP H09293877A JP 12926496 A JP12926496 A JP 12926496A JP 12926496 A JP12926496 A JP 12926496A JP H09293877 A JPH09293877 A JP H09293877A
Authority
JP
Japan
Prior art keywords
connection pad
film
mask
wiring
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12926496A
Other languages
Japanese (ja)
Other versions
JP3543130B2 (en
Inventor
Makoto Miyagawa
誠 宮川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP12926496A priority Critical patent/JP3543130B2/en
Publication of JPH09293877A publication Critical patent/JPH09293877A/en
Application granted granted Critical
Publication of JP3543130B2 publication Critical patent/JP3543130B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13458Terminal pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05009Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049Nitrides composed of metals from groups of the periodic table
    • H01L2924/050414th Group
    • H01L2924/05042Si3N4

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Liquid Crystal (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Thin Film Transistor (AREA)
  • Mathematical Physics (AREA)
  • Wire Bonding (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PROBLEM TO BE SOLVED: To enable east and perfect removal of an anodic oxidation mask formed in the surface of a connection pad connected to a gate electrode via a gate line, after an anodic oxidation film is formed on the surface of the gate electrode for formation of a thin-film transistor in an active matrix type liquid crystal display unit. SOLUTION: Only the surface of a connection pad 14 is covered with an anodic oxidation mask 17 made of silicon oxide, under which condition to pad is anodized to form an anodic oxidation film 18 on the surface of a gate electrode 12. Next, a gate insulating film 19 made of silicon nitride is formed all over the film 18. Thereafter, a contact hole 25 is made in the gate insulating film 19 and anodic oxidation mask 17 at their parts corresponding to a central part of the connection pad 19. In this case, the film 19 and mask 17 can be easily etched collectively. In addition, the mask 17 can be perfectly removed from on the top face of the pad 14 in the contact hole 25.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は配線の構造及びそ
の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure and a method for forming the structure.

【0002】[0002]

【従来の技術】例えば、アクティブマトリックス型の液
晶表示装置においては、スイッチング素子としての薄膜
トランジスタのゲート電極をAl−Ti(Tiを含有す
るAl合金)によって形成し、陽極酸化を行うことによ
り、ゲート電極の表面にAl−Ti−Oxからなる陽極
酸化膜を形成し、この陽極酸化膜をゲート絶縁膜の一部
として機能させることにより、本来のゲート絶縁膜の絶
縁耐圧を補うようにしたものがある。
2. Description of the Related Art For example, in an active matrix type liquid crystal display device, a gate electrode of a thin film transistor as a switching element is formed of Al-Ti (Al alloy containing Ti), and anodization is performed to form a gate electrode. There is a structure in which an anodic oxide film made of Al-Ti-Ox is formed on the surface of and the anodic oxide film is made to function as a part of the gate insulating film to supplement the original breakdown voltage of the gate insulating film. .

【0003】次に、従来のこのような液晶表示装置にお
けるゲート電極などからなるゲート配線の形成方法の一
例について、図11〜図14を順に参照しながら説明す
る。まず、図11(A)、(B)に示すように、ガラス
基板1の上面全体にAl−Tiからなるゲート配線(ゲ
ート電極を含むゲートライン及び該ゲートラインに接続
された接続パッドからなるゲート配線)形成用膜2を成
膜する。次に、ゲート配線形成用膜2の上面の所定の個
所に第1フォトレジストマスク3を形成する。次に、ド
ライエッチングあるいはウェットエッチングを行うと、
図12(A)、(B)に示すように、第1フォトレジス
トマスク3下にゲート電極4を含むゲートライン5及び
このゲートライン5の所定の一端部に接続された接続パ
ッド6が形成される。この後、第1フォトレジストマス
ク3を除去する。次に、図13(A)、(B)に示すよ
うに、接続パッド6の表面のみを被うように第2フォト
レジストマスク7を形成する。次に、陽極酸化を行う
と、図14(A)、(B)に示すように、第2フォトレ
ジストマスク7によって被われていないゲートライン5
の表面及びゲート電極4の表面にAl−Ti−Oxから
なる陽極酸化膜8が形成される。この後、第2フォトレ
ジストマスク7を除去すると、接続パッド6の表面が露
出される。この場合、接続パッド6の表面に陽極酸化膜
を形成しないのは、陽極酸化膜が絶縁性を有するので、
接続パッド6の接続機能を阻害しないようにするためで
ある。
Next, an example of a method of forming a gate wiring composed of a gate electrode and the like in such a conventional liquid crystal display device will be described with reference to FIGS. 11 to 14 in order. First, as shown in FIGS. 11A and 11B, a gate wiring made of Al—Ti (a gate line including a gate electrode and a gate made of a connection pad connected to the gate line is formed on the entire upper surface of the glass substrate 1. A wiring) forming film 2 is formed. Next, the first photoresist mask 3 is formed at a predetermined position on the upper surface of the gate wiring forming film 2. Next, if dry etching or wet etching is performed,
As shown in FIGS. 12A and 12B, a gate line 5 including a gate electrode 4 and a connection pad 6 connected to a predetermined one end of the gate line 5 are formed under the first photoresist mask 3. It After that, the first photoresist mask 3 is removed. Next, as shown in FIGS. 13A and 13B, a second photoresist mask 7 is formed so as to cover only the surface of the connection pad 6. Next, when anodic oxidation is performed, as shown in FIGS. 14A and 14B, the gate line 5 not covered with the second photoresist mask 7 is formed.
An anodic oxide film 8 made of Al-Ti-Ox is formed on the surface of the gate electrode 4 and the surface of the gate electrode 4. After that, when the second photoresist mask 7 is removed, the surface of the connection pad 6 is exposed. In this case, the reason why the anodic oxide film is not formed on the surface of the connection pad 6 is that the anodic oxide film has an insulating property.
This is to prevent the connection function of the connection pad 6 from being hindered.

【0004】[0004]

【発明が解決しようとする課題】ところで、陽極酸化用
の第2フォトレジストマスク7は、陽極酸化中に剥離し
ないようにするために、エッチング用の第1フォトレジ
ストマスク3を形成する際のベークと比較して、高温で
長い時間のベークによって形成している。このため、陽
極酸化用の第2フォトレジストマスク7の剥離性が悪く
なり、この第2フォトレジストマスク7を除去する際
に、接続パッド6の表面に部分的に残ることがある。そ
して、この部分的に残った第2フォトレジストマスク7
は、後述するコンタクトホール形成時のエッチングでは
除去できない。このような場合には、図示していない
が、接続パッド6の表面に形成されるあるいは接続され
る接続電極と接続パッド6との導通性が悪くなり、ひい
ては薄膜トランジスタが動作しなくなることがあるとい
う問題があった。この発明の課題は、接続パッドの表面
に形成された陽極酸化用マスクを容易にかつ完全に除去
することができるようにすることである。
By the way, the second photoresist mask 7 for anodization is baked at the time of forming the first photoresist mask 3 for etching so as not to be peeled off during anodization. Compared with, it is formed by baking at high temperature for a long time. Therefore, the peelability of the second photoresist mask 7 for anodic oxidation is deteriorated, and when the second photoresist mask 7 is removed, it may partially remain on the surface of the connection pad 6. Then, the second photoresist mask 7 that partially remains
Cannot be removed by etching, which will be described later, when forming a contact hole. In such a case, although not shown, the conductivity between the connection electrode formed on or connected to the surface of the connection pad 6 and the connection pad 6 may deteriorate, and the thin film transistor may not operate. There was a problem. An object of the present invention is to make it possible to easily and completely remove the anodizing mask formed on the surface of the connection pad.

【0005】[0005]

【課題を解決するための手段】請求項1記載の発明に係
る配線の構造は、接続パッドを有する配線の表面のうち
前記接続パッドの周囲部が無機膜によって被われ、少な
くとも前記接続パッドの中央部を除く前記配線の表面に
陽極酸化膜が形成されているものである。請求項4記載
の発明に係る配線の形成方法は、接続パッドを有する配
線の表面のうち少なくとも前記接続パッドの一部を無機
膜によって被い、この状態で陽極酸化を行うことによ
り、前記無機膜によって被われていない前記配線の表面
に陽極酸化膜を形成するようにしたものである。
According to a first aspect of the present invention, there is provided a wiring structure in which a peripheral portion of the connection pad on the surface of the wiring having the connection pad is covered with an inorganic film, and at least the center of the connection pad is formed. An anodic oxide film is formed on the surface of the wiring except the part. According to a fourth aspect of the present invention, in the method for forming a wiring, the inorganic film covers at least a part of the connection pad on the surface of the wiring having the connection pad, and anodization is performed in this state to form the inorganic film An anodic oxide film is formed on the surface of the wiring which is not covered by.

【0006】この発明によれば、陽極酸化用マスクとし
てフォトレジストのような有機膜ではなく例えば酸化シ
リコンや窒化シリコンのような無機膜を用いているの
で、接続パッドの表面に形成された陽極酸化用マスクと
しての無機膜を容易にかつ完全に除去することができ
る。
According to the present invention, since the inorganic film such as silicon oxide or silicon nitride is used as the mask for anodic oxidation instead of the organic film such as photoresist, the anodic oxidation formed on the surface of the connection pad. The inorganic film as a mask for use can be easily and completely removed.

【0007】[0007]

【発明の実施の形態】図1〜図7はそれぞれこの発明の
第1実施形態を適用した液晶表示装置の各製造工程を示
したものである。そこで、これらの図を順に参照しなが
ら、この実施形態における配線の構造及びその形成方法
について説明する。
1 to 7 show respective manufacturing steps of a liquid crystal display device to which the first embodiment of the present invention is applied. Therefore, the structure of the wiring and the method for forming the wiring in this embodiment will be described with reference to these drawings in order.

【0008】まず、図1(A)、(B)に示すように、
ガラス基板11の上面の所定の個所にAl−Tiからな
るゲート配線つまりゲート電極12を含むゲートライン
13及びこのゲートライン13の所定の一端部に接続さ
れた接続パッド14を形成する。次に、上面全体に陽極
酸化用マスクを形成するための酸化シリコン膜(無機
膜)15をスパッタリングにより成膜する。次に、酸化
シリコン膜15の上面の所定の個所に第1フォトレジス
トマスク16を形成する。次に、ドライエッチングある
いはウェットエッチングを行うと、図2(A)、(B)
に示すように、第1フォトレジストマスク16下に陽極
酸化用マスク17が形成される。すなわち、接続パッド
14の表面のみを被うように陽極酸化用マスク17を形
成する。この後、第1フォトレジストマスク16を除去
する。次に、陽極酸化を行うと、図3(A)、(B)に
示すように、陽極酸化用マスク17によって被われてい
ないゲートライン13の表面及びゲート電極12の表面
にAl−Ti−Oxからなる陽極酸化膜18が形成され
る。
First, as shown in FIGS. 1 (A) and 1 (B),
A gate line made of Al—Ti, that is, a gate line 13 including a gate electrode 12 and a connection pad 14 connected to a predetermined one end of the gate line 13 are formed at a predetermined position on the upper surface of the glass substrate 11. Next, a silicon oxide film (inorganic film) 15 for forming an anodizing mask is formed on the entire upper surface by sputtering. Next, the first photoresist mask 16 is formed at a predetermined position on the upper surface of the silicon oxide film 15. Next, when dry etching or wet etching is performed, as shown in FIGS.
An anodic oxidation mask 17 is formed under the first photoresist mask 16 as shown in FIG. That is, the anodic oxidation mask 17 is formed so as to cover only the surface of the connection pad 14. Then, the first photoresist mask 16 is removed. Next, when anodic oxidation is performed, as shown in FIGS. 3A and 3B, Al-Ti-Ox is formed on the surface of the gate line 13 and the surface of the gate electrode 12 which are not covered by the anodic oxidation mask 17. An anodic oxide film 18 of is formed.

【0009】次に、図4(A)、(B)に示すように、
上面全体に窒化シリコンからなるゲート絶縁膜19を成
膜し、次いでその上面全体にアモルファスシリコンなど
からなる半導体薄膜20を成膜する。次に、ゲート電極
12に対応する部分における半導体薄膜20の上面の所
定の個所に窒化シリコンからなるチャネル保護膜21を
形成する。次に、上面全体にn+シリコン層22を成膜
する。次に、チャネル保護膜21の上面両側におけるn
+シリコン層22の上面の所定の2個所に第2フォトレ
ジストマスク23を形成する。次に、ドライエッチング
あるいはウェットエッチングを行うと、図5(A)、
(B)に示すように、2つの第2フォトレジストマスク
23の各下にソース用n+シリコン層22a及びドレイ
ン用n+シリコン層22bが形成されるとともに、2つ
の第2フォトレジストマスク23下及びチャネル保護膜
21下に半導体薄膜20が残存される。この後、第2フ
ォトレジストマスク23を除去する。
Next, as shown in FIGS. 4 (A) and 4 (B),
A gate insulating film 19 made of silicon nitride is formed on the entire upper surface, and then a semiconductor thin film 20 made of amorphous silicon or the like is formed on the entire upper surface. Next, a channel protection film 21 made of silicon nitride is formed on a predetermined portion of the upper surface of the semiconductor thin film 20 in a portion corresponding to the gate electrode 12. Next, the n + silicon layer 22 is formed on the entire upper surface. Next, n on both sides of the upper surface of the channel protective film 21
+ A second photoresist mask 23 is formed at two predetermined places on the upper surface of the silicon layer 22. Next, when dry etching or wet etching is performed, as shown in FIG.
As shown in (B), an n + silicon layer 22a for a source and an n + silicon layer 22b for a drain are formed under each of the two second photoresist masks 23, and under the two second photoresist masks 23. Also, the semiconductor thin film 20 remains under the channel protective film 21. Then, the second photoresist mask 23 is removed.

【0010】次に、図6(A)、(B)に示すように、
ゲート絶縁膜19の上面の所定の個所にITOからなる
画素電極24を形成する。次に、接続パッド14の中央
部に対応する部分におけるゲート絶縁膜19及び陽極酸
化用マスク17にコンタクトホール25を形成し、接続
パッド14の中央部上面を露出させる。この場合、窒化
シリコンからなるゲート絶縁膜19と酸化シリコンから
なる陽極酸化用マスク17とを同一のドライエッチング
ガスであるいは同一のウェットエッチング液で一括して
容易にエッチングすることができる。したがって、コン
タクトホール25内における接続パッド14の上面に陽
極酸化用マスク17が全く残らないようにエッチングす
ることができる。ところで、この状態では、接続パッド
14の周囲部は陽極酸化用マスク17及びゲート絶縁膜
19によって被われている。そして、露出された接続パ
ッド14の中央部上面は、陽極酸化膜18が形成されて
いないので導電性を有する。
Next, as shown in FIGS. 6 (A) and 6 (B),
A pixel electrode 24 made of ITO is formed at a predetermined position on the upper surface of the gate insulating film 19. Next, a contact hole 25 is formed in the gate insulating film 19 and the anodic oxidation mask 17 in the portion corresponding to the central portion of the connection pad 14 to expose the upper surface of the central portion of the connection pad 14. In this case, the gate insulating film 19 made of silicon nitride and the anodizing mask 17 made of silicon oxide can be easily etched together with the same dry etching gas or the same wet etching solution. Therefore, the upper surface of the connection pad 14 in the contact hole 25 can be etched without leaving the anodic oxidation mask 17 at all. By the way, in this state, the peripheral portion of the connection pad 14 is covered with the anodizing mask 17 and the gate insulating film 19. The exposed upper surface of the central portion of the connection pad 14 has conductivity because the anodic oxide film 18 is not formed.

【0011】次に、図7(A)、(B)に示すように、
ソース用n+シリコン層22aの上面、ドレイン用n+
リコン層22bの上面及びコンタクトホール25内にお
ける接続パッド14の上面にCrからなるソース用コン
タクト層26a、ドレイン用コンタクト層26b及び接
続パッド用コンタクト層27を形成するとともに、ソー
ス用コンタクト層26a、ドレイン用コンタクト層26
b及び接続パッド用コンタクト層27の各上面にAlか
らなるソース電極28a、ドレイン電極28b及び接続
電極29を形成する。この場合、ゲート絶縁膜19の上
面の所定の個所にCr層とAl層とからなるドレインラ
イン30が同時に形成される。また、ソース用コンタク
ト層26a及びソース電極28aは画素電極24に接続
されて形成される。かくして、この実施形態における液
晶表示装置の一部が製造されることになる。
Next, as shown in FIGS. 7A and 7B,
A source contact layer 26a, a drain contact layer 26b, and a connection pad contact made of Cr are formed on the upper surface of the source n + silicon layer 22a, the upper surface of the drain n + silicon layer 22b, and the upper surface of the connection pad 14 in the contact hole 25. The layer 27 is formed, and the source contact layer 26a and the drain contact layer 26 are formed.
A source electrode 28a, a drain electrode 28b, and a connection electrode 29 made of Al are formed on each upper surface of the contact layer 27b and the contact pad contact layer 27. In this case, the drain line 30 including the Cr layer and the Al layer is simultaneously formed at a predetermined position on the upper surface of the gate insulating film 19. The source contact layer 26a and the source electrode 28a are formed so as to be connected to the pixel electrode 24. Thus, a part of the liquid crystal display device in this embodiment is manufactured.

【0012】このように、この実施形態では、コンタク
トホール25内における接続パッド14の上面に酸化シ
リコンからなる陽極酸化用マスク17が全く残らないよ
うにすることができるので、その上に形成された接続パ
ッド用コンタクト層27及び接続電極29と接続パッド
14との導通性を良好とすることができ、したがって薄
膜トランジスタを正常に動作させることができることに
なる。また、ゲート絶縁膜19にコンタクトホール25
を形成するとき、接続パッド14上の不要な陽極酸化用
マスク17を同時に除去することができるので、工程数
が増加しないようにすることができる。
As described above, in this embodiment, since it is possible to completely prevent the anodic oxidation mask 17 made of silicon oxide from remaining on the upper surface of the connection pad 14 in the contact hole 25, the mask 17 is formed thereon. The conductivity between the connection pad contact layer 27 and the connection electrode 29 and the connection pad 14 can be improved, and thus the thin film transistor can be operated normally. In addition, a contact hole 25 is formed in the gate insulating film 19.
Since the unnecessary anodic oxidation mask 17 on the connection pad 14 can be removed at the same time when forming, the number of steps can be prevented from increasing.

【0013】次に、この発明の第2実施形態について、
図8〜図10を順に参照しながら説明する。まず、図8
(A)、(B)に示すように、ガラス基板11の上面の
所定の個所に直線状に配列された複数の接続パッド14
をすべて被うように陽極酸化用マスク17を形成する。
次に、陽極酸化を行うと、図9(A)に示すように、陽
極酸化用マスク17によって被われていないゲートライ
ン13の表面及び図示しないゲート電極の表面に陽極酸
化膜18が形成される。次に、図9(A)、(B)に示
すように、ゲート絶縁膜19を成膜した後、接続パッド
14の中央部に対応する部分におけるゲート絶縁膜19
及び陽極酸化用マスク17にコンタクトホール25を形
成する。この場合も、ゲート絶縁膜19と陽極酸化用マ
スク17とを一括して容易にエッチングすることができ
る。また、コンタクトホール25内における接続パッド
14の上面に陽極酸化用マスク17が全く残らないよう
にエッチングすることができる。次に、図10(A)、
(B)に示すように、コンタクトホール25内における
接続パッド14の上面に接続パッド用コンタクト層27
及び接続電極29を形成する。
Next, regarding the second embodiment of the present invention,
This will be described with reference to FIGS. 8 to 10 in order. First, FIG.
As shown in (A) and (B), a plurality of connection pads 14 linearly arranged at predetermined locations on the upper surface of the glass substrate 11.
A mask 17 for anodic oxidation is formed so as to cover all of the above.
Next, when anodic oxidation is performed, as shown in FIG. 9A, an anodic oxide film 18 is formed on the surface of the gate line 13 not covered by the anodic oxidation mask 17 and the surface of the gate electrode (not shown). . Next, as shown in FIGS. 9A and 9B, after forming the gate insulating film 19, the gate insulating film 19 in a portion corresponding to the central portion of the connection pad 14 is formed.
Then, a contact hole 25 is formed in the anodizing mask 17. Also in this case, the gate insulating film 19 and the anodic oxidation mask 17 can be easily etched together. Further, it is possible to perform etching so that the mask 17 for anodization does not remain on the upper surface of the connection pad 14 in the contact hole 25. Next, FIG.
As shown in (B), the contact pad contact layer 27 is formed on the upper surface of the contact pad 14 in the contact hole 25.
And the connection electrode 29 is formed.

【0014】ところで、この第2実施形態では、図8
(A)、(B)に示すように、直線状に配列された複数
の接続パッド14をすべて被うように陽極酸化用マスク
17を形成しているので、陽極酸化用マスク17の配置
位置精度をある程度ラフとすることができる。したがっ
て、この場合の陽極酸化用マスク17をハードマスクを
用いたスパッタリングにより形成するようにしてもよ
い。また、いずれの実施形態においても、陽極酸化用マ
スク17を凸版印刷やスクリーン印刷などの印刷によっ
て形成するようにしてもよい。なお、印刷の場合には、
全面に印刷した後に、フォトリソグラフィにより陽極酸
化用マスク17を形成するようにしてもよい。さらに、
陽極酸化用マスク17をゲート絶縁膜19と同じ材料
(例えば窒化シリコン)によって形成するようにしても
よい。
By the way, in the second embodiment, as shown in FIG.
As shown in (A) and (B), since the mask 17 for anodization is formed so as to cover all the plurality of connection pads 14 arranged in a straight line, the positional accuracy of the mask 17 for anodization is high. Can be somewhat rough. Therefore, the anodic oxidation mask 17 in this case may be formed by sputtering using a hard mask. Further, in any of the embodiments, the anodizing mask 17 may be formed by printing such as letterpress printing or screen printing. In the case of printing,
After printing on the entire surface, the anodizing mask 17 may be formed by photolithography. further,
The anodic oxidation mask 17 may be made of the same material as the gate insulating film 19 (for example, silicon nitride).

【0015】[0015]

【発明の効果】以上説明したように、この発明によれ
ば、陽極酸化用マスクとしてフォトレジストのような有
機膜ではなく例えば酸化シリコンや窒化シリコンのよう
な無機膜を用いているので、接続パッドの表面に形成さ
れた陽極酸化用マスクとしての無機膜を容易にかつ完全
に除去することができ、したがって接続パッドの表面に
形成されるあるいは接続される接続電極と接続パッドと
の導通性を良好とすることができる。
As described above, according to the present invention, since the inorganic film such as silicon oxide or silicon nitride is used as the mask for anodic oxidation, not the organic film such as photoresist, the connection pad is used. It is possible to easily and completely remove the inorganic film as the anodizing mask formed on the surface of the connection pad, and therefore the conductivity between the connection electrode formed on or connected to the surface of the connection pad and the connection pad is improved. Can be

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の第1実施形態を適用した液晶表示装
置の製造に際し、当初の工程を示すものであって、
(A)は平面図、(B)はそのB−B線に沿う断面図。
FIG. 1 shows an initial step in manufacturing a liquid crystal display device to which a first embodiment of the present invention is applied,
(A) is a plan view and (B) is a sectional view taken along the line BB.

【図2】図1に続く工程を示すものであって、(A)は
平面図、(B)はそのB−B線に沿う断面図。
2A and 2B show a step following FIG. 1, in which FIG. 2A is a plan view and FIG. 2B is a sectional view taken along the line BB.

【図3】図2に続く工程を示すものであって、(A)は
平面図、(B)はそのB−B線に沿う断面図。
3A and 3B show a step following FIG. 2, in which FIG. 3A is a plan view and FIG. 3B is a cross-sectional view taken along the line BB.

【図4】図3に続く工程を示すものであって、(A)は
平面図、(B)はそのB−B線に沿う断面図。
4A and 4B are views showing a step following FIG. 3, in which FIG. 4A is a plan view and FIG. 4B is a sectional view taken along line BB thereof.

【図5】図4に続く工程を示すものであって、(A)は
平面図、(B)はそのB−B線に沿う断面図。
5A and 5B show a step following FIG. 4, in which FIG. 5A is a plan view and FIG. 5B is a cross-sectional view taken along line BB thereof.

【図6】図5に続く工程を示すものであって、(A)は
平面図、(B)はそのB−B線に沿う断面図。
6A and 6B are diagrams showing a step following FIG. 5, in which FIG. 6A is a plan view and FIG. 6B is a cross-sectional view taken along line BB thereof.

【図7】図6に続く工程を示すものであって、(A)は
平面図、(B)はそのB−B線に沿う断面図。
7A and 7B are views showing a step following FIG. 6, in which FIG. 7A is a plan view and FIG. 7B is a sectional view taken along line BB thereof.

【図8】この発明の第2実施形態を適用した液晶表示装
置の製造に際し、当初の工程を示すものであって、
(A)は平面図、(B)はそのB−B線に沿う断面図。
FIG. 8 shows an initial step in manufacturing a liquid crystal display device to which the second embodiment of the present invention is applied,
(A) is a plan view and (B) is a sectional view taken along the line BB.

【図9】図8に続く工程を示すものであって、(A)は
平面図、(B)はそのB−B線に沿う断面図。
9A and 9B are diagrams showing a step following FIG. 8, in which FIG. 9A is a plan view and FIG. 9B is a cross-sectional view taken along line BB thereof.

【図10】図9に続く工程を示すものであって、(A)
は平面図、(B)はそのB−B線に沿う断面図。
FIG. 10 shows a step that follows FIG.
Is a plan view, and (B) is a cross-sectional view along the line BB.

【図11】従来の液晶表示装置の製造に際し、当初の工
程を示すものであって、(A)は平面図、(B)はその
B−B線に沿う断面図。
11A and 11B show an initial step in manufacturing a conventional liquid crystal display device, in which FIG. 11A is a plan view and FIG. 11B is a cross-sectional view taken along the line BB.

【図12】図11に続く工程を示すものであって、
(A)は平面図、(B)はそのB−B線に沿う断面図。
FIG. 12 shows a step that follows FIG.
(A) is a plan view and (B) is a sectional view taken along the line BB.

【図13】図12に続く工程を示すものであって、
(A)は平面図、(B)はそのB−B線に沿う断面図。
FIG. 13 shows a step that follows FIG. 12,
(A) is a plan view and (B) is a sectional view taken along the line BB.

【図14】図13に続く工程を示すものであって、
(A)は平面図、(B)はそのB−B線に沿う断面図。
FIG. 14 shows a step that follows FIG.
(A) is a plan view and (B) is a sectional view taken along the line BB.

【符号の説明】[Explanation of symbols]

12 ゲート電極 13 ゲートライン 14 接続パッド 17 陽極酸化用マスク(無機膜) 18 陽極酸化膜 12 gate electrode 13 gate line 14 connection pad 17 anodizing mask (inorganic film) 18 anodizing film

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 接続パッドを有する配線の表面のうち前
記接続パッドの周囲部が無機膜によって被われ、少なく
とも前記接続パッドの中央部を除く前記配線の表面に陽
極酸化膜が形成されていることを特徴とする配線の構
造。
1. A surface of a wiring having a connection pad, a peripheral portion of the connection pad being covered with an inorganic film, and an anodic oxide film being formed on a surface of the wiring except at least a central portion of the connection pad. Wiring structure characterized by.
【請求項2】 薄膜トランジスタの一部を形成するため
のゲート電極を含むゲートライン及び該ゲートラインに
接続された接続パッドからなるゲート配線の表面のうち
前記接続パッドの周囲部が無機膜によって被われ、少な
くとも前記接続パッドの中央部を除く前記ゲート配線の
表面に陽極酸化膜が形成されていることを特徴とする配
線の構造。
2. A peripheral portion of the connection pad is covered with an inorganic film on a surface of a gate wiring including a gate line including a gate electrode for forming a part of a thin film transistor and a connection pad connected to the gate line. A wiring structure in which an anodic oxide film is formed on the surface of the gate wiring except at least the central portion of the connection pad.
【請求項3】 請求項1または2記載の発明において、
前記無機膜は酸化シリコンまたは窒化シリコンからなる
ことを特徴とする配線の構造。
3. The method according to claim 1, wherein
The wiring structure, wherein the inorganic film is made of silicon oxide or silicon nitride.
【請求項4】 接続パッドを有する配線の表面のうち少
なくとも前記接続パッドの一部を無機膜によって被い、
この状態で陽極酸化を行うことにより、前記無機膜によ
って被われていない前記配線の表面に陽極酸化膜を形成
することを特徴とする配線の形成方法。
4. An inorganic film covers at least a part of the connection pad on the surface of the wiring having the connection pad,
A method of forming a wiring, characterized by forming an anodized film on the surface of the wiring not covered with the inorganic film by performing anodization in this state.
【請求項5】 薄膜トランジスタの一部を形成するため
のゲート電極を含むゲートライン及び該ゲートラインに
接続された接続パッドからなるゲート配線の表面のうち
少なくとも前記接続パッドの一部を無機膜によって被
い、この状態で陽極酸化を行うことにより、前記無機膜
によって被われていない前記ゲート配線の表面に陽極酸
化膜を形成することを特徴とする配線の形成方法。
5. A surface of a gate wiring comprising a gate line including a gate electrode for forming a part of a thin film transistor and a connection pad connected to the gate line, at least a part of the connection pad being covered with an inorganic film. The method for forming a wiring is characterized by forming an anodized film on the surface of the gate wiring not covered with the inorganic film by performing anodization in this state.
【請求項6】 請求項4または5記載の発明において、
前記無機膜は酸化シリコンまたは窒化シリコンからなる
ことを特徴とする配線の形成方法。
6. The invention according to claim 4, wherein
The method for forming a wiring, wherein the inorganic film is made of silicon oxide or silicon nitride.
JP12926496A 1996-04-26 1996-04-26 Wiring structure and method of forming the same Expired - Fee Related JP3543130B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12926496A JP3543130B2 (en) 1996-04-26 1996-04-26 Wiring structure and method of forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12926496A JP3543130B2 (en) 1996-04-26 1996-04-26 Wiring structure and method of forming the same

Publications (2)

Publication Number Publication Date
JPH09293877A true JPH09293877A (en) 1997-11-11
JP3543130B2 JP3543130B2 (en) 2004-07-14

Family

ID=15005282

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3543130B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0930525A2 (en) * 1998-01-20 1999-07-21 Nec Corporation Liquid crystal display panel and method for manufacturing the same
KR100490043B1 (en) * 1998-01-21 2005-08-31 삼성전자주식회사 Planar drive type liquid crystal display device and its manufacturing method
KR100709710B1 (en) * 2000-08-14 2007-04-19 삼성전자주식회사 manufacturing method of thin film transistor array panel for liquid crystal display
WO2019041654A1 (en) * 2017-08-28 2019-03-07 武汉华星光电技术有限公司 Liquid crystal display panel with ultra-narrow lower bezel and manufacturing method therefor

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0930525A2 (en) * 1998-01-20 1999-07-21 Nec Corporation Liquid crystal display panel and method for manufacturing the same
US6259495B1 (en) 1998-01-20 2001-07-10 Nec Corporation Liquid crystal display panel and method of manufacturing the same, including a structure for, and a method of preparing, terminal or connecting electrodes for connecting liquid crystal display panel to an external drive circuit
US6356336B2 (en) 1998-01-20 2002-03-12 Nec Corporation Liquid crystal display panel and method for manufacturing the same
US6362867B2 (en) 1998-01-20 2002-03-26 Nec Corporation Method of manufacturing a liquid crystal display panel including preparing terminal or connecting electrodes for connecting liquid crystal display panel to an external drive circuit
US6452648B2 (en) 1998-01-20 2002-09-17 Nec Corporation Liquid crystal display panel and method for manufacturing the same
EP0930525A3 (en) * 1998-01-20 2002-10-16 Nec Corporation Liquid crystal display panel and method for manufacturing the same
US6515730B1 (en) 1998-01-20 2003-02-04 Nec Corporation Method of manufacturing a liquid crystal display panel including a terminal electrode part thereof
KR100490043B1 (en) * 1998-01-21 2005-08-31 삼성전자주식회사 Planar drive type liquid crystal display device and its manufacturing method
KR100709710B1 (en) * 2000-08-14 2007-04-19 삼성전자주식회사 manufacturing method of thin film transistor array panel for liquid crystal display
WO2019041654A1 (en) * 2017-08-28 2019-03-07 武汉华星光电技术有限公司 Liquid crystal display panel with ultra-narrow lower bezel and manufacturing method therefor

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