KR100487634B1 - Block Control Circuit of Semiconductor Memory Device - Google Patents

Abstract

In the semiconductor memory device, when testing the disturbance of a DRAM, the test time can be reduced by simultaneously activating one word line of a plurality of subblocks regardless of a subblock selection address signal. A block control circuit having a row activation function is provided.

The present invention provides a block control circuit of a semiconductor memory device for inputting a plurality of address signals to generate a subblock selection signal for controlling a plurality of subblocks of a memory cell array. A logic unit for generating a plurality of pairs of output signals; Inputs a plurality of pairs of output signals of the logic unit, and selects a subblock selection signal for activating only a subblock corresponding to an activated output signal pair among the plurality of output signal pairs among the plurality of subblocks of the memory cell array; Blocking the output signal of the logic unit from being applied to the block selection signal generation unit according to the generated block selection signal generation unit and the multilow activation signal applied from the outside, and driving the multilow line with the block selection signal generation unit And a multi-row activation unit for generating a pair of multi-row line driving signals.

Description

Block Control Circuit of Semiconductor Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to multi-row, which can reduce a test time by activating one word line at a time in a plurality of sub-blocks at the time of a discontinuity test. A block control circuit having an activation function is provided.

1 shows a cell array configuration of a conventional DRAM. FIG. 1 illustrates a block control circuit 20 for selecting a memory cell array unit 10 and a block of the memory cell array unit 10 of a conventional DRAM. The memory cell array unit 10 is composed of an 8M cell array. The memory cell array unit 10 is composed of 32 256 cell arrays consisting of 256 row addresses and 1024 column addresses, constituting an 8M cell array.

In this case, a 256K cell array having 256 row addresses and 1024 column addresses is called a sub block, and the DRAM of FIG. 1 includes 32 sub blocks SBLK0 to SBLK31.

Accordingly, it can be said that the DRAM of the 8M cell array of FIG. 1 is composed of 8192 (256x32) row address lines and 1024 column address lines. 13 address lines are required to create 8192 row addresses, and 8 address lines of Ax0-Ax7 of 13 address lines (Ax0-Axc) are connected to one of 256 row address lines in each subblock (SBLK0-SBLK31). It is an address for selecting, and five address lines of Ax8, Ax9, Axa, Axb, and Axc are addresses applied to the block control circuit 20 to select one of the 32 subblocks SBLK0 to SBLK31.

2 shows a detailed view of the block control circuit 20 in the conventional DRAM. Referring to FIG. 2, the conventional block control circuit includes a logic unit 21 which inputs two neighboring address input signals Ax8Ax9i and AxaAxbAxci and Ax8Ax9j and AxaAxbAxcj, and outputs the logic unit 21, respectively. And a block selection signal generator 22 for inputting and generating subblock selection signals SBLK0 to SBLK31, respectively.

The logic unit 21 includes a plurality of logic means (LOG0-NA31b) consisting of NAND gates NA0a-NA0b-(NA31a-NA31b) which input two neighboring address input signals Ax8Ax9i and AxaAxbAxci and (Ax8Ax9j and AxaAxbAxcj) as inputs. LOG31, and the block selection signal generator 22 inputs the output signals of the logic means LOG0 to LOG31 of the logic unit 21 to select subblocks of the memory cell array 10, respectively. It consists of a plurality of block selection signal generating means BCSG0-BCSG31 for generating block selection signals SBLK0-SBLK31, respectively.

The logic unit 21 activates only NAND gates corresponding to the NAND gates NA0a-NA0b-NA31a-NA31b by a combination of two neighboring address input signals Ax8Ax9i and AxaAxbAxci and Ax8Ax9i and AxaAxbAxci. Accordingly, the block select signal generator 22 activates only the block select signal generator BCSG which inputs the output signal of the activated NAND gate among the block select signal generators BCSG0 through BCSG31.

Here, two neighboring address input signals Ax8Ax9i and AxaAxbAxci and Ax8Ax9j and AxaAxbAxcj are address input signals for selecting two neighboring subblocks. 00001 becomes

Logical combinations of the two input signals Ax8Ax9i and AxaAxbAxci of the logic unit 21 are shown in Tables 1 and 2, respectively.

Table 1

Table 2

Therefore, in the conventional block control circuit, referring to Tables 1 and 2 above, the NAND gates NA0a to NA31a are formed by a logical combination of two address input signals Ax8Ax9i and AxaAxbAxci and Ax8Ax9j and AxaAxbAxcj. The logic states of the output nodes A0a-A31a and A0b-A31b of (NA0b-NA31b) are determined.

That is, when 00000 is input to two neighboring address input signals Ax8Ax9AxaAxbAxc, only the first logical means LOG0 of the plurality of logic means LOG0 to LOG31 of the logic unit 21 is activated. That is, only the NAND gate NA0a of the first logic means LOG0 generates the output signal A0a in the low state.

Accordingly, the first block selection signal generation means BCSG1 which inputs the output signal of the low state of the NAND gate NA0a among the plurality of block selection signal generation means BCSG0 to BCSG31 of the block selection signal generation unit 22. Only is activated to generate the sub-block selection signal SBLK0 for selecting the first sub-block among the plurality of sub-blocks.

In the conventional DRAM as described above, only one of the 32 subblocks SBLK0-SBLK31 is selected and activated by a 5-bit combination of Ax8-Axc during one cycle of memory access cycle. For example, when the addresses Ax8-Axc are 00000, only the first subblock SBLK0 is selected and activated among the 32 blocks SBLK0-SBLK31, and the addresses Ax8-Axc are 00001, 00010,... , 11101, 11110, and 11111, subblocks SBLK1, SBLK2,... Of 32 subblocks, respectively. , SBLK29, SBLK30, SBLK31 are selected and activated.

When only one of the subblocks SBLK0-SBLK31 of the memory cell array 10 is selected and activated through the control block circuit 20 by the five addresses Ax8-Axc, 256 row address lines of one activated subblock are activated. Only one row address line is activated by the combination of A0-A7.

Therefore, 8192 memory access cycles are required to access all 8192 row address lines. Therefore, if one row address line is discontinued by 64mS in the distance test, a test time of 8192x64mS = 524.3 sec is required in order to access the entire 8192 row address lines, thereby resulting in a long test time.

The present invention is to solve the problems of the prior art as described above, the multi-row activation function that can reduce the test time by activating one word line of each of a plurality of sub-blocks at the same time during the disaster test of the DRAM It is to provide a block control circuit of a semiconductor memory device having a.

In order to achieve the above object of the present invention, the present invention provides a block control circuit of a semiconductor memory device for inputting a plurality of address signals to generate a subblock selection signal for controlling a plurality of subblocks of a memory cell array. A logic unit configured to input a plurality of neighboring two address input signals to generate a plurality of pairs of output signals; Receives a multi-row activation signal applied from the outside, and outputs the output signal of the logic unit as it is when the multi-row activation signal is disabled, and outputs the logic unit when the multi-row activation signal is enabled A multi-row activator for blocking signals and generating a pair of multi-row line driving signals for driving the multi-row lines; And receiving an output signal of the multi-row activation unit, and when the multi-row activation signal is in a disabled state, activates one of the subblocks of the memory cell array by an output signal of the logic unit passing through the multi-row activation unit. And a block select signal generator for activating the entire cell array subblock when the multi-row enable signal is enabled.

In the present invention, the multi-row activation unit transmits a plurality of pairs of output signals of the logic unit by the multi-row activation signal to the block selection signal generator or the pair of driving signals for driving a mullow line. It consists of a plurality of multi-row activation means generated by the block selection signal generator.

In the present invention, each of the multi-row activation means is a transmission means for transferring a corresponding pair of output signals of the plurality of pairs of output signals output from the logic unit by the multi-row activation signal to the block selection signal generator and; And a generating means for generating a pair of drive signals for driving the multi-row lines by the multi-row activation signal to the block selection signal generator.

According to an embodiment of the present invention, the logic unit may include a plurality of logic means for generating a plurality of pairs of output signals by inputting two neighboring address input signals.

According to an embodiment of the present invention, each logic means of the logic unit comprises: a first NAND gate for inputting a first input signal of two adjacent address input signals to generate a first output signal of each pair of output signals; And a second NAND gate configured to input a second input signal among two neighboring address input signals to generate a second output signal of each pair of output signals.

According to an exemplary embodiment of the present invention, the multi-row activation unit transmits a plurality of pairs of output signals of the logic unit by the multi-row activation signal to the block selection signal generator or a pair of pairs for driving a mullow line. Characterized in that it comprises a plurality of multi-row activation means for generating a drive signal to the block selection signal generator, respectively.

According to an embodiment of the present invention, each of the multi-row activation means transfers a corresponding pair of output signals from the plurality of pairs of output signals output from the logic unit by the multi-row activation signal to the block selection signal generator. Delivery means for; And a generating means for generating a pair of driving signals for driving the multi-row lines by the multi-row activation signal to the block selection signal generator.

According to an embodiment of the present invention, each transmission means of the multi-row activation means respectively sends a corresponding pair of output signals from among a plurality of pairs of output signals of the logic part by the multi-row activation signal to the block selection signal generator. It is characterized by consisting of a pair of transfer gate for transmitting.

According to an embodiment of the present invention, each of the generating means of the multi-row activation means is applied to the multi-row activation signal to the gate, the drain is connected to the block selection signal generator, the source is grounded, a pair of multi-row It is characterized by consisting of a pair of NMOS transistor which generate | occur | produces a line drive signal.

According to an exemplary embodiment of the present invention, the block selection signal generation unit inputs a plurality of pairs of output signals of the logic unit or a plurality of pairs of multirow line driving signals applied from the multirow line activator to the memory cell. And a plurality of block selection signal generating means for generating a subblock selection signal for selecting a subblock of the array.

According to an embodiment of the present invention, when the output signal of the logic unit is applied through the multi-row activation unit by the multi-row activation signal, the block selection signal generation unit may be configured by the logic unit among a plurality of block selection signal generation means. And a sub-block selection signal for selecting only one subblock of the plurality of subblocks through the block selection signal generating means to which the activated output signal is applied among the output pairs of output signals.

On the other hand, when the block selection signal generation unit is blocked from transmitting the output signal of the logic unit through the multi-row activation unit by the multi-row activation signal, a pair of multi for driving the multi-row line from the multi-row activation means The low line driving signal is applied to the sub-block selection signal to be generated simultaneously from the block selection signal generating means.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a block control circuit of a semiconductor memory device according to an embodiment of the present invention. A block control circuit of a semiconductor memory device according to an embodiment of the present invention includes a logic unit 21 which inputs two neighboring address input signals Ax8Ax9i and AxaAxbAxci and Ax8Ax9j and AxaAxbAxcj, and the logic unit 21 of the logic controller 21. A block select signal generator 23 for inputting the output signals A0a, A0b-(A31a, A31b) to generate subblock selection signals SBLK0-SBLK31 for activating the subblock, and a tester (not shown in the drawing) When the multi-row activation signal SMRA is applied, the output signals A0a and A0b to A031a and A31b of the logic unit 21 are blocked from being transmitted to the block selection signal generator 23. The block select signal generator 23 includes a multi-row activation unit 23 for generating a pair of drive signals for driving the multi-row lines.

The logic unit 21 inputs two neighboring address input signals Ax8Ax9i and AxaAxbAxci and Ax8Ax9j and AxaAxbAxcj, respectively, and includes a plurality of logic means (LOG0) consisting of NAND gates NA0a-NA0b-NA31a-NA31b. -LOG31).

The multi-row activation unit 23 outputs the output signals A0a, A0b-A31Aa, A31b of the plurality of logic means LOG0-LOG31 of the logic unit 21 by the multi-row activation signal SMRA. A plurality of multi-row activation means (MRA0 to MRA31) are provided to the block select signal generator 22 or to generate a drive signal for driving the mullow line to the block select signal generator 22.

Each of the multi-row activation means MRA0 to MRA31 transmits the output signals of the plurality of logic means LOG0 to LOG31 of the logic unit 21 to the block selection signal generator 22 by a multi-row activation signal SMRA. And means for generating the drive selection signal for driving the multi-row line by the multi-row activation signal SMRA to the block selection signal generator 22.

Each transmission means of the multi-row activation means MRA0 to MRA31 is output signals A0a and A0b of the plurality of logic means LOG0 to LOG31 of the logic unit 21 by the multi-row activation signal SMRA. And a pair of transfer gates TG0a and TG0b-TG31a and TG31b for transferring the A31a and A31b to the block selection signal generator 22.

Each of the transfer gates TG0a and TG0b to TG31a and TG31b includes a PMOS transistor and an NMOS transistor to which the multirow enable signal SMRA and the multirow enable signal inverted through the respective inverters I0 to I31 are applied to the gate, respectively. (P0a, N0a)-(P31a, N31a).

The generating means of the multi-row activating means MRA0 to MRA31 is a multilow activating signal SMRA applied to a gate, connected to an input terminal of each block selection signal generating means BCSG0 to BCSG31 at a drain, and the source is grounded. It consists of a pair of NMOS transistors N0a, N0b-(N31a, N31b).

The block selection signal generator 22 is composed of a plurality of block selection signal generating means BCSG0-BCSG31, and the logic unit is provided through the multirow activation means MRA0-MRA31 by the multirow activation signal SMRA. When the output signals A0a, A0b-A31a, A31b of (21) are applied, a plurality of subs from the block selection signal generation means to which the output signal of the activated logic means is applied during the output of the logic unit 21. A subblock selection signal for selecting one of the blocks is generated.

However, the block select signal generator 22 outputs the output signals A0a and A0b-() of the logic unit 21 through the multirow activation means MRA0 to MRA31 by the multirow activation signal SMRA. When transmission of A31a and A31b is interrupted, a pair of drive signals for driving the multirow line from the multirow activation means MRA0 to MRA31 are applied to the block selection signal generation means BCSG0 to BCSG31. At the same time, the sub-block selection signals SBLK0 to SBLK31 are simultaneously generated.

The operation of the block control circuit of the semiconductor memory device of the present invention having the configuration as described above is as follows.

In the normal operation, a low state signal is applied to the multi-row activation signal SMRA, and in the multi-row activation unit 23, all of the transfer gates TG0-TG31 of each of the multi-row activation means MRA0-MRA31 are turned on. NMOS transistors N0a, N0b-(N31a, N31b) are turned off.

Therefore, the multi-row activation operation is not performed, and the block control circuit of the present invention performs the normal subblock selection operation.

That is, the logic unit 21 activates only one logical means among a plurality of logic means LOG0 to LOG31 for inputting two neighboring address input signals A8A9AxaAxbAxci and A8A9AxaAxbAxcj.

For example, when 00010 and 00011 are respectively input to two neighboring address input signals A8A9AxaAxbAxci and A8A9AxaAxbAxcj, the second logical means LOG1 of the plurality of logic means LOG0 to LOG31 of the logic unit 21 is input. Only NAND gate NA1a is activated.

Therefore, only the outputs A1a and A1b of the second logic means LOG1 of the logic unit 21 go low and high, respectively, and all the outputs of the remaining logic means go high.

Each output of each logic means LOG0-LOG31 of the logic section 21 is applied to the multirow activation section 23, and each transfer gate TG0a, TG0b of the multirow activation means MRA0-MRA31-( The block selection signal generator 22 is applied to the block selection signal generator 22 through TG31a and TG31b.

The block select signal generator 22 inputs the output signals A0a, A0b-(A31a, A31b) of the logic unit 21 applied through the multi-row enabler 23, and a plurality of block select signal generators. Of the BCSG0 BCSG31, only the first block selection signal generating means BCSG1 which inputs the output signal of the activated logic means LOG1 is activated. Accordingly, only the sub block selection signal SBLK1 is activated to select the first sub block.

The second sub-block selection signal SBLK1 generated from the block selection signal generator 22 selects a second sub-block among a plurality of memory cell arrays, controls a sense amplifier of the selected first sub-block, and controls the bit line. Precharges the role.

On the other hand, when the high-low multi-row activation signal SMRA is applied from the tester to test the disturbance, the multi-row activation section 23 transfers the gates of the multi-row activation means MRA0 to MRA31. TG0a, TG0b)-(TG31a, TG31b) are turned off by the high-low multi-low activation signal SMRA.

As the transfer gates TG0a and TG0b to TG31a and TG31b are turned off, transmission of an output signal generated from the logic unit 21 to the block selection signal generator 22 is blocked.

At this time, the high-low multi-row activation signal SMRA is applied to the gates of the NMOS transistors N0a and N0b of the multi-row activation means MRA0 to MRA31 so that the multi-row activation means MRA0 to MRA31 are turned on. Output a pair of multirow drive signals in a low state, respectively.

Accordingly, the block select signal generator 22 applies the low row multi-row drive signals to the respective block select signal generators BCSG0 to BCSG31, regardless of the address input signal to be applied. (BCSG0-NCSG31) generate all of the activated subblock selection signals SBLK0-SBLK31 at the same time.

Thus, in the block control circuit of the present invention, when the multi-row activation signal SMRA is applied from the tester, the sub-block selection signal SBLK0-at the same time from the block selection signal generation means BCSG0-BCSG31 of the block selection signal generator 22. SBLK31 is activated, so that the subblocks of the memory cell array are simultaneously selected.

Therefore, when one row line among the plurality of row lines of the subblocks is selected by the remaining A0-A7 address signals, the row lines of each subblock are selected and activated.

Therefore, when controlling a subblock as shown in FIG. 3, one rowline of one subblock is activated during one memory access cycle, whereas in the present invention, one of 32 subblocks is used during one memory access cycle. Since it is possible to simultaneously activate the low lines, that is, 32 low lines, it is possible to reduce the disturbance test time by 1/32 compared with the conventional method.

The multi-row enable signal (SMRA) creates a separate pad for supplying this signal, and the tester controls the signal directly. In this case, the multi-row enable signal (SMRA) is controlled like a memory control clock such as / CAS or / RAS. Since real-time control is possible, it is possible to use a multirow enable circuit freely in a test pattern.

When packaged, by bonding the pad for multi-low activation signal (SMRA) to ground, turn off the NMOS transistor of the mul-low activation section 23 when the user uses this product so as not to be affected by the multi-row activation operation. do.

According to the present invention as described above, during the disturbance test operation, the test time can be reduced by simultaneously activating each row line of each of the plurality of subblocks of the memory cell array to perform the test operation.

Accordingly, it is possible to save the test cost by simultaneously driving the multi-row line to reduce the test time.

1 is a view showing a memory cell array of a conventional DRAM (DRAM),

2 is a block diagram of a block control circuit of a conventional semiconductor memory device;

3 is a detailed circuit diagram of a block control circuit of the semiconductor memory device of FIG.

4 is a block diagram of a block selection circuit of a semiconductor memory device according to an embodiment of the present invention;

5 is a detailed circuit diagram of the block control circuit of FIG. 4;

(Explanation of symbols for the main parts of the drawing)

10: memory cell array 20: block control circuit

21: logic section 22: sub-block selection signal generator

23: multi-row activator LOG1-LOG31: logic means

NA0a-NA31a, NA0b, NA31b: NAND Gate

MRA0-MRA31: Multilow activation means

TG0a-TG31a, TG0b-TG031b: Transfer Gate

N0a-N31a, N0b-N31b: NMOS transistor

BCSG 0-BCSG 31: block selection signal generating means

I0 -I31: Inverter

Claims (3)

In a block control circuit of a semiconductor memory device for generating sub-block selection signals SBLK0 to SBLK31 for controlling a plurality of subblocks of a memory cell array, A logic unit 21 for receiving address signals ax98 to axABC for selecting one of the plurality of subblocks; Receives a multi-row activation signal (SMRA) applied from the outside, and outputs the output signal of the logic unit as it is when the multi-row activation signal is disabled, and when the multi-row activation signal is enabled A multi-row activator 23 for generating a driving signal for selecting all of the sub-blocks after blocking the output signal of the logic part; And a block selection signal generator 22 generating a sub block selection signal SBLK0-SBLK31 for selecting the sub block in response to an output signal of the multi-row activation unit. When the multi-row enable signal SMRA is in a disabled state, one of the sub-blocks of the memory cell array is activated by an output signal of the logic unit passing through the multi-row enable unit, and the multi-row enable signal is And a block control circuit of the semiconductor memory device, wherein the entire subblock of the cell array is activated in the enabled state. The method of claim 1, The multi-row enable signal SMRA is in a disabled state when the memory device is in normal operation, and the multi-row enable signal SMRA is in an enable state when the memory device is in a test mode. Block control circuit of memory element. The method of claim 1, When the multi-row enable signal SMRA is in a disabled state, only one of the sub-block selection signals SBLK0-SBLK31 is enabled by the address signal, and only a corresponding subblock is enabled. When the multi-row enable signal SMRA is in an enabled state, all of the sub-block selection signals SBLK0 to SBLK31 are enabled regardless of the address signal, so that the entire plurality of subblocks are enabled. Block control circuit of semiconductor memory device.

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