JPH0711917B2 - Dynamic RAM - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a dynamic RAM (random access memory), for example, to a technique effective when used in an internal automatic refresh circuit. Is.

[Conventional technology]

The dynamic memory cell is composed of a storage capacitor for storing information in the form of electric charges and a MOSFET for address selection. In a memory cell formed on a semiconductor substrate, the electric charge accumulated in the capacitor decreases with time due to leak current or the like. Therefore, in order to always store accurate information in the memory cell, the information stored in the memory cell must be
Before the information is lost, it is necessary to read it, amplify it, and write it again in the same memory cell, that is, a so-called refresh operation. For example, as an automatic refresh method for memory cells in a 64K-bit dynamic RAM, an automatic refresh circuit shown in pp30 to 33 of Vol23, No3 of "Electronic Technology" is known. That is, a dynamic RAM is provided with an external terminal for refresh control, and a plurality of memory cells in the dynamic RAM are automatically refreshed by applying a refresh control signal ▲ ▼ of a predetermined level to this external terminal. The automatic refresh function is provided, and the built-in timer circuit is activated by keeping the refresh signal ▲ ▼ at a predetermined level to perform the refresh operation at regular intervals.

[Problems to be solved by the invention]

In the automatic refresh circuit as described above, all memory cells are refreshed in the same cycle.
An extremely short refresh cycle of about 4 to 4 ms is selected. In dynamic RAM, refresh operation is always performed at such an extremely short time interval.
Most of this power consumption is due to the refresh operation.

The present inventor examined the information storage retention time of the memory cells, and as a result, the information storage retention time in most of the memory cells was large at about 400 to 1000 ms, and only a plurality of limited memory cells fell out due to a process defect or the like. I found that it was worse for several ms. Therefore,
The inventor of the present application considered changing the refresh cycle so as to match the information storage retention time of the memory cell.

An object of the present invention is to provide a dynamic RAM with low power consumption.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, of the plurality of memory arrays, only the sense amplifier of the memory array in which the selected memory cell exists is set to the operating state, and the address of the word line in which the defective defective memory cell exists is stored in the address storage circuit. The row address signal is compared with the stored address signal, and the coincidence detection output is used to instruct the plurality of memory arrays to operate the word line and the sense amplifier.

[Work]

According to the above-mentioned means, the cycle can be substantially shortened by performing the refreshing on the defective memory cells that are defective in every refreshing operation on the common address in the plurality of memory arrays.

〔Example〕

FIG. 1 shows a dynamic RAM to which the present invention is applied.
A block diagram of one embodiment of is shown. Each main circuit block in the figure is drawn in accordance with the actual geometrical arrangement on the semiconductor chip, and is not particularly limited by a known CMOS (complementary MOS) integrated circuit technology, but one Is formed on a semiconductor substrate made of single crystal silicon.

As will be apparent from the description below, the various circuits constituting the RAM are row-system and column-system timing generation circuits R-.
Each operation is controlled by various timing signals respectively generated from TG and C-TG. However,
In FIG. 1, signal lines to be provided between the row and column timing generation circuits R-TG and C-TG and various circuits in order to prevent the drawing from becoming complicated are omitted.

The dynamic RAM of this embodiment has four memory arrays M0 to M3, although not particularly limited thereto. Each of the memory arrays M0 to M3 is configured by a folded bit line (data line) system. Therefore, each of the memory arrays M0 to M3 has a plurality of data lines to be paired, that is, a plurality of complementary data lines and a plurality of data input / output terminals coupled to the corresponding data lines. It has a dynamic memory cell and a plurality of word lines to which the selection terminals of the dynamic memory cell are connected. Although not shown in FIG. 1, the data line extends in the lateral direction of FIG. The word lines are extended in the vertical direction in the figure.

The memory arrays M0 to M3 have the same storage capacity by arranging the same number of memory cells in a matrix. The complementary data lines of each memory array M0 to M3 are coupled to the input / output nodes of the sense amplifiers SA0 to SA3, respectively.

The sense amplifiers SA0 to SA3 are provided with a sense amplifier activation timing signal formed based on the row address strobe signal ▲ ▼ and row-related address signals ai−1, ai.
The timing signals φpa0 to φpa3 output from the row timing generation circuit R-TG according to the decoded signal of
The memory array M0 or
Only those compatible with M3 are activated. The first
It should be understood that the sense amplifiers SA1 to SA3 as the circuit blocks in the figure each include a precharge circuit, a dummy cell, an active restore circuit, and the like.

The illustrated RAM has an address selection circuit for selecting a desired memory cell among a plurality of memory cells and a desired dummy cell among a plurality of dummy cells in each memory array. The address selection circuit is a row address buffer R-
It is composed of ADB, column address buffer C-ADB, row address decoders R-DCR0 to R-DCR3, column address decoders C-DCR1 to 2, and column switch circuits CW0 to CW3.

The operation of each circuit constituting the address selection circuit is controlled by the timing signals generated from the respective timing generation circuits R-TG and C-TG of the row and column systems.

External row address signals AX0 to AXi and column address signals AY0 to AYi are time-divided to the external terminals of the RAM, to which the input terminals of the row address buffer R-ADB and the column address buffer C-ADB are coupled, according to the address multiplexing method. Is supplied to.

The row address buffer R-ADB responds to the timing signal for address signal fetch control generated from the row timing generation circuit R-TG in synchronization with the generation of the row address strobe signal ▲ ▼, in response to the external row signal. Take in address signals AX0 to AXi. As a result,
Row-system internal complementary address signals ax0 to axi to be supplied to the row address decoders R-DCR0 to R-DCR3 are output from the address buffer R-ADB via the output drive circuit R-DRV. The column address buffer C-ADB fetches an external column address signal in response to a similar timing signal generated from the column timing generation circuit C-TG in synchronization with the generation of the column address strobe signal ▲ ▼. The column-system internal complementary address signals ay0-ayi to be supplied to the column address decoder C-DCR1 are output via the output drive circuit C-DRV.

The row address decoders R-DCR0 to R-DCR3 are the first
It is arranged below the memory arrays M0 to M3 in the figure,
Each output terminal is coupled to a corresponding memory array word line and to a dummy word line. The operation of each of the row address decoders R-DCR0 to R-DCR3 is controlled by the word line selection timing signal φx generated from the row timing generation circuit R-TG.
The word line selection signal and the dummy word line selection signal are output in synchronization with the timing signal φx.

Therefore, the word line of each memory array M0 to M3 is selected by supplying the word line selection signal formed by the row address decoders R-DCR0 to R-DCR3, respectively. In this case, each row address decoder R
-DCR0 to R-DCR3 are row address signals of all bits
Takes ax0 or axi and decrypts it. This allows
Of the memory arrays M0 to M4, the selection operation of the word line and the dummy word line is performed by one row address decoder only for one memory array in which the memory cell to be selected exists, and the remaining three memory arrays are , The word line is left unselected (precharged state).

The operation of the column address decoder C-DCR1 is controlled by the data line selection timing signal or column selection timing signal φy output from the column timing generation circuit C-TG, and the data line selection signal or Output the column selection signal. The column address decoder C-DCR1 is not particularly limited.
Are located to the right of the memory array as shown. An output line (not shown) of the column address decoder C-DCR1, that is, a data line selection line is extended on the memory array and coupled to the column switch circuits CW0 to CW3. Although the column address decoder C-DCR1 is not directly related to the present invention per se and its details are not shown in the figure, the column address decoder C-DCR1 is composed of a plurality of unit circuits each of which supplies an output to each data line selection line.

The column switch circuits CW0 to CW3 are respectively provided between the common data lines provided corresponding to the memory arrays M0 to M3 and the complementary data, and the data line selection signals formed by the column address decoder C-DCR1 are provided. Commonly supplied.

In order to select one pair (1 bit) of signals from the above four pairs of common data lines, four pairs of common data lines corresponding to the memory arrays M0 to M3, the output terminal of the data input buffer DIB and the data output. Second column switch circuits CW2L and CW2R are provided between the input terminals of the buffer DOB. These second column switch circuits CW2L and CW2R
The respective operations are controlled by the selection signal formed by the second column address decoder circuit DCR2.

The operation of the data input buffer DIB is controlled by the write timing signal φw generated from the timing generation circuit C-TG, forms a write signal corresponding to the write signal supplied from the external terminal Din, and outputs it. It is supplied to the second column switch circuit CW2L or CW2R. The data input buffer DIB exhibits high output impedance characteristics when it is placed in the inactive state.

The data output buffer DOB, whose operation is similarly controlled by the read timing signal φr generated from the timing generation circuit C-TG, receives the read signal output through the second column switch circuit CW2L or CW2R, and Is amplified and sent to the external terminal Dout.

The timing generation circuit C-TG for controlling the read / write operation of information receives the column address strobe signal ▲ ▼ and the write enable signal ▲ ▼ supplied from the external terminal to identify the write / read mode, and A corresponding column system and the above various timing signals are formed.

The row-related timing generation circuit R-TG includes a row address strobe signal ▲ ▼ supplied from an external terminal and a 2-bit address signal for instructing the memory arrays M0 to M3.
By receiving ai-1, ai and the internal CAS signal, various row-related timing signals are formed. According to this embodiment, the word line and the dummy word line are selected only for the memory cells to be selected among the four memory arrays M0 to M3 as described above.
Therefore, timing signals φpa0 to φpa3 that selectively activate the sense amplifiers SA0 to SA3 are required. The address signals ai-1 and ai are used to generate the timing signals φpa0 to φpa3. Further, the internal CAS signal is used to identify the refresh mode. That is, the row address strobe signal ▲ ▼
When the level changes from high level to low level, CA
If the S signal level is high, it is judged and a refresh signal REF is output (CAS before RAS refresh).

The refresh control circuit REFC includes a refresh address counter circuit. Refresh control circuit REFC
Is activated when the resh signal REF is supplied, and supplies refresh address signals ax0 'to axi' to the row address buffer R-ADB. Row address buffer R
The ADB has a multiplexer function as an input, and in the refresh mode, its input is switched from the external address terminals (AX0 to AXi) to the refresh address terminals (ax0 'to axi').

In this embodiment, an address storage circuit that stores a row address corresponding to a word line of a defective memory cell that has a defective storage cell whose storage time is shortened as described above, and this defective address signal are used for accessing or refreshing. An address detection circuit R-AC is provided which includes an address comparison circuit which compares the address signal supplied from the address buffer R-ADB with the address signal to detect that the stored defective address is input. The address detection circuit R-AC detects memory access or refresh for a defective address which is missed, and causes all of the four memory arrays M0 to M3 to be simultaneously selected. In order to enable such simultaneous selection, the address signals stored in the storage circuit are stored in the memory arrays.
Lower bits commonly used for M0 to M3 (address signals ai-1 and ai for selecting the memory arrays M0 to M3)
(Excluding bits). Thereby, one failing defective address is stored as a common address regardless of whether there are any failing defective memory cells in the other three memory arrays.

Although not particularly limited, in this embodiment, in order to achieve high-speed operation, in other words, in order to reduce the output load capacity of the address buffer and increase the transmission speed of the address signal supplied to the redundant circuit, The detection circuit R-AC is arranged between the row address buffer R-ADB and its output drive circuit R-DRV.

Although not particularly limited, the address detection circuit R-
The memory circuit of the defective address, which is included in AC, is composed of a memory circuit using a fuse means using a polysilicon layer. Therefore, in order to selectively blow (blown) the fuse means, the address buffer R-
Address signals through ADB are used respectively.

FIG. 2 is a circuit diagram of a specific embodiment of the enable circuit and the unit circuit which form the address detection circuit R-AC.

In the following description, MOSFET (insulated gate field effect transistor) is an N-channel MOSF unless otherwise specified.
It is ET. In the figure, the MOSFET with an arrow added to the channel portion is a P-channel type.

The one address detection circuit is a unit circuit UAC0 including a storage circuit and an address comparison circuit, each of which has an address corresponding to the number of bits of the lower-order address signal.
And one enable circuit.

The terminals P1 to P4 are programming voltage supply terminals for writing the above-mentioned defective addresses, and when writing a predetermined defective address, the terminals P1, P3
Is supplied with a power supply voltage Vcc, and terminals P2 and P4 are supplied with the ground potential of the circuit.

The enable circuit is composed of the following circuit elements. The load MOSFET Q1 and the drive MOSFET Q2 form an inverter, and the drain and gate of the load MOSFET Q1 are connected to the terminal P3. The output of this inverter is connected to the gate of drive MOSFET Q3 which causes fuse F1 to be blown. This MOS
A fuse F1 is provided between the drain of the FET Q3 and the terminal P1, and its source is connected to the terminal P2. Also, the above MOSF
The gate of ET Q2 is connected to terminal P4. A resistor R2 is provided between the terminal P4 and the power supply voltage Vcc. The fuse F1 is made of, but not limited to, polysilicon. When writing a specified defective address, the power supply voltage Vcc is applied to the terminals P1 and P3, and the terminals P2 and P4
Is supplied with the ground potential of the circuit. As a result, the output of the inverter becomes high level and the drive MOSFET Q3 is turned on, so that the fuse F1 is automatically cut.

The following CMOS inverter and latch circuit are provided to determine whether or not the fuse F1 is blown.

The outputs of the CMOS NAND gate circuits G1 and G2 and one input are cross-connected to each other to form a latch circuit.

The above MOSFET Q3 drain output is the CMOS inverter circuit N1.
It is supplied to the input and the other input of one NAND gate circuit G2 forming the latch circuit. The output of the CMOS inverter circuit N1 is transmitted to the other input of the other NAND gate circuit G1 constituting the latch circuit and the gate of the feedback MOSFET Q4 in parallel with the drive MOSFET Q3. The output of the other NAND gate circuit G2 is supplied to the input of the CMOS inverter circuit N2. The enable signal φk is output from the output of the CMOS inverter circuit N2.

The unit circuit UAC0 of the defective address that is missed is composed of the following circuit elements. The memory circuit of the defective address that is missed is similar to the enable circuit described above.
It is composed of SFETs Q5 to Q9, a fuse F2, a CMOS inverter circuit N3, and CMOS NAND gate circuits G3 and G4 in a latch form. For writing the defective address, the non-inverted address signal a0 sent from the address buffer R-ADB is supplied to the gate of the MOSFET Q7 in parallel with the driving MOSFET Q6 forming the inverter. When writing a specified defective address, set pins P1 and P3 as described above.
Is supplied with a power supply voltage Vcc, and terminals P2 and P4 are supplied with the ground potential of the circuit. If the defective address signal a0 to be written is at high level, the MOSFET Q7 is turned on.
As a result, the drive MOSFET Q8 coupled to the fuse F2 is turned off, so that the cutting current does not flow in the fuse F2, so that the fuse F2 is not cut. If the defective address signal a0 is low level, the MOSFET Q7 is turned off. This allows the drive MO coupled to fuse F2.
Since the SFET Q8 is turned on, a cutting current flows through the fuse F2, and the fuse F2 is cut.

In order to determine whether or not the fuse F2 is blown, the same CMOS inverter circuit N3 and its feedback MOSF as described above are used.
An ET Q9 and latched NAND gate circuits G3, G4 are provided.

The 1-bit address comparison circuit corresponding to the defective address is a P-channel MOSFET Q10, Q in serial form.
11 and N channel MOSFET Q12, Q13 and P channel MOSF
ET Q14, Q15, N-channel MOSFETs Q16, Q17, and a CMOS inverter circuit N4. The above two series MOSF
Connection point of MOSFET Q11 and Q12 in ET circuit and MOSFET Q1
The connection point between 5 and Q16 is commonly connected to form the output terminal c0.

The non-inverted address signal a0 output from the address buffer R-ADB (or C-ADB) is supplied to the gates of the MOSFETs Q11 and Q12 in one of the series MOSFET circuits. The corresponding MOSFETs Q15 and Q16 in the other series MOSFET circuit
The address signal 0 inverted by the inverter circuit N4 is supplied to the gate of the.

Bad address signal a0 'depending on whether fuse F2 is blown or not
And 0'are the remaining MO in the above two series MOSFET circuits.
P-channel MOS such as SFET Q10 and Q17 and Q13 and Q14
Crossed supply to FET and N-channel MOSFET. The unit circuit UAC0 similar to the above has the remaining address signals a1 to
The same applies to ai-2.

Now, when the address signal a0 is set to a high level (logic "1") as a defective address, in other words, when the fuse F2 is not cut, the output a0 of the NAND gate circuit G3 forming the CMOS latch circuit 'Is high level, and the output 0'of the NAND gate circuit G4 is low level. Therefore, the N-channel MOSFET Q17 and the P-channel MOSFET Q14 are in the ON state.

P-channel MOSF if the address signal a0 input by memory access or refresh mode is low level
When the ET Q10 is turned on, the N-channel MOSFET is turned on by the high level of the address signal 0 inverted by the inverter circuit N4.
Q16 is turned on. In this way, when the two address signals do not match, the N-channel MOSF in the on state is turned on.
Low level (logic “0”) output signal depending on ET Q16 and Q17
C0 is sent.

N-channel MOSF if address signal a0 input by memory access or refresh mode is high level
When the ET Q12 is turned on, the P-channel MOSFET is turned on by the low level of the address signal 0 inverted by the inverter circuit N4.
Q15 is turned on. Thus, when both address signals match, the P-channel MOSFET in the ON state is
High-level (logic "1") output signal c0 depending on Q14 and Q15
Is sent. Output signals c1 to ci-2 are sent from the above circuits corresponding to the remaining address signals a1 to ai-2.

When the high-level (logical "1") coincidence output signals c0 to ci-2 and the logical "1" of the enable signal φk are obtained for all the bits of the address signal, the logical sum circuit G5
The defective address is detected by the output of the above, and the high-order 2 bits (ai-) to the row address decoders R-DCR0 to R-DCR3 and the row timing generation circuit R-TG are detected.
, Ai) is generated as an active signal AR. As a result, each row address decoder R-DCR0 to R-DCR3
Form a selection signal for the word line and the dummy word line corresponding to the lower bit addresses a0 to ai-2. The row-related timing generation circuit R-TG activates the timing signals φpa0 to φpa3 at the same time.

As a result, for example, when there is a defective defective memory cell in a specific word line of the memory array M0, the above-mentioned error is caused in the refresh operation of the other memory arrays M1 to M3 in the refresh operation (similar to the memory address operation). When the memory cells connected to the word line of the address corresponding to the word line are refreshed, they are refreshed at the same time. As a result, the refresh cycle of the defective defective memory cells is shortened to 1/4 of that of other memory cells. In other words, the refresh operation is performed on the other memory cells in a cycle that is four times as long as that of the above-mentioned missed memory cells. As a result, when the four memory arrays are sequentially selected, the power consumption can be greatly reduced to 1/4.

The enable signal .phi.k inhibits the generation of the signal AR by its logic "0" output.

The operational effects obtained from the above-described examples are as follows. That is, (1) by selectively setting the word lines of the plurality of memory arrays to the selected state and operating the sense amplifier,
Keep the refresh cycle longer, store the address of the word line where the defective defective memory cells are present as a common address for each memory array, and when that is specified, all memory arrays and sense amplifiers are stored. To the operating state. As a result, it is possible to relieve the defective memory cells and prolong the refresh cycle, so that the effect of significantly reducing the power consumption can be obtained.

(2) By arranging the address detection circuit of the defective memory cell, which is sparsely defective, adjacent to the corresponding address buffer, the signal line between the address buffer and the storage circuit and / or the address comparison circuit has the shortest distance. it can.
As a result, the parasitic capacitance of the signal line can be minimized, so that the output load capacitance seen from the address buffer is reduced, so that the operation can be speeded up.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, the number of memory arrays may be 2n. In addition, the memory array is divided into a plurality of sets, each of the divided plurality of memory arrays is regarded as one, and the inside thereof is further divided into four sets (2n is sufficient) for refreshing similar to the above. The selection may be performed. For example, in FIG. 1, one set of memory arrays M0 and M1 (1
It may be regarded as one memory array), and M2 and M3 are divided into other groups, and the selection operation similar to the above is performed for each group. In this case, based on the refresh cycle of the memory cells that are sloppy,
The refresh cycle can be doubled. If the memory array M0 has a defective bit, any one of the memory arrays M1 to M3 and M0 may be selected. In other words, the selected memory array does not have to be the entire array, and the memory array including at least the defective bit and the memory array in which the selected memory cell exists is selected and its sense amplifier is activated. It may be. In addition, the defective defective address storage circuit may be any circuit that selectively cuts a predetermined wiring using a laser beam. The defective defective memory circuits and address comparison circuits are
In addition to the above CMOS circuit, it may be configured by only an N-channel MOSFET (or a P-channel MOSFET).

The specific circuit configuration of each circuit block of the dynamic RAM can adopt various embodiments. For example, the address signals supplied from the external terminals are preferably those which simultaneously supply the row address signal and the column address signal from the independent external terminals. For example, in order to increase the storage capacity such as IM bit, the memory array is configured by providing a similar memory array and row address selection circuit on the right side of the column decoder in FIG. Various embodiments can be adopted such as a similar memory array provided on the lower side centering on the. The refresh address signal may be supplied from an external terminal.

The present invention can be widely used for dynamic RAMs that require refresh operations.

〔The invention's effect〕

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, by selectively setting the word lines of the plurality of memory arrays to the selected state and setting the sense amplifier to the operating state, the refresh cycle is lengthened and the address of the word line in which the defective memory cell that is absent is present. By storing as a common address of each memory array, and when it is designated, by operating a plurality of memory arrays and sense amplifiers, it is possible to relieve a missed memory cell and lengthen a refresh cycle. it can.

[Brief description of drawings]

FIG. 1 is an internal configuration block diagram showing an embodiment of a dynamic RAM according to the present invention, and FIG. 2 is a circuit diagram showing an embodiment of a unit circuit constituting the address detection circuit. M0 to M3 …… Memory array, SA0 to SA3 …… Sense amplifier,
R-ADB: Row address buffer, CW0 to CW3: Column switch, C-ADB: Column address buffer, R
-DCR0 to R-DCR3 ... Row address decoder, C-DCR
1, CDCR2 ... Column decoder, R-TG ... Row system timing generation circuit, C-TG ... Column system timing generation circuit, R-AC ... Address detection circuit, DIB ... Data input buffer, DOB ... Data Output buffer

Claims (2)

[Claims] 1. A plurality of memory arrays in which a plurality of word lines and a plurality of data lines are arranged so as to be orthogonal to each other, and memory cells are arranged at respective intersections thereof. A plurality of row addresses for selecting word lines in the memory array based on an access address signal provided externally or a refresh address signal supplied from an external or internal refresh address counter. A selection circuit, a column address selection circuit for selecting a data line in the memory array based on an address signal supplied from the outside, a sense amplifier activated in response to the selection operation of the memory array, An address storage circuit capable of setting a row address to which a refresh defective memory cell belongs, An address comparison circuit for comparing the address stored in the address storage circuit with the refresh address signal, a memory array including a memory cell having a refresh failure when an address match is detected by the address comparison circuit, and another memory array An address detection circuit including a logic circuit that forms a signal for instructing a selected state to the corresponding row address selection circuit, and the refresh cycle is shortened only for the row address to which the above defective memory cell belongs. A dynamic RAM that is configured as follows. 2. The address detection circuit is provided with an enable circuit for enabling or disabling a signal for instructing a selection state output from the address detection circuit to a row address selection circuit in advance. The dynamic RAM according to claim 1, characterized in that: