KR0172243B1 - Semiconductor memory device with enhanced repair efficiency - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device that improves the repair efficiency according to the refresh cycle when implementing a plurality of refresh cycles in one chip. The redundancy column access means for selecting a column of a cell to be repaired is connected between each unit cell block. And redundancy address selecting means for outputting a programmed address signal for selecting a column of defective cells using a fuse programmed with an address of a defective cell for inputting a block selection address and a column address, and from the redundant address selecting means. And a column decoder means for combining at least two output signals per one redundancy column and outputting the output signals to the redundant column access means.

Description

Semiconductor memory device with improved repair efficiency

1 is a cell configuration diagram of a conventional 64M DRAM.

2 is a circuit diagram illustrating an 8M cell block shown in FIG.

3 is a detailed circuit diagram of a column redundancy circuit and a decoder circuit for outputting the column decoder output signal shown in FIG.

4 is a configuration circuit diagram of an 8M cell block according to the first embodiment of the present invention.

5 is a configuration circuit diagram of an 8M cell block according to a second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11: 8M cell block 12_0 ~ 12_31: cell_array block

13: first fuse box 14: second fuse box

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having improved repair efficiency according to refresh cycles when a plurality of refresh cycles are implemented in one chip.

In general, as a semiconductor memory device is highly integrated, a memory chip is divided into a plurality of unit cell blocks. For example, in the case of 64M DRAM, 256 unit cell blocks are formed, and each unit cell block is composed of 256k bits. The 256 unit cell blocks are divided into 8M cell groups 11 as shown in FIG. 1 for the convenience of chip construction, and thus 32 unit cell blocks form 8M.

2 is a configuration circuit diagram of the 8M cell block 11 shown in FIG. 1, in which 32 unit cell blocks 12_0 to 12_31 are alternately positioned with a bit line sense amplifier interposed therebetween. Redundant column access transistors Q1 to Q32 are formed between -12_31.

In the cell array structure of the type described above, the output (ryi) of the column decoder is used as a control signal for controlling the operation of the redundancy column access transistors Q1 to Q32 that control the plurality of unit cell arrays 12_0-12_31.

The output signal ryi of the column decoder is a signal output from the redundancy address selection circuit (FIG. 3A) and the column decoder circuit (FIG. 3B) shown in FIG.

First, referring to a process in which an output signal ryi of a column decoder is generated, the redundancy address selection circuit (FIG. 3a) receives addresses corresponding to a cell block and a column to be repaired in the first and second fuse boxes 13 and 14. Each program is programmed in, and receives an address signal. In the normal operation in which the programmed address is not applied from the input address, the charges of the nodes A and B are discharged to the ground voltage through the first fuse box 13 or the second fuse box 14, so that the nodes A and The node B has a low state, and thus, even when the enabled column pass start signal / CS is applied, the output ryi of the column redundancy device remains low so that the column redundancy operation of the chip is not performed. On the other hand, in the programmed redundancy address selection circuit (Fig. 3a), when an address for selecting a defective cell is applied, the charges of the nodes A and B are grounded through the first fuse box 13 or the second fuse box 14. Since the node A is not discharged, the fuse output signal fuse_out has a high state due to the charge transferred through the PMOS transistor MP1 and the PMOS transistor MP2, and the enabled column pass start signal / CS and the fuse output having the high state are enabled. The combination of the signal fuse_out causes the output signal ryi of the column decoder circuit (Fig. 3B) to have high. Accordingly, the redundancy column access transistors Q1 to Q32 are turned on to perform data read / write operations through a cell connected to the spare bit line.

In the cell array structure of the semiconductor memory device having the structure shown in FIG. 2, the number of unit cell blocks that are activated is determined according to the refresh cycle. For example, if 4k and 8k refreshes are simultaneously implemented in 64M DRAM on the same chip, the unit cell block selected from the 8M group in the case of 8k refresh is activated only in one unit cell block of 32 unit cell blocks. In the case of refreshing, two unit cell blocks are activated.

That is, when one unit cell block is selected from the 8M group, only one column is repaired by the redundancy column decoder, but when two unit cell blocks are selected, two columns can be repaired simultaneously. Since the number of times is reduced to 1/2, there is a problem that the repair efficiency is lowered.

Accordingly, an object of the present invention is to provide a semiconductor memory device having improved repair efficiency by increasing the number of redundant column decoders without increasing the number of redundant columns.

In order to achieve the above object, in the semiconductor memory device of the present invention, redundancy column access means connected to each unit cell block and selecting a column of a cell to be repaired;

Redundancy address selection means for inputting a block selection address and a column address to output a programmed address signal for selecting a column of the defective cell using a fuse in which the address of the defective cell is programmed;

And a column decoder means for combining at least two output signals per one redundancy column by combining the output signals from the redundancy address selecting means and outputting them to the redundancy column access means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

4 is a configuration circuit diagram of the 8M cell block 11 according to the first embodiment of the present invention, and is input to the gates of the redundancy column access transistors Q1-Q32 so that the number of repaired cases remains constant regardless of the refresh cycle. One or more redundant column decoder output signals are implemented.

Here, the output signal of the redundancy column decoder is ryi_up, ryi_On, ryi_con, and ryi_up is used to repair 16 unit cell blocks from the 8M group of FIG. It is used to repair. At this time, the unit cell blocks selected at the same time are selected by the same selection address, but are repaired by ryi_uP or ryi_dn programmed to be repaired by the redundant column because the redundant column decoder exists separately.

The redundancy column access transistor Q16 existing between the unit cell blocks 12_15 and 12_16 is used when the cell blocks 12_15 and 12_16 are selected. That is, since the access transistor Q16 is used to repair the unit cell blocks 12_15 and 12_16, the access transistor Q16 is used both in the case where the repair operation occurs by ryi_up and in the case where the repair operation occurs by ryi_dn. Therefore, ryi_com is a redundancy decoder that operates when both ryi_up and ryi_dn operate, and are output by the OR operation of ryi_up and ryi_dn.

FIG. 5 is a circuit diagram of the 8M cell block 11 according to the second embodiment of the present invention. The redundancy column decoder output signal ryi_com shown in FIG. 4 is used as a global signal, and ryi_up, ryi_du is alternately implemented to be the gate input of the access transistor existing between the cell blocks 12_15 and 12_16. The configuration is connected between the node for inputting the redundancy column decoder output signal ryi_up and the output terminal for outputting the output signal ryi_com. NMOS transistor MN1 to which the block selection signal Bish is applied and NMOS transistor MN2 to which the block selection signal bis1 is applied as a gate are connected between the node for inputting the redundancy column decoder output signal ryi_dn and the output terminal for outputting the output signal ryi_com. .

First, when the cell block 12_15 is selected, the block selection signal Bish is high and Bis1 is low, and the ryi_up signal is input to the gate of the redundancy column access transistor Q16. When the cell block 12_16 is selected, the block selection signal Bish is low, Bis1. Becomes high and the ryi_dn signal is redundant in column access. It is input to the gate of the transistor Q16.

As described above, when the semiconductor memory device of the present invention is used, when the embroidery and refresh cycles are implemented in one chip, the repair efficiency according to the refresh cycles can be improved.

Claims (4)

A semiconductor memory device comprising a plurality of unit cell blocks, comprising: redundancy column access means connected between each unit cell block and selecting a column of a cell to be repaired, and a block selection address and a column address as inputs At least two output signals per redundancy column by combining redundancy address selecting means for outputting a programmed address signal for selecting a column of defective cells using an address programmed fuse and an output signal from the redundancy address selecting means. And column decoder means for outputting to the redundancy column access means. The semiconductor memory device according to claim 1, wherein the column decoder means has three output signals, one of which OR-operates the other two signals. 3. The semiconductor memory device according to claim 2, wherein one output signal produced by said OR operation is input to said redundancy column access means in which the output of the column decoder means is overlapped in accordance with a refresh mode. 2. The output of the redundant column access means according to claim 1, wherein the column decoder means has two output signals, one of which is selected by a block selection signal and the output of the column decoder means is duplicated according to the refresh mode. And input to the redundancy column access means.