KR100480230B1 - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR100480230B1 KR100480230B1 KR10-1998-0031874A KR19980031874A KR100480230B1 KR 100480230 B1 KR100480230 B1 KR 100480230B1 KR 19980031874 A KR19980031874 A KR 19980031874A KR 100480230 B1 KR100480230 B1 KR 100480230B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
Abstract
본 발명은 반도체장치의 금속배선 형성방법에 관한 것으로서, 본 발명의 목적은 다층 금속배선막 형성시 금속라인으로의 수분 침투에 의한 부식을 방지하기 위해 방지막으로 사용되는 TEOS산화막의 평탄화를 위한 블랭킷에치후 발생되는 텐실스트레스에 의한 금속의 쐐기형 깨짐현상을 방지할 수 있는 반도체장치의 금속배선 형성방법을 제공함에 있다. 상기와 같은 목적을 실현하기 위한 본 발명은 금속라인이 형성된 상태에서 장벽산화막을 증착한후 블랭킷에치하여 평탄화함으로서 다층 금속배선을 형성하는 반도체장치의 금속배선 형성방법에 있어서, 금속라인이 형성된 상태위 식각속도가 낮은 TEOS산화막을 증착하는 단계와, 상기 단계에서 증착된 TEOS산화막위에 포터레지스터를 도포하고 하드베이크하는 단계와, 상기 단계에서 하드베이크된 결과물을 마스크없이 일정한 두께로 블랭킷에치하는 단계와, 상기 단계에서 블랭킷에치된 결과물에 제2산화막과 상층 금속배선을 순서대로 형성하고 보호막을 형성하여 합금하는 단계로서 금속배선을 형성하여 TEOS산화막의 낮은 습식에칭율과 텐실스트레스의 감소로 금속의 쐐기형 깨짐현상을 방지할 수 있게 되어 소자의 수명 및 소자의 신뢰성이 증대되어 금속에서의 누설전류를 감소시킬 수 있다는 이점이 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a semiconductor device, and an object of the present invention is to provide a blanket for planarization of a TEOS oxide film used as a barrier to prevent corrosion due to moisture penetration into metal lines when forming a multilayer metal wiring film. The present invention provides a method for forming a metal wiring in a semiconductor device that can prevent a wedge-shaped cracking phenomenon of a metal due to tensile stress generated after dentition. In the present invention for realizing the above object, in the metal line forming method of the semiconductor device in which the multilayer oxide wiring is formed by depositing a barrier oxide film in the state where the metal line is formed and flattening the blanket. Depositing a TEOS oxide film having a low etching rate above, applying and hard-baking a port register on the TEOS oxide film deposited in the step, and blanket-etching the hard-baked result in a predetermined thickness without a mask. And forming the second oxide film and the upper metal wiring in order and alloying the protective film by forming the second oxide film and the upper metal wiring in order in the above step, and forming the metal wiring to reduce the wet etching rate of the TEOS oxide film and the reduction of the tensil stress. It is possible to prevent the wedge-shaped cracking of the device, which increases device life and device reliability. It has the advantage of reducing the leak current in the control of metal.
Description
본 발명은 반도체장치의 금속배선 형성방법에 관한 것으로서, 보다 상세하게는 다층 금속배선막 형성시 금속라인으로의 수분 침투에 의한 부식을 방지하기 위해 방지막으로 사용되는 TEOS산화막의 평탄화를 위한 블랭킷에치후 발생되는 텐실스트레스에 의한 금속의 쐐기형 깨짐현상을 방지할 수 있는 반도체장치의 금속배선 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a semiconductor device, and more particularly, to blanketing a TEOS oxide film used as a prevention film to prevent corrosion due to moisture penetration into a metal line when forming a multilayer metal wiring film. The present invention relates to a method for forming metal wirings in a semiconductor device that can prevent wedge-shaped cracking of metals due to generated tensile stresses.
반도체소자를 고집적화함에 따라 소자의 동작속도를 증가시키기 위해서는 다층 금속배선 공정이 필요하며 그에따라 금속층간 평탄화 기술이 중요하다. As the semiconductor devices are highly integrated, a multi-layer metallization process is required to increase the operation speed of the devices. Therefore, planarization between metal layers is important.
보통 평탄화 물질로 SOG(Spin On Glass) 및 PHOTO RESISTER를 사용하나 이러한 물질은 수분을 다량 함유하여 수분을 없애기 위한 열공정이 반드시 필요하며 금속라인으로의 수분 침투를 방지하기 위한 장벽산화막이 요구된다. Usually, SOG (Spin On Glass) and PHOTO RESISTER are used as the planarization material. However, these materials contain a large amount of moisture, which requires a thermal process to remove moisture, and a barrier oxide film is required to prevent moisture penetration into metal lines.
그래서, 장벽산화막으로는 기능이 우수한 TEOS산화막을 사용한다. Therefore, TEOS oxide film having excellent function is used as the barrier oxide film.
그런데 이 장벽산화막의 평탄화를 위한 전면식각후 장벽산화막이 갖는 +4.5×108 Dyne/㎠ 의 텐실스트레스(Tensile Stress)에 의해 에스펙트율이 큰 부분에서는 금속의 쐐기형 깨짐현상이 발생한다.However, the wedge-shaped cracking phenomenon of the metal occurs in the large aspect ratio due to Tensile Stress of + 4.5 × 10 8 Dyne / cm 2 of the barrier oxide film after the entire surface etching for planarization of the barrier oxide film.
도1은 일반적인 방법에 의한 TEOS산화막의 블랭킷에치된 상태를 나타낸 도면으로서 금속라인(30) 위에 17000Å 두께의 TEOS산화막(40)을 증착한후 평탄화를 위해 블랭킷에치를 R.O.X(Remain Oxide Thickness) 9000Å이 되도록 에칭한다. 그런데 TEOS산화막(40)의 장점인 금속 에스펙트율이 큰 부분에서의 GAP FILL은 우수하나 그에 따라 TEOS산화막(40) 내부에 Si-H 결합구조가 증가하여 TEOS산화막(40)의 습식에칭율(7:1 BOE, 25℃ 조건) 특성이 아주 높게 되어 평탄화를 위한 블랭킷에치시에도 과도한 에치가 발생하여 금속라인(30)에 식각현상이 발생되고 R.O.X가 크기 때문에 TEOS산화막(40) 자체의 텐실스트레스에 의한 금속의 쐐기형 깨짐현상(N)이 발생하게 되어 전류누설 및 소자의 수명을 감소시키게 된다는 문제점이 있다. 1 is a view showing a blanket etched state of a TEOS oxide film according to a general method. After depositing a TEOS oxide film 40 having a thickness of 17000 Å on a metal line 30, the blanket etch is ROX (Remain Oxide Thickness) 9000 Å for planarization. Etch so that it may become. However, the GAP FILL is excellent in the metal aspect ratio, which is an advantage of the TEOS oxide film 40, but the Si-H bonding structure is increased in the TEOS oxide film 40, so that the wet etching rate of the TEOS oxide film 40 is increased. 7: 1 BOE, 25 ℃ condition) The characteristics of the TEOS oxide film 40 itself is tensil stress due to the excessively high etch occurs and excessive etching occurs even in the blanket etch for the planarization and the ROX is large There is a problem that the wedge-shaped crack phenomenon (N) of the metal is generated by the current leakage and reduce the life of the device.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 장벽산화막인 TEOS산화막의 텐실스트레스 및 습식에칭율이 높은 현상에 의한 금속의 쐐기형 깨짐현상을 방지하도록 하는 반도체장치의 금속배선 형성방법을 제공함에 있다. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device for preventing wedge-shaped cracking of metals due to high tensile stress and wet etching rate of TEOS oxide, which is a barrier oxide. A metal wiring forming method is provided.
상기와 같은 목적을 실현하기 위한 본 발명은 금속라인이 형성된 상태에서 장벽산화막을 증착한후 블랭킷에치하여 평탄화함으로서 다층 금속배선을 형성하는 반도체장치의 금속배선 형성방법에 있어서, 금속라인이 형성된 상태위 식각속도가 낮은 TOES산화막을 증착하는 단계와, 상기 단계에서 증착된 TEOS산화막위에 포토레지스터를 도포하고 하드베이크하는 단계와, 상기 단계에서 하드베이크된 결과물을 마스크없이 일정한 두께로 블랭킷에치하는 단계와, 상기 단계에서 블랭킷에치된 결과물에 제2산화막과 상층 금속배선을 순서대로 형성하고 보호막을 형성하여 합금하는 단계로서 금속배선을 형성한다. In the present invention for realizing the above object, in the metal line forming method of the semiconductor device in which the multilayer oxide wiring is formed by depositing a barrier oxide film in the state where the metal line is formed and flattening the blanket. Depositing a TOES oxide film having a low etching rate, applying a photoresist to the TEOS oxide film deposited in the above step, and hard baking, and blanket-etching the resultant hard bake at a predetermined thickness without a mask. And forming a second oxide film and an upper metal wiring in order, and forming a protective film on the resultant blanket etched in the above step to form a metal wiring.
상기와 같이 이루어진 본 발명을 설명하면 식각속도가 낮은 TOES산화막을 증착하여 식각시 과도한 에칭에 의한 금속의 식각이 발생되지 않도록 되며 단차가 높은 지역에 대한 평탄화 특성이 좋게되어 TOES산화막의 두께를 과도히 남기지 않아 텐실스트레스를 없애고 보호막 형성후 합금함으로서 TEOS산화막의 텐사일스트레서에 의한 금속의 쐐기형 깨짐현상을 방지하게 된다. When explaining the present invention made as described above, by etching the TOES oxide film having a low etching rate to prevent the etching of the metal due to excessive etching during etching, the planarization characteristics of the high step area is good, the thickness of the TOES oxide film excessively By removing the tensil stress and leaving the alloy after forming the protective film, the wedge-shaped cracking phenomenon of the metal by the tensil stresser of the TEOS oxide film is prevented.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도2는 본 발명의 의한 실시예로서 장벽산화막의 평탄화 공정을 단계적으로 나타낸 단면도이다. Figure 2 is a cross-sectional view showing a planarization process of the barrier oxide film step by step according to an embodiment of the present invention.
도2의 (A)는 BPSG막(10) 위에 형성된 금속라인(30)위에 TEOS산화막(40)을 증착한 상태를 나타낸 단면도이다. 2A is a cross-sectional view showing a state in which the TEOS oxide film 40 is deposited on the metal line 30 formed on the BPSG film 10.
이때 TEOS산화막(40)은 압력 2.2 Torr로 고주파출력이 1215W, 저주파출력이 770W로 하는 듀얼파워를 사용하여 TEOS액 1.6 ㎖, 02 7 slm을 플라즈마 증착법으로 17000±1000Å의 두께로 증착하게 된다. 그래서 TEOS산화막(40)의 습식에칭율 특성이 30～35Å/sec, 스트레스가 -0.5×109 ～ -1.5×109 dyne/㎠ 가 되도록 한다.At this time, the TEOS oxide film 40 is deposited to a thickness of 17000 ± 1000Å by the plasma deposition method using 1.6 ml of TEOS solution and 02 7 slm using dual power with a high frequency output of 1215W and a low frequency output of 770W at a pressure of 2.2 Torr. Thus, the wet etching rate characteristic of the TEOS oxide film 40 is 30 to 35 kPa / sec, and the stress is -0.5 x 10 9 to -1.5 x 10 9 dyne / cm 2.
도2의 (B)는 도2의 (A)의 결과물에 포터레지스터(60)를 도포한 상태를 나타낸 단면도이다. FIG. 2B is a cross-sectional view showing a state in which the port register 60 is applied to the resultant product of FIG.
포터레지스터(60)는 TEOS산화막(40)의 토폴로지가 심한 부분을 평탄화시키기 위해 1300Å의 두께로 도포하고 TEOS산화막(40)과의 접착력을 향상시키기 위해 130℃에서 약 50분간 하드베이크하게 된다. The port register 60 is applied to a thickness of 1300 kPa to planarize the heavily topological portion of the TEOS oxide film 40 and hard-baked at 130 ° C. for about 50 minutes to improve adhesion to the TEOS oxide film 40.
이때 TEOS산화막(40)과 베이크된 포터레지스터(60)의 전체 두께는 23600Å이 된다. At this time, the total thickness of the TEOS oxide film 40 and the baked port register 60 is 23600 kPa.
도2의 (C)는 도2의 (B)의 결과물을 층간 평탄화를 위해 블랭킷에치한 상태를 나타낸 단면도이다. FIG. 2C is a cross-sectional view showing a state in which the resultant product of FIG. 2B is blanket etched for interlayer planarization.
평탄화를 위해 사용된 포터레지스터(60)를 블랭킷에치하기 위해서는 먼저 O2가스를 이용하여 플라즈마방식으로 포터레지스터(60)를 제거하고 TEOS산화막(40)을 CF계열 가스로 ROX가 8000Å까지 마스크없이 플라즈마 에치하게 된다.In order to blanket-etch the port register 60 used for planarization, the port register 60 is removed by plasma using O 2 gas, and the TEOS oxide film 40 is CF-based gas without ROX up to 8000Å without a mask. Plasma etch.
이때의 에치조건은 압력은 600mTorr, 출력은 450W로 하고 CF4는 100sccm, CHF3는 30sccm, O2는 30sccm의 조건하에서 블랭킷에치하고 폴리머 찌꺼기를 제거하기 위해 폴리아미드 성분으로 폴리머제거용으로 사용되는 ACT처리를 하여 폴리머를 제거한다.The etch condition is 600mTorr pressure, 450W output, CF 4 is 100sccm, CHF 3 is 30sccm, O 2 is blanket scetched and polyamide is used for polymer removal to remove polymer residue. ACT treatment to remove the polymer.
도2의 (D)는 도2의 (C)의 결과물에 제2산화막(50)을 증착한 상태를 나타낸 단면도이다. FIG. 2D is a cross-sectional view showing a state in which the second oxide film 50 is deposited on the resultant product of FIG.
제2산화막(50)은 이후 증착될 상부 금속층(70)으로의 수분침투를 방지하기 위해 약 6000Å의 두께로 증착하게 된다. The second oxide film 50 is deposited to a thickness of about 6000 kPa in order to prevent moisture penetration into the upper metal layer 70 to be deposited later.
그런다음 도2의 (E)에 도시된 바와 같이 상부 금속층(70)의 증착 및 패턴을 형성한후 최종적으로 보호막(80)을 약 10000Å으로 증착하고 TEOS산화막(40)의 쐐기형 깨짐현상을 방지하기 위해 410℃로 30분간 튜브로(Tube furnace)에서 합금 열공정으로 한다. Then, as shown in FIG. 2E, after the deposition and the pattern of the upper metal layer 70 are formed, the protective film 80 is finally deposited to about 10000 microns and the wedge-shaped crack of the TEOS oxide film 40 is prevented. To do this, the alloy thermal process is carried out in a tube furnace at 410 ° C. for 30 minutes.
상기한 바와 같이 본 발명은 장벽산화막의 습식식각율 특성이 낮도록 하여 블랭킷에치시 단차에 따른 과도한 에치가 발생하지 않도록 하여 하부층의 금속이 식각되지 않도록 하며, 낮은 습식식각율 특성과 텐실스트레스의 감소로 블랭킷에치후 남은 장벽산화막의 두께를 얇게하여 텐실스트레스에 의한 금속의 쐐기형 깨짐 현상을 줄일 수 있어 소자의 수명 및 소자의 신뢰성이 증대되어 금속의 누설전류를 감소시킬 수 있다는 이점이 있다.As described above, according to the present invention, the wet etch rate characteristic of the barrier oxide film is low so that excessive etch does not occur due to the step difference in the blanket etch so that the metal of the lower layer is not etched, and the low wet etch rate characteristic and tensil stress are reduced. By reducing the thickness of the barrier oxide film remaining after the furnace blanket etching, it is possible to reduce the wedge-shaped cracking phenomenon of the metal due to the tensile stress, thereby increasing the lifespan and reliability of the device, thereby reducing the leakage current of the metal.
도1은 종래의 방법에 의해 형성하는 다층 금속배성 형성공정중 장벽산화막의 평탄화단계를 나타낸 단면도이다. 1 is a cross-sectional view showing a planarization step of a barrier oxide film during a multilayer metal composition forming process formed by a conventional method.
도2는 본 발명에 의한 방법으로 장벽산화막의 평탄화 공정을 단계적으로 나타낸 단면도이다. 2 is a cross-sectional view showing the planarization process of the barrier oxide film step by step according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
30 : 금속라인 40 : TEOS산화막30 metal line 40 TEOS oxide film
50 : 제2산화막 60 : 포토레지스터50: second oxide film 60: photoresist
80 : 보호막 80: shield
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05235184A (en) * | 1992-02-26 | 1993-09-10 | Nec Corp | Manufacturing method of multilayer wiring structural body of semiconducot rdevice |
| WO1994029899A1 (en) * | 1993-06-04 | 1994-12-22 | Vlsi Technology, Inc. | Method enhancing planarization etchback margin, reliability, and stability of a semiconductor device |
| JPH07312368A (en) * | 1994-04-18 | 1995-11-28 | Advanced Micro Devices Inc | Method to form even structure of insulation film |
| JPH09213800A (en) * | 1996-02-07 | 1997-08-15 | Nec Corp | Semiconductor device and manufacture thereof |
| KR0141562B1 (en) * | 1994-05-26 | 1998-07-15 | 김주용 | Method of forming metal wiring in semiconductor device |
| KR19980025800A (en) * | 1995-10-05 | 1998-07-15 | 윌리엄 이. 힐러 | Planar Dielectric Layer Formation Method and Multilevel Wiring Patterns |
| KR19980036071A (en) * | 1996-11-15 | 1998-08-05 | 김광호 | Method of manufacturing a semiconductor device having a voidless passivation layer |
-
1998
- 1998-08-05 KR KR10-1998-0031874A patent/KR100480230B1/en not_active IP Right Cessation
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05235184A (en) * | 1992-02-26 | 1993-09-10 | Nec Corp | Manufacturing method of multilayer wiring structural body of semiconducot rdevice |
| WO1994029899A1 (en) * | 1993-06-04 | 1994-12-22 | Vlsi Technology, Inc. | Method enhancing planarization etchback margin, reliability, and stability of a semiconductor device |
| JPH07312368A (en) * | 1994-04-18 | 1995-11-28 | Advanced Micro Devices Inc | Method to form even structure of insulation film |
| US5503882A (en) * | 1994-04-18 | 1996-04-02 | Advanced Micro Devices, Inc. | Method for planarizing an integrated circuit topography |
| KR0141562B1 (en) * | 1994-05-26 | 1998-07-15 | 김주용 | Method of forming metal wiring in semiconductor device |
| KR19980025800A (en) * | 1995-10-05 | 1998-07-15 | 윌리엄 이. 힐러 | Planar Dielectric Layer Formation Method and Multilevel Wiring Patterns |
| JPH09213800A (en) * | 1996-02-07 | 1997-08-15 | Nec Corp | Semiconductor device and manufacture thereof |
| KR19980036071A (en) * | 1996-11-15 | 1998-08-05 | 김광호 | Method of manufacturing a semiconductor device having a voidless passivation layer |
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