KR0141562B1 - Method of forming metal wiring in semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multi-metal interconnection in a semiconductor device manufacturing process. After forming a metal layer to planarize an interlayer insulating film and a protective film formed on a large interconnection and to improve electrical properties of the metal interconnection The reliability of the device can be increased by forming metal wires with positive slop by certain etching processes (natural oxide removal, primary and secondary etching processes, barrier metal removal, residue removal, and protection processes). The present invention relates to a method for forming a multi-metal wiring of a semiconductor device.

Description

Method of forming multi-metal wiring of semiconductor device

1A and 1B are cross-sectional views of a device for explaining a method of forming a multi-metal wiring of a conventional semiconductor device.

2A to 2C are cross-sectional views of a device for explaining a method for forming a multi-metal wiring of a semiconductor device according to the present invention.

* Explanation of symbols for main parts of the drawings

1: Silicon substrate 2: Insulation layer

3, 3A: bottom metal wiring 4: 1st IMO

5: SOG film 6: second IMO

7, 7A: upper metal wiring 8: first protective film

9: 2nd protective film 10: Molding film

11: O ₃ -TEOS film 12: Void

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multi-metal interconnection of a semiconductor device, and in particular, an intermetallic insulating film or passivation formed thereon by allowing a metal interconnection formed by a predetermined etching process after forming a metal layer to have a positive slop. The present invention relates to a method of forming a multi-metal interconnection of a semiconductor device in which the planarization of the ()) and the electrical characteristics of the metal interconnection are improved to increase the reliability of the device.

In general, in the manufacturing process of a semiconductor device, the metal wiring is formed in a double or multi level structure, and as the degree of integration of the device increases, the topology between the metal wirings increases. In addition, since the space between the adjacent metal wirings is narrowed, the step coverage becomes poor and the surface planarization becomes difficult at the time of forming the subsequent interlayer insulating film or the protective film. Accordingly, an intermetallic insulating film or a protective film is formed in a multi-layered structure. An SOG film is used for step coverage and surface planarization in forming the interlayer insulating film. This SOG film contains a large amount of moisture, and the electrical properties of the metal wiring are degraded due to the release of moisture during the curing process, and voids occur due to moisture infiltration during the molding process. Is generated. In addition, cracks are generated due to stress in the subsequent heat treatment process, thereby reducing the reliability of the device.

1A and 1B are cross-sectional views of a device for explaining a method of forming a multi-metal wire of a conventional semiconductor device.

First, as shown in FIG. 1A, a lower metal layer is formed on a silicon substrate 1 on which an integrated side of the device is formed and an insulating layer 2 is formed thereon, and then a lower metal wiring 3 is formed through an etching process. Next, a first inter-metal oxide (Inter-Metal Oxide) (hereinafter referred to as IMO) 4 is formed. Thereafter, the SOG film 5 is applied, cured, and planarized to form a second IMO 6, thereby forming intermetallic insulating films 4, 5, and 6.

Subsequently, as shown in FIG. 1B, an upper metal layer is formed on the interlayer insulating layers 4, 5, and 6, and an upper metal wiring 7 is formed through an etching process, and then the first and second passivation layers 8, 9) are sequentially formed, and then a molding film 10 is formed using a fix. At this time, moisture is released during the curing of the SOG film 5, and as a result, the quality of the interlayer insulating films 4, 5, and 6 and the lower and upper metal wires 3 and 7 is reduced, and Moisture diffuses toward the substrate, resulting in leakage currents. In addition, when the molding layer 10 is formed, cracks due to B / I test defects and stress due to poor sidewell step coverage are generated, and voids 12 are generated due to moisture infiltration. There is a problem of lowering the reliability.

Accordingly, an object of the present invention is to provide a method for forming a multi-metal wiring of a semiconductor device which can solve the above problems by forming a metal wiring having a positive slop by a predetermined etching process after forming a metal layer. .

According to an aspect of the present invention, there is provided a method of forming a multi-metal interconnection line of a semiconductor device, the method comprising: forming a lower metal interconnection on an insulating layer formed on an upper portion of a substrate on which an internal device integrated layer is formed; Forming an interlayer insulating film, forming an upper metal wiring on the metal interlayer insulating film, and sequentially forming a first passivation film, a second passivation film, and a molding film on the upper metal wiring. In the metal wiring forming method, the step of forming the lower metal wiring and the upper metal wiring, the step of removing the natural oxide film on the upper metal layer after forming the metal layer, and first etching the metal layer using a semi-etch process And second etching the metal layer using an etch stop etching process. The residue remaining in the metal layer is removed by an over-etching process, and then Cl ₂ is replaced by F in a protective process, so that the lower metal wiring and the upper metal wiring have a positive slope.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A to 2C are cross-sectional views of devices for explaining a method of forming a multi-metal interconnection of a semiconductor device according to the present invention.

Referring to FIG. 2A, a Ti / TiN / Al alloy is deposited on a silicon substrate 1 having an integrated layer formed thereon and an insulating layer 2 formed thereon, and then positively inclined through an etching process. The bottom metal wiring 3A having a positive slop is formed. At this time, the process for forming the lower metal wiring 3A having a positive slope is as follows.

First, a Ti / TiN / Al alloy or the like is deposited to form a lower metal layer, and a native oxide (not shown) grown on top of the lower metal layer is 140BCl ₃ and 10Cl at a pressure of about 25 mTorr and an energy of about -250 VDC. using an etchant (etchant) for ₂ removed for about 2.5 minutes, and a pressure of about 30mTorr and about -190VDC of energy by using the etchant of 150HCl _3, 35Cl ₂ and ₃ 15CHF bansik for about 8 minutes each The lower metal layer is first etched by performing a half etch process. Subsequently, secondary etching was performed for about 10 minutes using an etchant of 150HCl ₃ , 20Cl ₂ and 30CHF ₃ at a pressure of about 30 mTorr and an energy of about -150 VDC using an etch end of point etching method. Next, the barrier metal of the etch stop is removed for about 8 minutes using an etchant of 150BCl ₃ , 20Cl ₂ and 15CHF ₃ at a pressure of about 30 mTorr and an energy of about -250 VDC, and a pressure of about 80 mTorr and Residue is removed by an Over Etch method for about 10 minutes using an etchant of 50CHF ₃ and 50CF ₄ with an energy of about 160W. Finally, a passivation step of replacing Cl ₂ with F for about 3 minutes using an etchant of 50CHF ₃ at a pressure of about 100 mTorr and an energy of about 160 W is performed.

Referring to FIG. 2B, the first IMO 4 is formed on the lower metal wiring 3A having a positive slope to a thickness of 1000 to 2000 GPa, and the O ₃ -TEOS film 11 having excellent step coverage is 3000 to 6000 GPa. Deposit. After the second IMO (6) is formed to a thickness of 1000 to 300Å, the interlayer insulating films 4, 11 and 6 are formed, and the Ti / TiN / Al alloy is deposited thereon, and then positively inclined through the etching process. An upper metal wiring 7A having a shape is formed. At this time, the process for forming the upper metal wiring 7A having the positive inclination is as follows. First, a Ti / TiN / Al alloy is deposited to form an upper metal layer, and a native oxide (not shown) grown on top of the upper metal layer 7A is applied at a pressure of about 25 mTorr and an energy of about -250 VDC. Remove for about 2 minutes 30 seconds using an etchant of 140BCl ₃ and 10Cl ₂ , and use an etchant of 150HCl ₃ , 35Cl ₂ and 15CHF ₃ at a pressure of about 30 mTorr and an energy of about -190VDC. The lower metal layer is first etched through a half etch process for minutes. Subsequently, secondary etching was performed for about 10 minutes using an etchant of 150HCl ₃ , 20Cl _2, and 30CHF ₃ at a pressure of about 30 mTorr and an energy of about -150 VDC using an etch end of point etching method. Using an etchant of 150BCl ₃ , 20Cl ₂ and 15CHF ₃ at a pressure of about 30 mTorr and an energy of about -250 VDC to remove the barrier metal of the etch stop for about 8 minutes, and a pressure of about 80 mTorr and about Residue is removed by an Over Etch method for about 10 minutes using an etchant of 50CHF ₃ and 50CF ₄ with 160 W of energy. Finally, a passivation step is performed to replace Cl ₂ with F for about 3 minutes using an etchant of 50CHF ₃ at a pressure of about 100 mTorr and an energy of about 160W.

FIG. 2C is a cross-sectional view of the semiconductor device being formed flat by forming the molding film 10 using the pix after sequentially forming the first and second passivation films 8 and 9 in the state of FIG. 2B. . At this time, an oxide film is deposited on the first passivation film 8 and a nitride film is deposited on the second passivation film 9.

According to this method, since the upper and lower metal wirings 3A and 7A have positive inclinations, the step coverage of the insulating film and the protective film deposited on the upper part is improved, the planarization is improved, and the SOG film is not used. The intrinsic resistance of is kept low to increase the reliability of the device.

As described above, according to the present invention, by etching to have the metal positive slop by a predetermined etching process after the metal layer, the planarization of the interlayer insulating film and the protective film and the electrical properties of the metal wiring are improved, thereby increasing the reliability of the device. There is an excellent effect that can be.

Claims (3)

Forming a lower metal interconnection on an insulating layer formed on the substrate on which the device internal integrated layer is formed, forming an intermetallic insulation layer on the lower metal interconnection, and forming an upper metal interconnection on the intermetallic insulation layer And forming a first protective film, a second protective film, and a molding film sequentially on the upper metal wiring, wherein the forming process of each of the lower metal wiring and the upper metal wiring is performed. Removing the natural oxide layer on the upper portion of the metal layer after forming the metal layer, first etching the metal layer by using a half etching process, and second etching the metal layer by using an etching stop point etching process. and the residue remaining on the metal layer after the protection step to remove excess etching process replacing the Cl ₂ as F Method is formed by performing a multi-step metal wiring of a semiconductor device which is characterized in that the lower metal wiring and an upper metal wiring so as to have a positive slope. The method of claim 1, wherein the metal layer is formed of a stacked structure of Ti, TiN, and Al alloys. The method of claim 1, wherein the native oxide layer is removed using an etchant of 140 BCl ₃ and 10Cl ₂ at a pressure of about 250 mTorr and an energy of about −250 VDC, and the primary etching process is performed at a pressure of about 30 mTorr and about −190 VDC. with energy by using the etchant of 150HCl _3, 35Cl ₂ and ₃ 15CHF bansik and not to be carried out each step, the second etching process in the 150HCl _3, 20Cl 30CHF ₂ and ₃ in a pressure of about 30mTorr and about -150VDC energy Etch stop point etching process using a cheat, the residue is removed using an etchant of 50CHF ₃ and 50 CF ₄ at a pressure of about 80mTorr and energy of about 160W, the protection process is a pressure of about 100mTorr And using an etchant of 50CHF _{3 with} an energy of about 160W.