KR100467777B1 - Method of fuse disconnection - Google Patents
Method of fuse disconnection Download PDFInfo
- Publication number
- KR100467777B1 KR100467777B1 KR10-2002-0031709A KR20020031709A KR100467777B1 KR 100467777 B1 KR100467777 B1 KR 100467777B1 KR 20020031709 A KR20020031709 A KR 20020031709A KR 100467777 B1 KR100467777 B1 KR 100467777B1
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- Prior art keywords
- metal wiring
- fuse
- fuse disconnection
- plasma
- etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Drying Of Semiconductors (AREA)
Abstract
퓨즈 단절 방법에 관한 것으로, 그 목적은 레이저 빔에 의한 손상을 방지하고 고집적화된 소자에 적용가능한 퓨즈 단절 방법을 제공하는 데 있다. 이를 위해 본 발명에서는 플라즈마를 이용하여 단락시키고자 하는 금속배선의 일부분을 식각하는 것을 특징으로 하며, 이로써 더욱 미세한 소자에 대해서도 퓨즈 단절을 수행할 수 있게 된다.The present invention relates to a fuse disconnection method, which aims to prevent damage by a laser beam and to provide a fuse disconnection method applicable to a highly integrated device. To this end, the present invention is characterized in that by etching the part of the metal wiring to be short-circuited by using the plasma, it is possible to perform fuse disconnection even for finer devices.
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 퓨즈를 단절하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of disconnecting a fuse.
일반적으로 프로그램 가능한 소자, 일례로 FPGA(field programmable gate array)와 같은 소자를 형성할 경우에는 원하는 부분의 금속배선을 단락시키기 위해 별도의 비정질 유전체를 삽입하는 방법을 주로 사용하여 왔다.In general, when forming a programmable device, for example, a field programmable gate array (FPGA), a method of inserting a separate amorphous dielectric to short-circuit a desired metal wiring has been mainly used.
도 1은 비정질 유전체 삽입된 것을 도시한 단면도로서, 이에 도시된 바와 같이, 단락시키고자 하는 하부 금속배선(1) 상에 비정질 실리콘(2)과 같은 유전체를 형성하고, 비정질 실리콘(2) 상에 상부 금속배선(3)을 형성하였다.FIG. 1 is a cross-sectional view showing an amorphous dielectric inserted, and as shown therein, a dielectric such as amorphous silicon 2 is formed on the lower metal wiring 1 to be shorted, and on the amorphous silicon 2. The upper metal wiring 3 was formed.
그러나 이러한 방법은 유전체 형성 공정이 추가로 필요하기 때문에 번거로운 단점이 있었으며, 또한 고전압에 대한 손상으로 수율이 낮아 생산원가가 상승하는문제점이 있었다.However, this method has a disadvantage in that it requires an additional dielectric formation process, and also has a problem in that the production cost increases due to a low yield due to damage to high voltage.
이러한 문제점을 해결하기 위해 레이저를 이용하여 단락시키고자 하는 금속배선을 제거하여 퓨즈를 단절시키는 방법이 등장하였다. 이 경우 레이저 빔의 크기가 2.5~3 ㎛ 로서 비교적 크기 때문에 웨이퍼 내 다이(die) 크기가 커져 생산 가능한 순수 다이 숫자가 적은 단점이 있다.In order to solve this problem, a method of disconnecting a fuse by removing a metal wiring to be shorted using a laser has emerged. In this case, since the size of the laser beam is relatively large as 2.5 to 3 μm, the die size in the wafer is increased, and thus the number of pure dies that can be produced is small.
특히 소자의 고집적화 추세에 따라 선폭이 가늘어질수록 레이저 빔에 의해 이웃하는 다른 금속배선까지 손상되는 현상이 심각한 문제점으로 지적되고 있다.In particular, as the line width becomes thinner according to the trend of higher integration of devices, the phenomenon that damage to other adjacent metal wirings by a laser beam is pointed out as a serious problem.
따라서, 고집적화되는 소자에 적용가능한 퓨즈 단절 방법이 절실히 요청되고 있는 실정이다.Therefore, there is an urgent need for a fuse disconnection method applicable to a highly integrated device.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 레이저 빔에 의한 손상을 방지하는 퓨즈 단절 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a fuse disconnection method for preventing damage caused by a laser beam.
본 발명의 또 다른 목적은 고집적화되는 소자에 적용가능한 퓨즈 단절 방법을 제공하는 데 있다.It is still another object of the present invention to provide a fuse disconnection method applicable to a highly integrated device.
도 1은 종래 기술에 따라 비정질 유전체가 삽입된 것을 도시한 단면도이고,1 is a cross-sectional view showing an amorphous dielectric is inserted according to the prior art,
도 2는 본 발명에 따라 퓨즈가 단절된 것을 보여주는 금속배선의 상면도이다.Figure 2 is a top view of a metallization showing that the fuse is blown in accordance with the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 플라즈마를 이용하여 단락시키고자 하는 금속배선의 일부분을 식각하는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized by etching a part of the metal wiring to be short-circuited using plasma.
이 때 플라즈마로 식각하기 전에는, 식각하고자 하는 부분만을 노출시키고 나머지 부분을 덮는 감광막 패턴을 형성한 후, 감광막 패턴을 마스크로 하여 플라즈마 식각하는 것이 바람직하다.At this time, before etching with plasma, it is preferable to form only a portion to be etched and to form a photoresist pattern covering the remaining portion, and then plasma etching using the photoresist pattern as a mask.
이하, 본 발명에 따른 퓨즈 단절 방법에 대해 상세히 설명한다.Hereinafter, a fuse disconnection method according to the present invention will be described in detail.
도 2는 본 발명에 따라 퓨즈가 단절된 것을 보여주는 금속배선의 상면도이다. 여기서 빗금친 부분으로 표시한 하부 금속배선(11)은 비아홀(12)을 통해 상부 금속배선(13)과 연결되어 있으며, 플라즈마에 의해 식각되어 퓨즈 단절된 부분(14a, 14b)은 검은색으로 표시되어 있다.Figure 2 is a top view of a metallization showing that the fuse is blown in accordance with the present invention. Here, the lower metal wiring 11 marked as hatched is connected to the upper metal wiring 13 through the via hole 12, and the portions 14a and 14b which are etched by the plasma and blown off are marked in black. have.
이 때 퓨즈 단절은 하부 금속배선(11)이나 상부 금속배선(12)을 차단시키는 단절선(14a)으로 이루어질 수도 있고, 또는 하부 금속배선(11)과 상부금속배선(12)이 중첩되는 부분에서 원모양으로 상부금속배선 및 그 하부 비아홀의 적어도 일부를 식각하는 단절홀(14b)로 이루어질 수도 있다.In this case, the disconnection of the fuse may be made of a disconnection line 14a that blocks the lower metal line 11 or the upper metal line 12, or at a portion where the lower metal line 11 and the upper metal line 12 overlap. It may be made of a disconnect hole 14b for etching at least a portion of the upper metal wiring and the lower via hole in a circular shape.
이와 같이 플라즈마로 단락시키고자 하는 영역을 식각하기 전에, 식각하고자 하는 영역만을 노출시키고 나머지 영역은 보호하도록 감광막 패턴을 형성하고, 그 감광막 패턴을 마스크로 하여 플라즈마 식각을 수행한다.As described above, before etching the region to be short-circuited with plasma, a photoresist pattern is formed to expose only the region to be etched and protect the remaining region, and plasma etching is performed using the photoresist pattern as a mask.
플라즈마 식각으로 단락시키고자 하는 영역의 금속 배선을 제거하여 퓨즈를 단절시킨 다음에는, 진공을 유지한 상태에서 다른 챔버로 이동하여 인시튜(in-situ)로 H2O 및 O2가스를 이용하여 감광막을 제거한다.After removing the metal wiring in the area to be shorted by plasma etching, the fuse is disconnected, and then moved to another chamber while maintaining the vacuum, using H 2 O and O 2 gas in-situ. Remove the photoresist.
감광막 제거 후에는 금속 배선 및 감광막 제거 공정 중에 발생한 부산물인 폴리머를 습식식각으로 제거함으로써, 제거된 금속배선의 내부에 이물질이 남지 않도록 한다.After removing the photoresist layer, the polymer, which is a by-product generated during the metal wiring and the photoresist removal process, is removed by wet etching so that no foreign matter remains inside the removed metal interconnection.
상술한 바와 같이, 본 발명에서는 플라즈마 식각으로 단절시키고자 하는 금속배선의 영역을 제거하기 때문에, 종래 레이저를 이용한 경우에 비해 다이 크기가 감소하고 이로써 생산 가능한 다이수가 증가하는 효과가 있다. 즉, 플라즈마 식각을 이용하면 레이저를 이용한 종래에 비해 더욱 미세한 소자에도 적용하는 것이 가능해지는 효과가 있다.As described above, in the present invention, since the area of the metal wiring to be disconnected by plasma etching is removed, the die size is reduced and the number of dies that can be produced is increased as compared with the conventional laser. That is, using plasma etching has an effect that can be applied to a finer device than the conventional laser.
또한, 플라즈마 식각을 이용하면 기본적인 회로 구성 위에 다수 개의 단절선 또는 단절홀 패턴을 형성함으로써, 소비자가 원하는 다양한 회로 구성을 할 수 있으며 따라서 다양한 디자인의 소자를 제조하는 효과가 있다.In addition, by using plasma etching, by forming a plurality of disconnection lines or disconnection hole patterns on the basic circuit configuration, various circuit configurations desired by the consumer can be achieved, and thus, devices of various designs can be manufactured.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0031709A KR100467777B1 (en) | 2002-06-05 | 2002-06-05 | Method of fuse disconnection |
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| Application Number | Priority Date | Filing Date | Title |
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| KR10-2002-0031709A KR100467777B1 (en) | 2002-06-05 | 2002-06-05 | Method of fuse disconnection |
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| Publication Number | Publication Date |
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| KR20030093832A KR20030093832A (en) | 2003-12-11 |
| KR100467777B1 true KR100467777B1 (en) | 2005-01-24 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS645032A (en) * | 1987-06-26 | 1989-01-10 | Nec Corp | Manufacture of semiconductor device |
| JPH09312342A (en) * | 1996-05-22 | 1997-12-02 | Advantest Corp | Memory repair method, and electron beam memory repair device where the memory repair method is applicable, and memory redundant circuit |
| JPH1126589A (en) * | 1997-07-02 | 1999-01-29 | Sony Corp | Manufacture of semiconductor device |
| JPH11145301A (en) * | 1997-11-13 | 1999-05-28 | Toshiba Corp | Semiconductor device, its manufacture and defective bit relieving system |
-
2002
- 2002-06-05 KR KR10-2002-0031709A patent/KR100467777B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS645032A (en) * | 1987-06-26 | 1989-01-10 | Nec Corp | Manufacture of semiconductor device |
| JPH09312342A (en) * | 1996-05-22 | 1997-12-02 | Advantest Corp | Memory repair method, and electron beam memory repair device where the memory repair method is applicable, and memory redundant circuit |
| JPH1126589A (en) * | 1997-07-02 | 1999-01-29 | Sony Corp | Manufacture of semiconductor device |
| JPH11145301A (en) * | 1997-11-13 | 1999-05-28 | Toshiba Corp | Semiconductor device, its manufacture and defective bit relieving system |
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| KR20030093832A (en) | 2003-12-11 |
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