KR100449034B1 - semiconductor package and its manufacturing method - Google Patents
semiconductor package and its manufacturing method Download PDFInfo
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- KR100449034B1 KR100449034B1 KR10-1999-0056412A KR19990056412A KR100449034B1 KR 100449034 B1 KR100449034 B1 KR 100449034B1 KR 19990056412 A KR19990056412 A KR 19990056412A KR 100449034 B1 KR100449034 B1 KR 100449034B1
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- semiconductor chip
- input
- film
- double
- bond
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 160
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000002390 adhesive tape Substances 0.000 claims abstract description 23
- 239000008393 encapsulating agent Substances 0.000 claims description 10
- 239000011521 glass Substances 0.000 claims description 8
- 230000004927 fusion Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims 2
- 239000010408 film Substances 0.000 description 36
- 238000003384 imaging method Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
이 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, CCD용 반도체칩을 탑재한 반도체패키지에서 그 패키지의 크기를 반도체칩의 크기에 가깝게 하기 위해, 상면에 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 저면과 상기 반도체칩의 상면중 입출력패드 근방에 접착된 양면접착테이프와; 필름을 기본층으로 그 저면에, 상기 반도체칩의 입출력패드에 접속되는 동시에 양면접착테이프에 접착되는 다수의 본드핑거가 형성되고, 상기 본드핑거로부터 연장되어서는 패턴이 형성되며, 상기 패턴의 단부에는 상기 반도체칩 저면의 양면접착테이프에 접착되는 동시에 필름 저면으로 노출된 랜드가 형성되어 이루어진 써킷테이프와; 상기 써킷테이프의 필름 저면으로 노출된 랜드에 융착된 도전성 볼을 포함하여 이루어진 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, comprising: a semiconductor chip having a plurality of input / output pads formed on an upper surface thereof in order to make the size of the package close to the size of the semiconductor chip in a semiconductor package equipped with a CCD semiconductor chip; A double-sided adhesive tape bonded to a bottom surface of the semiconductor chip and a top surface of the semiconductor chip in the vicinity of an input / output pad; On the bottom of the film as a base layer, a plurality of bond fingers are formed which are connected to the input / output pads of the semiconductor chip and are bonded to the double-sided adhesive tape, and a pattern is formed extending from the bond fingers. A circuit tape bonded to the double-sided adhesive tape of the bottom surface of the semiconductor chip and formed with lands exposed to the bottom surface of the film; It characterized in that it comprises a conductive ball fused to the land exposed to the film bottom surface of the circuit tape.
Description
본 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 보다 상세하게 설명하면 CCD용 반도체칩을 탑재한 반도체패키지에서 그 패키지의 크기를 반도체칩의 크기에 가깝게 한 칩싸이즈화한 반도체패키지 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same. More specifically, in a semiconductor package equipped with a CCD semiconductor chip, a chip sized semiconductor package having a size close to that of a semiconductor chip and a method of manufacturing the same It is about.
통상 CCD는 Charge Coupled Devices의 약어로 반도체 소자의 일종인 전하결합 소자를 말하며 하나의 소자로부터 인접한 다른 소자로 전하를 전송할 수 있는 소자를 말한다. 텔레비전 카메라의 영상신호 계통에서 피사체의 빛은 렌즈를 통과한 후 색분해 광학계에 의해 3원색으로 분해돼 각각 촬상 디바이스의 수광면에 결상되는데 그 상을 소자내에서 전자적으로 주사해 전기신호로 변환시켜 출력하는 소자가 고체촬상소자이다. 이러한 CCD의 응용분야는 촬상디바이스, 대용량메모리, 아날로그 신호처리의 세가지이며 구조적으로는 MOS집적회로이기 때문에 MOS프로세스 기술을 사용해 고집적회로(LSI)화도 용이하다. CCD는 특히 자기주사 기능과 광전변환 기능을 함께 갖추고 있기 때문에 촬상디바이스에 주로 응용되며 일차원의 라인센서와 이차원의 에이리어 센서가 있으며 그 화소수는 일반적으로 라인센서는 1,500화소, 에이리어센서는 512×320화소의 것이 있다.In general, CCD is an abbreviation of Charge Coupled Devices and refers to a charge coupled device, which is a kind of semiconductor device, and a device capable of transferring charges from one device to another adjacent device. In the video signal system of the television camera, the light of the subject passes through the lens and is decomposed into three primary colors by color separation optical systems, and is then formed on the light receiving surface of the imaging device. The device to be used is a solid state imaging device. There are three application fields of CCD such as imaging device, large-capacity memory, and analog signal processing, and because the structure is MOS integrated circuit, it is easy to make LSI using MOS process technology. CCD is mainly applied to imaging device because it has both self-scanning function and photoelectric conversion function, and there are one-dimensional line sensor and two-dimensional area sensor, and the number of pixels is generally 1,500 pixels for line sensor and 512 for area sensor. There is a thing of x320 pixels.
상기한 CCD 소자가 다수 형성된 CCD용 반도체칩을 탑재한 반도체패키지는 통상 그 반도체칩이 외부의 빛을 수광할 수 있도록 반도체칩의 상면에 글래스가 위치되어 있으며, 이러한 종래의 반도체패키지(100')를 도1a 및 도1b를 참조하여 간단히 설명하면 다음과 같다.In a semiconductor package equipped with a CCD semiconductor chip having a plurality of CCD elements, glass is usually placed on a top surface of the semiconductor chip so that the semiconductor chip can receive external light. Such a conventional semiconductor package 100 ' It will be described briefly with reference to Figures 1a and 1b as follows.
먼저 일면에 다수의 입출력패드(2a)가 형성된 반도체칩(2)이 구비되어 있다. 상기 반도체칩(2)의 저면에는 접착제에 의해 회로기판(10)이 접착되어 있다. 상기 회로기판(10)은 수지층(11)을 중심으로 상면에는 다수의 본드핑거(12)를 포함하는 회로패턴이 형성되어 있고, 저면에는 다수의 랜드(13)를 포함하는 회로패턴이 형성되어 있으며, 상기 상,하면의 회로패턴은 도전성 비아홀(14)로 상호 연결되어 있다. 또한 상기 상면의 본드핑거(12) 및 저면의 랜드(13)를 제외한 모든 회로패턴은 솔더마스크(15) 등으로 코팅되어 있다.First, a semiconductor chip 2 having a plurality of input / output pads 2a formed on one surface thereof is provided. The circuit board 10 is adhered to the bottom of the semiconductor chip 2 by an adhesive. In the circuit board 10, a circuit pattern including a plurality of bond fingers 12 is formed on an upper surface of the resin layer 11, and a circuit pattern including a plurality of lands 13 is formed on a bottom surface of the circuit board 10. The upper and lower circuit patterns are interconnected by conductive via holes 14. In addition, all circuit patterns except for the bond finger 12 on the upper surface and the land 13 on the lower surface are coated with a solder mask 15 or the like.
한편, 상기 반도체칩(2)의 입출력패드(2a)와 상기 회로기판(10)의 본드핑거(12)는 도전성와이어(20)에 의해 전기적으로 접속되어 있다.Meanwhile, the input / output pad 2a of the semiconductor chip 2 and the bond finger 12 of the circuit board 10 are electrically connected by conductive wires 20.
또한, 상기 반도체칩(2)의 외주연 즉, 본드핑거(12)의 외주연에는 회로기판(10)의 상면에 대략 상기 도전성와이어(20)의 루프 높이보다 높게 댐(30)이 형성되어 있으며, 상기 댐(30)에는 반도체칩(2)으로 외부의 빛이 수광될 수 있도록 투명체의 글래스(40)가 접착되어 있다. 더불어 상기 회로기판(10)의 저면인 랜드(13)에는 다수의 도전성볼(60)이 융착되어 있다.In addition, a dam 30 is formed on the outer circumference of the semiconductor chip 2, that is, on the outer circumference of the bond finger 12, and is substantially higher than the loop height of the conductive wire 20 on the upper surface of the circuit board 10. The glass 30 of the transparent body is bonded to the dam 30 so that external light can be received by the semiconductor chip 2. In addition, a plurality of conductive balls 60 are fused to the land 13, which is a bottom surface of the circuit board 10.
그러나 이러한 반도체패키지는 그 반도체칩의 크기에 비해 반도체패키지의 크기가 절대적으로 크다. 즉, 상기 반도체칩을 중심으로 그 하면에는 다층 구조의 회로기판이 위치되어 있고, 또한 상면에는 와이어 루프 높이보다 큰 댐이 형성되어 있음으로써 그 두께가 크고, 또한 반도체칩의 외주연으로 회로기판이 확장되어 있으므로 반도체칩의 크기에 비해 전체적인 반도체패키지의 넓이도 크다.However, such a semiconductor package is absolutely larger than the size of the semiconductor chip. That is, a circuit board having a multilayer structure is located on the lower surface of the semiconductor chip, and a dam larger than the height of the wire loop is formed on the upper surface of the semiconductor chip, and the circuit board is formed on the outer circumference of the semiconductor chip. Since it is expanded, the overall semiconductor package is larger than the size of the semiconductor chip.
이와 같이 반도체패키지의 크기가 커지게 되면 결국 마더보드에의 실장밀도가 저하되고 이는 상기 반도체패키지를 사용한 전자제품의 크기 축소에 한계가 있음을 의미한다.As the size of the semiconductor package increases, the mounting density on the motherboard eventually decreases, which means that there is a limit in size reduction of electronic products using the semiconductor package.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, CCD용 반도체칩을 탑재한 반도체패키지에서 그 패키지의 크기를 반도체칩의 크기에 가깝게 한 칩싸이즈화한 반도체패키지 및 그 제조 방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned problems, and in a semiconductor package equipped with a CCD semiconductor chip, a chip sized semiconductor package having a size close to that of a semiconductor chip, and a manufacturing method thereof To provide.
도1a 및 도1b는 종래의 반도체패키지를 도시한 단면도이다.1A and 1B are cross-sectional views showing a conventional semiconductor package.
도2a 및 도2b는 본 발명의 제1,2실시예에 의한 반도체패키지를 도시한 단면도이다.2A and 2B are cross-sectional views showing semiconductor packages according to the first and second embodiments of the present invention.
도3a 내지 도3e는 본 발명에 의한 반도체패키지의 제조 방법을 도시한 순차 설명도이다.3A to 3E are sequential explanatory diagrams showing a method of manufacturing a semiconductor package according to the present invention.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
100,101; 본 발명에 의한 반도체패키지100,101; Semiconductor package according to the present invention
2; 반도체칩 2a; 입출력패드2; Semiconductor chip 2a; I / O pad
10; 써킷테이프 11; 제1필름, 필름10; Circuit tape 11; 1st film, film
12; 본드핑거 13; 랜드12; Bondfinger 13; rand
14; 패턴 15; 제2필름14; Pattern 15; 2nd film
16; 관통구 20; 양면접착테이프16; Through hole 20; Double sided adhesive tape
30; 도전성볼 40; 글래스30; Conductive ball 40; Glass
50; 봉지재50; Encapsulant
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지에 의하면, 상면에 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 저면과 상기 반도체칩의 상면중 입출력패드 근방에 접착된 양면접착테이프와; 필름을 기본층으로 그 저면에, 상기 반도체칩의 입출력패드에 접속되는 다수의 본드핑거가 형성되고, 상기 본드핑거로부터 연장되어서는 패턴이 형성되며, 상기 패턴의 단부에는 상기 반도체칩 저면의 양면접착테이프에 접착되는 동시에 필름 저면으로 노출된 랜드가 형성되어 이루어진 써킷테이프와; 상기 써킷테이프의 필름 저면으로 노출된 랜드에 융착된 도전성볼을 포함하여 이루어진 것을 특징으로 한다.According to the semiconductor package according to the present invention for achieving the above object, a semiconductor chip having a plurality of input and output pads on the upper surface; A double-sided adhesive tape bonded to a bottom surface of the semiconductor chip and a top surface of the semiconductor chip in the vicinity of an input / output pad; On the bottom of the film as a base layer, a plurality of bond fingers connected to the input / output pads of the semiconductor chip are formed, and patterns extending from the bond fingers are formed, and both ends of the bottom surface of the semiconductor chip are formed at the ends of the patterns. A circuit tape formed by adhering to the tape and having lands exposed to the bottom of the film; It characterized in that it comprises a conductive ball fused to the land exposed to the film bottom surface of the circuit tape.
상기 반도체칩의 입출력패드 상에 위치되는 필름상에는 반도체칩의 상면을 덮을 수 있도록 투명체의 글래스가 더 접착될 수 있다.The glass of the transparent body may be further bonded on the film positioned on the input / output pad of the semiconductor chip to cover the top surface of the semiconductor chip.
상기 반도체칩의 입출력패드 상에 위치되는 필름은 반도체칩의 상면 전체를 덮을 수 있도록 연장되어 형성될 수도 있다. 이때, 상기 필름은 투명체로 형성함이 바람직하다.The film positioned on the input / output pad of the semiconductor chip may be formed to extend to cover the entire upper surface of the semiconductor chip. In this case, the film is preferably formed of a transparent body.
상기 반도체칩의 입출력패드와 대응하는 영역의 필름에는 관통구가 형성되고, 상기 관통구는 봉지재로 봉지될 수 있다.A through hole may be formed in the film of the region corresponding to the input / output pad of the semiconductor chip, and the through hole may be sealed with an encapsulant.
상기 양면접착테이프는 반도체칩의 측면에도 형성되어 써킷테이프가 접착될 수도 있다.The double-sided adhesive tape is also formed on the side of the semiconductor chip may be bonded to the circuit tape.
또한 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지의 제조 방법은 필름을 기본층으로 그 저면에, 반도체칩의 입출력패드에 접속되도록 다수의 본드핑거가 형성되고, 상기 본드핑거로부터 연장되어서는 패턴이 형성되며, 상기 패턴의 단부에는 상면으로 노출되어 랜드가 형성된 가요성의 써킷테이프를 제공하는 단계와; 상면에 다수의 입출력패드가 형성된 반도체칩을 제공하는 단계와; 상기 반도체칩의 저면 및 상면의 입출력패드 근방에 양면접착테이프를 접착하는 단계와; 상기 써킷테이프가 상기 반도체칩의 상면, 측면 및 저면에 근접하도록 벤딩하되, 상기 써킷테이프의 본드핑거는 상기 반도체칩의 입출력패드에 접속되도록 하는 동시에 양면접착테이프에 의해 접착되도록 하고, 상기 써킷테이프의 랜드는 반도체칩의 저면에 위치하도록 접착하는 단계와; 상기 써킷테이프의 랜드에 도전성볼을 융착하는 단계를 포함하여 이루어진 것을 특징으로 한다.In addition, in order to achieve the above object, in the method of manufacturing a semiconductor package according to the present invention, a plurality of bond fingers are formed on the bottom of the film as a base layer and connected to the input / output pads of the semiconductor chip, and extend from the bond fingers. Providing a flexible circuit tape having a pattern formed thereon and exposed to an upper surface at an end of the pattern, the land having a land formed thereon; Providing a semiconductor chip having a plurality of input / output pads formed on an upper surface thereof; Bonding a double-sided adhesive tape to the input / output pads on the bottom and top of the semiconductor chip; The circuit tape is bent so as to be close to the top, side, and bottom of the semiconductor chip, wherein the bond finger of the circuit tape is connected to the input / output pad of the semiconductor chip and bonded by a double-sided adhesive tape, and Bonding the lands to be located on the bottom of the semiconductor chip; And fusion bonding conductive balls to lands of the circuit tape.
상기 써킷테이프 제공 단계는 상기 반도체칩의 입출력패드와 대응하고 본드핑거가 형성된 영역의 필름을 제거하여 관통구를 형성할 수도 있다. 이때, 상기 본드핑거와 반도체칩의 입출력패드를 접속한 후에는 상기 써킷테이프의 관통구에 봉지재를 충진함이 바람직하다.In the circuit tape providing step, a through hole may be formed by removing a film in a region corresponding to an input / output pad of the semiconductor chip and in which a bond finger is formed. In this case, after the bond finger is connected to the input / output pad of the semiconductor chip, the sealing material is preferably filled in the through hole of the circuit tape.
상기 써킷테이프 제공 단계는 반도체칩의 상면 전체를 덮을 수 있도록 투명체의 필름을 더 연장하여 형성할 수 있다.In the circuit tape providing step, the film of the transparent body may be further extended to cover the entire upper surface of the semiconductor chip.
상기 반도체칩의 상면에 위치하는 써킷테이프에는 반도체칩의 상면 전체를 덮을 수 있도록 투명체의 글래스를 부착하는 단계를 더 포함할 수도 있다.The circuit tape positioned on the upper surface of the semiconductor chip may further include attaching a glass of the transparent body to cover the entire upper surface of the semiconductor chip.
상기와 같이 하여 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 반도체칩의 상면, 저면 및 측면 전체를 본드핑거, 패턴 및 랜드 등이 형성된 써킷테이프를 밀착시켜 부착시킴으로써 반도체패키지의 크기가 상기 반도체칩의 크기에 가깝게 칩싸이즈화 된다.According to the semiconductor package according to the present invention and the manufacturing method as described above, the size of the semiconductor package is reduced by attaching the upper, bottom and side surfaces of the semiconductor chip in close contact with a circuit tape on which bond fingers, patterns, and lands are formed. Chip sized close to chip size.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도2a 및 도2b는 본 발명의 제1,2실시예에 의한 반도체패키지(100,101)를 도시한 단면도이다.2A and 2B are cross-sectional views showing semiconductor packages 100 and 101 according to the first and second embodiments of the present invention.
먼저 도2a의 반도체패키지(100)를 참조하면, 상면에 다수의 입출력패드(2a)가 형성된 반도체칩(2)이 구비되어 있고, 상기 반도체칩(2)의 저면과 상면의 입출력패드(2a) 근방에는 양면접착테이프(20)가 접착되어 있다.First, referring to the semiconductor package 100 of FIG. 2A, a semiconductor chip 2 having a plurality of input / output pads 2a formed on an upper surface thereof is provided, and an input / output pad 2a on a bottom surface and an upper surface of the semiconductor chip 2 is provided. In the vicinity, the double-sided adhesive tape 20 is bonded.
상기 반도체칩(2)의 상면, 측면 및 저면에는 일체의 써킷테이프(10)가 부착되어 있으며 이는 다음과 같이 구성되어 있다.An integrated circuit tape 10 is attached to the top, side, and bottom surfaces of the semiconductor chip 2, which is configured as follows.
즉, 상기 반도체칩(2)의 상면, 측면 및 저면을 덮을 수 있는 정도의 크기로 제1필름(11)이 구비되어 있고, 상기 제1필름(11)의 표면에는 상기 반도체칩(2)의 입출력패드(2a)와 접속되는 본드핑거(12)가, 상기 본드핑거(12)에 연장되어서는 패턴(14)이, 상기 패턴(14)에 연장되어서는 랜드(13)가 형성되어 있다.That is, the first film 11 is provided to the extent that it can cover the top, side, and bottom of the semiconductor chip 2, the surface of the first film 11 of the semiconductor chip 2 The bond finger 12 connected to the input / output pad 2a extends from the bond finger 12 to the pattern 14, and the land 13 extends from the pattern 14.
또한, 상기 본드핑거(12)를 제외한 패턴(14) 및 랜드(13)의 표면은 제2필름(15)이 감싸고 있으며, 이 제2필름(15)이 상기 반도체칩(2) 저면 및 상면에 형성된 양면접착테이프(20)에 접착되어 있다.In addition, the surface of the pattern 14 and the land 13 except for the bond finger 12 is surrounded by the second film 15, and the second film 15 is formed on the bottom and top surfaces of the semiconductor chip 2. It is bonded to the formed double-sided adhesive tape 20.
더불어, 상기 본드핑거(12)가 형성된 영역의 제1필름(11)은 일정 크기로 관통되어 관통구(16)가 형성되어 있으며, 상기 랜드(13)는 제1필름(11)을 통해 외부로 노출되어 있다.In addition, the first film 11 in the region where the bond finger 12 is formed is penetrated to a predetermined size to form a through hole 16, and the land 13 is moved to the outside through the first film 11. Exposed
여기서, 상기 본드핑거(12), 패턴(14) 및 랜드(13)는 모두 구리 또는 얼로이 42로 형성된 박막 형태이다. 또한 상기 본드핑거(12)에는 반도체칩(2)의 입출력패드(2a)와의 접속이 양호하도록 은(Ag)이 도금되어 있고, 상기 랜드(13)에는 차후 도전성볼이 양호하게 융착되도록 금(Au), 은(Ag), 니켈(Ni) 및 팔라디엄(Pd) 등이 도금되어 있다.Here, the bond finger 12, the pattern 14 and the land 13 are all formed of a thin film formed of copper or alloy 42. In addition, the bond finger 12 is plated with silver (Ag) so as to have a good connection with the input / output pad 2a of the semiconductor chip 2, and the land 13 has a gold (Au) in order to fusion well. ), Silver (Ag), nickel (Ni), palladium (Pd) and the like are plated.
한편, 상기 제1필름(11)은 반도체칩(2) 상면 전체를 덮을 수 있도록 연장되어 있으며, 상기 제1필름(11)은 반도체칩(2)이 빛을 용이하게 수광할 수 있도록 투명체로 형성되어 있다.Meanwhile, the first film 11 extends to cover the entire upper surface of the semiconductor chip 2, and the first film 11 is formed of a transparent body so that the semiconductor chip 2 can easily receive light. It is.
상기 써킷테이프(10)의 관통구(16)에는 봉지재(50)가 충진되어 상기 본드핑거(12) 및 반도체칩(2)의 입출력패드(2a) 등을 외부 환경으로부터 보호할 수 있도록 되어 있으며, 상기 봉지재(50)로서는 액상 봉지재가 바람직하다.The through hole 16 of the circuit tape 10 is filled with an encapsulant 50 to protect the bond finger 12 and the input / output pad 2a of the semiconductor chip 2 from the external environment. As the encapsulant 50, a liquid encapsulant is preferable.
상기 써킷테이프(10)의 제1필름(11) 저면으로 노출된 랜드(13)에는 솔더볼과 같은 도전성볼(30)이 융착되어 있음으로써 차후 마더보드에 실장 가능하게 되어 있다.The land 13 exposed to the bottom surface of the first film 11 of the circuit tape 10 is welded with a conductive ball 30 such as a solder ball so that it can be mounted on the motherboard later.
상기 반도체칩(2)의 측면에도 양면접착테이프(20)를 개재하여 상기 써킷테이프(10)가 반도체칩(2)의 측면에 밀착되도록 할 수도 있다.The circuit tape 10 may be in close contact with the side surface of the semiconductor chip 2 through the double-sided adhesive tape 20 on the side surface of the semiconductor chip 2.
다음으로 도2b의 반도체패키지(101)를 참조하면, 상면에 다수의 입출력패드(2a)가 형성된 반도체칩(2)이 구비되어 있고, 상기 반도체칩(2)의 저면, 측면 및 상면의 입출력패드(2a) 근방에는 양면접착테이프(20)가 접착되어 있다.Next, referring to the semiconductor package 101 of FIG. 2B, a semiconductor chip 2 having a plurality of input / output pads 2a formed on an upper surface thereof is provided, and the input / output pads of the bottom, side, and top surfaces of the semiconductor chip 2 are provided. The double-sided adhesive tape 20 is bonded in the vicinity of (2a).
상기 반도체칩(2)의 상면 일정 영역(입출력패드(2a)의 근방), 측면 및 저면에는 일체의 써킷테이프(10)가 부착되어 있으며 이는 다음과 같이 구성되어 있다.An integrated circuit tape 10 is attached to a predetermined upper surface of the semiconductor chip 2 (in the vicinity of the input / output pad 2a), the side surface, and the bottom surface, and is configured as follows.
즉, 상기 반도체칩(2)의 상면 일정영역(입출력패드(2a) 근방), 측면 및 저면을 감쌀 수 있는 정도의 크기로 필름(11)이 구비되어 있고, 상기 필름(11)의 표면에는 상기 반도체칩(2)의 입출력패드(2a)와 접속되는 본드핑거(12)가, 상기 본드핑거(12)에 연장되어서는 패턴(14)이, 상기 패턴(14)에 연장되어서는 랜드(13)가 형성되어 있다.That is, the film 11 is provided in such a size as to cover a certain region (near the I / O pad 2a), the side surface and the bottom surface of the semiconductor chip 2, and the surface of the film 11 When the bond finger 12 connected to the input / output pad 2a of the semiconductor chip 2 is extended to the bond finger 12, the pattern 14 is extended to the pattern 14, and the land 13 is extended to the pattern 14. Is formed.
상기 본드핑거(12), 패턴(14) 및 랜드(13)는 모두 반도체칩(2)의 표면에 부착된 양면접착테이프(20)에 직접 접착되어 있으며, 상기 랜드(13)는 필름(11) 저면으로 오픈되어 있다. 또한 상기 필름(11) 저면으로 오픈된 랜드(13)에는 다수의 도전성볼(30)이 융착되어 있다.The bond finger 12, the pattern 14, and the land 13 are all directly bonded to the double-sided adhesive tape 20 attached to the surface of the semiconductor chip 2, and the land 13 is a film 11. It is open to the bottom. In addition, a plurality of conductive balls 30 are fused to lands 13 opened to the bottom surface of the film 11.
한편, 상기 써킷테이프(10)는 반도체칩(2)의 입출력패드(2a) 근방에서 측면을 따라 저면으로 연장되어 있기 때문에, 반도체칩(2)의 상면이 외부로 오픈되어 있다. 따라서, 상기 반도체칩(2)의 상면을 덮을 수 있도록 투명체의 글래스(40)가상기 써킷테이프(10)상에 접착되어 있다.On the other hand, since the circuit tape 10 extends from the vicinity of the input / output pad 2a of the semiconductor chip 2 to the bottom along the side surface, the upper surface of the semiconductor chip 2 is opened to the outside. Therefore, the glass 40 of the transparent body is adhered on the circuit tape 10 so as to cover the upper surface of the semiconductor chip 2.
도3a 내지 도3e는 본 발명에 의한 반도체패키지(100)의 제조 방법을 도시한 순차 설명도이다.3A to 3E are sequential explanatory diagrams showing the manufacturing method of the semiconductor package 100 according to the present invention.
먼저 반도체칩(2)의 상면, 측면 및 저면 전체를 덮을 수 있는 크기로 가요성의 제1필름(11)이 구비되고, 그 저면에는 반도체칩(2)의 입출력패드(2a)에 접속되도록 다수의 본드핑거(12)가 형성되고, 상기 본드핑거(12)로부터 연장되어서는 패턴(14)이 형성되며, 상기 패턴(14)의 단부에는 상면으로 오픈된 다수의 랜드(13)가 형성되어 있는 써킷테이프(10)를 제공한다.(도3a 참조)First, a flexible first film 11 is provided to cover the entire top, side, and bottom surfaces of the semiconductor chip 2, and a plurality of flexible first films 11 are connected to the bottom of the semiconductor chip 2 so as to be connected to the input / output pads 2a of the semiconductor chip 2. A bond finger 12 is formed, and a pattern 14 is formed by extending from the bond finger 12, and a circuit is formed at the end of the pattern 14 in which a plurality of lands 13 are opened. Provide tape 10 (see Figure 3a).
여기서, 상기 패턴(14) 및 랜드(13) 저면에는 가요성의 제2필름(15)이 구비될 수 있고, 상기 본드핑거(12)가 위치된 제1필름(11)에는 관통구(16)가 구비되어 본드핑거(12)가 외부로 노출되도록 할 수 있다. 또한, 상기 제1필름(11) 1층만 형성된 영역은 차후 반도체칩(2)의 상면 전체를 덮게 되며, 본드핑거(12)는 반도체칩(2)의 입출력패드(2a)에 대응되고, 패턴(14)은 대체로 반도체칩(2)의 측면에 대응되며, 랜드(13)는 반도체칩(2)의 저면 전체에 대응하게 된다. 물론, 상기 반도체칩(2)의 상면에 위치되는 제1필름(11)은 투명체로 제조하여 반도체칩(2)이 외부의 빛을 용이하게 수광할 수 있도록 한다.Here, the second film 15 may be provided on the bottom surface of the pattern 14 and the land 13, and the through hole 16 may be provided on the first film 11 on which the bond finger 12 is located. The bond finger 12 may be provided to be exposed to the outside. In addition, the region where only one layer of the first film 11 is formed may cover the entire upper surface of the semiconductor chip 2 later, and the bond finger 12 may correspond to the input / output pad 2a of the semiconductor chip 2, and the pattern ( 14 generally corresponds to the side surface of the semiconductor chip 2, and the land 13 corresponds to the entire bottom surface of the semiconductor chip 2. Of course, the first film 11 positioned on the upper surface of the semiconductor chip 2 is made of a transparent body so that the semiconductor chip 2 can easily receive external light.
한편, 상기 써킷테이프(10)는 도2b에서와 같은 반도체패키지(101)를 제공하기 위해 필름(11) 상에 본드핑거(12), 패턴(14) 및 외부로 오픈된 랜드(13)가 형성되어, 반도체칩(2)의 입출력패드(2a) 근방, 측면 및 저면만을 덮을 수 있도록 제조될 수도 있다.On the other hand, the circuit tape 10 is formed with a bond finger 12, a pattern 14 and an open land 13 on the film 11 to provide the semiconductor package 101 as shown in Figure 2b As a result, the semiconductor chip 2 may be manufactured so as to cover only the vicinity, the side surfaces, and the bottom surface of the input / output pad 2a of the semiconductor chip 2.
계속해서, 상면에 다수의 입출력패드(2a)가 형성된 반도체칩(2)을 제공하되, 상기 반도체칩(2)의 저면 및 상면의 입출력패드(2a) 근방에는 양면접착테이프(20)를 접착하여 제공한다.(도3b 참조)Subsequently, a semiconductor chip 2 having a plurality of input / output pads 2a formed on the upper surface thereof is provided, and a double-sided adhesive tape 20 is adhered to the lower surface of the semiconductor chip 2 and the vicinity of the input / output pad 2a on the upper surface thereof. (See Figure 3b).
이어서, 상기 써킷테이프(10)가 상기 반도체칩(2)의 상면, 측면 및 저면에 근접하도록 벤딩하되, 상기 써킷테이프(10)의 본드핑거(12)가 상기 반도체칩(2)의 입출력패드(2a)에 접속되도록 하는 동시에 제2필름(15)은 상기 양면접착테이프에 의해 접착되도록 하고, 또한 상기 써킷테이프(10)의 랜드(13)는 반도체칩(2)의 저면에 접착되도록 써킷테이프(10)를 반도체칩(2)의 외주연에 접착시킨다. 물론, 제1필름(11)만 형성된 영역은 반도체칩(2)의 상면 전체에 위치됨으로써 외부의 빛을 상기 반도체칩(2)이 용이하게 수광할 수 있도록 한다.(도3c 참조)Subsequently, the circuit tape 10 is bent to be close to the top, side, and bottom surfaces of the semiconductor chip 2, and the bond fingers 12 of the circuit tape 10 are formed on the input / output pads of the semiconductor chip 2. 2a) and the second film 15 is bonded by the double-sided adhesive tape, and the land 13 of the circuit tape 10 is bonded to the bottom surface of the semiconductor chip 2 by a circuit tape ( 10) is bonded to the outer periphery of the semiconductor chip (2). Of course, the region where only the first film 11 is formed is located on the entire upper surface of the semiconductor chip 2 so that the semiconductor chip 2 can easily receive external light (see FIG. 3C).
이때, 상기 써킷테이프(10)의 본드핑거(12)와 반도체칩(2)의 입출력패드(2a)는 탭(TAB)본딩 또는 리드본딩에 의해 상호 전기적으로 접속함이 바람직하다.At this time, it is preferable that the bond finger 12 of the circuit tape 10 and the input / output pad 2a of the semiconductor chip 2 are electrically connected to each other by tap (TAB) bonding or lead bonding.
이어서, 상기 본드핑거(12)가 위치된 써킷테이프(10)의 관통구(16) 내측을 액상 봉지재(50)와 같은 봉지재(50)를 이용하여 봉합함으로써 외부의 이물질이 침투하지 않토록 한다.(도3d)Subsequently, the inside of the through hole 16 of the circuit tape 10 in which the bond finger 12 is positioned is sealed using an encapsulant 50 such as a liquid encapsulant 50 so that external foreign substances do not penetrate. (Fig. 3d)
한편, 상기 도2b에 도시된 반도체패키지(101)를 제조하기 위해서는, 필름(11)이 상기 반도체칩(2)의 상면 전체를 덮지 않음으로 별도의 글래스(40)를 구비하여 그 반도체칩(2)의 상면에 접착한다.Meanwhile, in order to manufacture the semiconductor package 101 shown in FIG. 2B, the film 11 does not cover the entire upper surface of the semiconductor chip 2, so that a separate glass 40 is provided and the semiconductor chip 2 is provided. Adhere to the top of).
마지막으로 상기 반도체칩(2)의 저면에 위치된 써킷테이프(10)의 랜드(13)에 솔더볼과 같은 다수의 도전성볼(30)을 융착하여 마더보드에 실장가능한 형태가 되도록 한다.(도3e 참조)Finally, a plurality of conductive balls 30 such as solder balls are fused to the lands 13 of the circuit tape 10 located on the bottom surface of the semiconductor chip 2 so as to be mountable on the motherboard (FIG. 3E). Reference)
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다. 예를 들면, 상기 제1,2실시예에서는 반도체칩의 양측면을 덮을 수 있도록 써킷테이프가 구비되었지만, 반도체칩의 4측면을 모두 덮을 수 있는 써킷테이프도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention. For example, in the first and second embodiments, circuit tapes are provided to cover both sides of the semiconductor chip, but circuit tapes covering all four sides of the semiconductor chip may be possible.
따라서, 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 반도체칩의 상면, 저면 및 측면 전체를 본드핑거, 패턴 및 랜드 등이 형성된 써킷테이프를 밀착시켜 부착시킴으로써 반도체패키지의 크기가 상기 반도체칩의 크기에 가깝게 칩싸이즈화 되는 효과가 있다.Therefore, according to the semiconductor package and the method of manufacturing the same according to the present invention, the entire surface of the semiconductor chip, the bottom and the side surface of the semiconductor chip is adhered to the circuit tape on which bond fingers, patterns and lands, etc. are closely adhered to the size of the semiconductor package. It has the effect of chipizing to near size.
Claims (11)
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980068344A (en) * | 1997-02-18 | 1998-10-15 | 황인길 | Chip-Scale Semiconductor Package Using Rigid-Flex Printed Circuit Board and Manufacturing Method Thereof |
| KR19980068343A (en) * | 1997-02-18 | 1998-10-15 | 황인길 | Chip scale semiconductor package using flexible circuit board and manufacturing method thereof |
| JPH10340981A (en) * | 1997-06-09 | 1998-12-22 | Nec Corp | Semiconductor device and manufacture of the semiconductor device |
| KR19990001876U (en) * | 1997-06-23 | 1999-01-15 | 김영환 | Semiconductor package |
| KR19990016047A (en) * | 1997-08-12 | 1999-03-05 | 윤종용 | Tape Circuit Board and Chip Size Semiconductor Chip Package Using the Same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980068344A (en) * | 1997-02-18 | 1998-10-15 | 황인길 | Chip-Scale Semiconductor Package Using Rigid-Flex Printed Circuit Board and Manufacturing Method Thereof |
| KR19980068343A (en) * | 1997-02-18 | 1998-10-15 | 황인길 | Chip scale semiconductor package using flexible circuit board and manufacturing method thereof |
| JPH10340981A (en) * | 1997-06-09 | 1998-12-22 | Nec Corp | Semiconductor device and manufacture of the semiconductor device |
| KR19990001876U (en) * | 1997-06-23 | 1999-01-15 | 김영환 | Semiconductor package |
| KR19990016047A (en) * | 1997-08-12 | 1999-03-05 | 윤종용 | Tape Circuit Board and Chip Size Semiconductor Chip Package Using the Same |
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