KR20010058581A - semiconductor package and its manufacturing method - Google Patents
semiconductor package and its manufacturing method Download PDFInfo
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- KR20010058581A KR20010058581A KR1019990065931A KR19990065931A KR20010058581A KR 20010058581 A KR20010058581 A KR 20010058581A KR 1019990065931 A KR1019990065931 A KR 1019990065931A KR 19990065931 A KR19990065931 A KR 19990065931A KR 20010058581 A KR20010058581 A KR 20010058581A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 137
- 238000004519 manufacturing process Methods 0.000 title description 13
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000011521 glass Substances 0.000 claims abstract description 38
- 239000000853 adhesive Substances 0.000 claims abstract description 13
- 230000001070 adhesive effect Effects 0.000 claims abstract description 13
- 239000008393 encapsulating agent Substances 0.000 claims description 51
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- 239000011347 resin Substances 0.000 claims description 17
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- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- 238000003384 imaging method Methods 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
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- 229910000679 solder Inorganic materials 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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- 238000005452 bending Methods 0.000 description 1
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- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
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- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
- H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
본 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 더욱 상세하게 설명하면 CCD용 반도체칩이 탑재되는 반도체패키지 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package on which a semiconductor chip for a CCD is mounted and a method for manufacturing the same.
통상 CCD는 Charge Coupled Devices의 약어로 반도체 소자의 일종인 전하결합 소자를 말하며 하나의 소자로부터 인접한 다른 소자로 전하를 전송할 수 있는 소자를 말한다. 텔레비전 카메라의 영상신호 계통에서 피사체의 빛은 렌즈를 통과한 후 색분해 광학계에 의해 3원색으로 분해돼 각각 촬상 디바이스의 수광면에 결상되는데 그 상을 소자내에서 전자적으로 주사해 전기신호로 변환시켜 출력하는 소자가 고체촬상소자이다. 이러한 CCD의 응용분야는 촬상디바이스, 대용량메모리, 아날로그 신호처리의 세가지이며 구조적으로는 MOS집적회로이기 때문에 MOS프로세스 기술을 사용해 고집적회로(LSI)화도 용이하다. CCD는 특히 자기주사 기능과 광전변환 기능을 함께 갖추고 있기 때문에 촬상디바이스에 주로 응용되며 일차원의 라인센서와 이차원의 에이리어 센서가 있으며 그 화소수는 일반적으로 라인센서는 1,500화소, 에이리어센서는 512×320화소의 것이 있다.In general, CCD is an abbreviation of Charge Coupled Devices and refers to a charge coupled device, which is a kind of semiconductor device, and a device capable of transferring charges from one device to another adjacent device. In the video signal system of the television camera, the light of the subject passes through the lens and is decomposed into three primary colors by color separation optical systems, and is then formed on the light receiving surface of the imaging device. The device to be used is a solid state imaging device. There are three application fields of CCD such as imaging device, large-capacity memory, and analog signal processing, and because the structure is MOS integrated circuit, it is easy to make LSI using MOS process technology. CCD is mainly applied to imaging device because it has both self-scanning function and photoelectric conversion function, and there are one-dimensional line sensor and two-dimensional area sensor, and the number of pixels is generally 1,500 pixels for line sensor and 512 for area sensor. There is a thing of x320 pixels.
상기한 CCD 소자가 다수 형성된 CCD용 반도체칩을 탑재한 반도체패키지는 통상 그 반도체칩이 외부의 빛을 수광할 수 있도록 반도체칩의 상면에 글래스가 위치되어 있으며, 이러한 종래의 반도체패키지(100')를 도1을 참조하여 간단히 설명하면 다음과 같다.In a semiconductor package equipped with a CCD semiconductor chip having a plurality of CCD elements, glass is usually placed on a top surface of the semiconductor chip so that the semiconductor chip can receive external light. Such a conventional semiconductor package 100 ' 1 will be briefly described as follows.
먼저 다수의 입출력패드(12)가 형성된 CCD용 반도체칩(10)이 구비되어 있고, 상기 CCD용 반도체칩(10)은 회로기판(70)에 형성된 관통공(76)에 위치되어 있다. 상기 회로기판(70)은 중앙에 일정크기로 관통되어 형성된 관통공(76)을 포함하는 수지층(71)을 기본층으로 하여, 상기 수지층(71) 상면에는 본드핑거(72)를 포함하는 회로패턴이, 하면에는 볼랜드(73)를 포함하는 회로패턴이 형성되어 있으며, 상기 상하면의 회로패턴은 도전성비아홀(74)에 의해 상호 연결되어 있다. 또한 상기 본드핑거(72) 및 볼랜드(73)가 오픈되도록 모든 회로패턴이 커버코트(75)로 코팅되어 있으며, 상기 회로기판(70)의 관통공(76) 저면에는 반도체칩(10)이 탑재되어 위치될 수 있도록 지지부재(80)가 접착되어 있다. 상기 반도체칩(10)의 입출력패드(12)와 회로기판(70)의 본드핑거(72)는 도전성와이어(30)로 본딩되어 있다. 상기 반도체칩(10)의 상면에는 수광영역이 형성되어 있으며, 상기 수광영역을 외부환경으로부터 보호하기 위해 댐(46)이 개재된 채 투명체의 글래스(50)가 부착되어 있다. 또한 상기 도전성와이어(30) 등을 외부환경으로부터 보호하고, 상기 반도체칩(10)이 회로기판(70)의 관통공(76)내에서 견고히 지지되도록 상기회로기판(70)의 관통공(76) 내의 반도체칩(10)(글래스(50)의 외주연)이 봉지재(40)로 봉지되어 있으며, 이때 상기 봉지재(40)는 글래스(50)의 내주연은 침범하지 않토록 되어 있다. 더불어 상기 회로기판(70)의 볼랜드(73)에는 도전성볼(60)이 융착됨으로써 반도체칩(10)의 신호를 외부로 인출할 수 있도록 되어 있다.First, a CCD semiconductor chip 10 having a plurality of input / output pads 12 is provided, and the CCD semiconductor chip 10 is positioned in the through hole 76 formed in the circuit board 70. The circuit board 70 has a resin layer 71 including a through hole 76 formed through a predetermined size in the center thereof as a base layer, and a bond finger 72 is formed on the upper surface of the resin layer 71. The circuit pattern has a circuit pattern including a borland 73 on the lower surface, and the upper and lower circuit patterns are interconnected by conductive via holes 74. In addition, all the circuit patterns are coated with a cover coat 75 so that the bond finger 72 and the borland 73 are opened, and the semiconductor chip 10 is mounted on the bottom surface of the through hole 76 of the circuit board 70. The support member 80 is bonded so that it can be positioned. The input / output pads 12 of the semiconductor chip 10 and the bond fingers 72 of the circuit board 70 are bonded with conductive wires 30. A light receiving region is formed on an upper surface of the semiconductor chip 10, and a glass 50 of a transparent body is attached with a dam 46 interposed to protect the light receiving region from an external environment. In addition, the conductive wire 30 and the like are protected from the external environment, the through hole 76 of the circuit board 70 so that the semiconductor chip 10 is firmly supported in the through hole 76 of the circuit board 70. The semiconductor chip 10 (the outer periphery of the glass 50) inside is sealed with the encapsulant 40, and the encapsulant 40 is such that the inner periphery of the glass 50 does not invade. In addition, the conductive ball 60 is fused to the ball land 73 of the circuit board 70 so that the signal of the semiconductor chip 10 can be drawn out.
따라서, 이러한 반도체패키지는 상기 반도체칩(10)으로 수광된 빛에 의한 소정의 전기적 신호가 도전성와이어(30), 본드핑거(72)를 포함하는 회로패턴, 도전성비아홀(74), 볼랜드(73)를 포함하는 회로패턴 및 도전성볼(60)을 통해서 외부의 마더보드로 전달된다.Accordingly, the semiconductor package includes a circuit pattern including conductive wires 30 and bond fingers 72, and a predetermined electrical signal by light received by the semiconductor chip 10, conductive via holes 74, and borland 73. It is transmitted to the external motherboard through the circuit pattern and the conductive ball 60, including.
이러한 반도체패키지의 제조 방법을 간단히 설명하면 다음과 같다.A method of manufacturing such a semiconductor package is briefly described as follows.
먼저 중앙에 관통공(76)이 구비된 회로기판(70)을 구비하고, 상기 관통공(76)의 저면에는 지지부재(80)를 접착시켜 그것을 폐쇄시킨다.First, a circuit board 70 having a through hole 76 in the center is provided, and the support member 80 is adhered to the bottom of the through hole 76 to close it.
상기 관통공(76)의 지지부재(80)상에 접착제 등을 이용하여 반도체칩(10)을 접착한다.The semiconductor chip 10 is adhered to the support member 80 of the through hole 76 using an adhesive or the like.
상기 반도체칩(10) 상면에 댐(46)을 개재하여 글래스(50)를 부착시킨다. 여기서, 상기 반도체칩(10)은 미리 글래스(50)가 부착된 것을 회로기판(70)의 관통공(76) 내에 탑재할 수도 있다.The glass 50 is attached to the upper surface of the semiconductor chip 10 via the dam 46. Here, the semiconductor chip 10 may be mounted in the through hole 76 of the circuit board 70 to which the glass 50 has been previously attached.
상기 반도체칩(10)의 입출력패드(12)와 회로기판(70)의 본드핑거(72)를 도전성와이어(30)를 이용하여 상호 접속시킨다.The input / output pads 12 of the semiconductor chip 10 and the bond fingers 72 of the circuit board 70 are interconnected using the conductive wires 30.
상기 관통공(76) 및 반도체칩(10)의 글래스(50)가 부착된 영역 외측을 봉지재(40)로 봉지한다.The outer side of the region where the through hole 76 and the glass 50 of the semiconductor chip 10 are attached is encapsulated with the encapsulant 40.
상기 회로기판(70)의 볼랜드(73)에 다수의 도전성볼(60)을 융착함으로써 마더보드에 실장 가능한 형태로 한다.A plurality of conductive balls 60 are fused to the ball lands 73 of the circuit board 70 so as to be mounted on the motherboard.
그러나 이러한 종래의 반도체패키지 및 그 제조 방법은 다음과 같은 문제점이 있다.However, such a conventional semiconductor package and its manufacturing method have the following problems.
첫째, 중앙에 관통공이 형성되고, 상하면에는 복잡한 회로패턴이 형성된 회로기판을 이용함으로써 반도체패키지의 가격이 고가로 된다.First, the price of the semiconductor package becomes expensive by using a circuit board having a through hole formed in the center and a complicated circuit pattern formed on the upper and lower surfaces thereof.
둘째, 회로기판에 반도체칩을 탑재한 후 글래스의 외주연인 관통공 및 그 주변 영역을 봉지재로 봉지함으로써 봉지재가 상기 글래스 상면을 쉽게 오염시키게 된다.Second, after the semiconductor chip is mounted on the circuit board, the encapsulant easily contaminates the upper surface of the glass by encapsulating the through hole, which is the outer periphery of the glass, and the peripheral region thereof with the encapsulant.
셋째, 봉지 공정중 몰드의 가압력이 상기 글래스에 그대로 전달되어 상기 글래스가 파손될 위험이 있다.Third, there is a risk that the pressing force of the mold during the encapsulation process is transferred to the glass as it is and the glass is broken.
넷째, 반도체칩의 상면에 댐을 개재하여 직접 글래스를 부착하여야 함으로써 높은 정밀도를 필요로 할 뿐만 아니라 글래스 부착시 반도체칩의 상면을 파손하거나 또는 오염시키는 문제점이 있다.Fourth, by attaching the glass directly to the upper surface of the semiconductor chip via a dam, not only high precision is required, but also there is a problem of damaging or contaminating the upper surface of the semiconductor chip when the glass is attached.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 고가의 회로기판뿐만 아니라 저가의 리드프레임을 이용한 반도체패키지 및 그 제조 방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and to provide a semiconductor package using a low cost lead frame as well as an expensive circuit board and a method of manufacturing the same.
본 발명의 다른 목적은 반도체칩의 탑재전에 봉지재와 회로기판 또는 리드프레임을 일체로 한 베이스기판을 구비함으로써, 종래와 같은 글래스 상면의 오염이나 파손 문제를 해결할 수 있는 반도체패키지 및 그 제조 방법의 제공에 있다.Another object of the present invention is to provide a semiconductor package and a method for manufacturing the same, which can solve the problem of contamination or damage on the upper surface of a glass by providing a base substrate in which an encapsulant, a circuit board or a lead frame are integrated before the semiconductor chip is mounted. Is in the offering.
본 발명의 또다른 목적은 상기 베이스기판에 글래스를 부착함으로써 종래와 같이 반도체칩의 파손이나 오염 문제를 제거할 수 있는 반도체패키지 및 그 제조 방법의 제공에 있다.Still another object of the present invention is to provide a semiconductor package and a method of manufacturing the same, by which glass is attached to the base substrate to eliminate the problem of damage or contamination of a semiconductor chip as in the prior art.
도1a 및 도1b는 종래 리드프레임 및 회로기판을 이용한 CCD용 반도체패키지를 도시한 단면도이다.1A and 1B are cross-sectional views showing a semiconductor package for a CCD using a conventional lead frame and a circuit board.
도2 내지 도4는 본 발명의 제1,2,3 실시예에 의한 CCD용 반도체패키지를 도시한 단면도이다.2 to 4 are cross-sectional views showing a semiconductor package for a CCD according to the first, second and third embodiments of the present invention.
도5a 내지 도5e는 본 발명의 제1실시예에 의한 반도체패키지의 제조 방법을 도시한 설명도이다.5A to 5E are explanatory views showing a method of manufacturing a semiconductor package according to the first embodiment of the present invention.
도6은 도5a에 도시된 베이스기판을 얻기 위한 공정을 도시한 것이다.FIG. 6 shows a process for obtaining the base substrate shown in FIG. 5A.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
101,102,103; 본 발명의 제1,2,3실시예에 의한 반도체패키지101,102,103; Semiconductor package according to the first, second and third embodiments of the present invention
10; 반도체칩 12; 입출력패드10; Semiconductor chip 12; I / O pad
20; 리드 22; 돌출단자20; Lead 22; Protrusion terminal
24; 칩탑재판 30; 도전성와이어24; Chip mounting plate 30; Conductive Wire
40; 봉지재 42; 단턱40; Encapsulant 42; Step
44; 웰영역 50; 글래스44; Well region 50; Glass
60; 도전성볼 70; 회로기판60; Conductive ball 70; Circuit board
71; 수지층 72; 본드핑거71; Resin layer 72; Bondfinger
73; 볼랜드 74; 도전성비아홀73; Borland 74; Conductive Via Hole
75; 커버코트 76; 관통공75; Covercoat 76; Through hole
77; 도전성비아홀 80; 지지부재77; Conductive via holes 80; Support member
90; 탑몰드 92; 바텀몰드90; Top mold 92; Bottom mold
B; 베이스기판B; Base board
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 상면에 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 외주연에 하부를 향하여 다수의 돌출단자가 구비된 리드가 위치된 동시에, 상기 반도체칩의 외주연에 소정 공간의 웰영역이 형성되면서 상기 리드를 감싸는 봉지재로 이루어진 베이스기판과; 상기 반도체칩의 입출력패드와 베이스기판의 리드를 전기적으로 접속시키는 도전성와이어와; 상기 반도체칩의 외주연에 위치된 봉지재에 접착제로 접착된 글래스를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention comprises: a semiconductor chip having a plurality of input / output pads formed on an upper surface thereof; A base substrate having a lid disposed on an outer circumference of the semiconductor chip, the lid having a plurality of protruding terminals positioned downward, and a sealing material surrounding the lead while a well region of a predetermined space is formed on the outer circumference of the semiconductor chip; Conductive wires electrically connecting the input / output pads of the semiconductor chip to the leads of the base substrate; It characterized in that it comprises a glass adhesively bonded to the encapsulant located on the outer periphery of the semiconductor chip.
여기서, 상기 리드의 돌출단자는 봉지재 저면으로 노출 또는 돌출되어야 한다. 또한, 상기 리드의 상면 일정 영역은 도전성와이어와 접속될 수 있도록 봉지재 상면으로 노출 또는 돌출되어야 한다.Here, the protruding terminal of the lead should be exposed or protruded from the bottom of the encapsulant. In addition, a predetermined region of the upper surface of the lead should be exposed or protruded from the upper surface of the encapsulant so as to be connected to the conductive wire.
또한, 상기 베이스기판은 상기 반도체칩의 저면에도 돌출단자를 갖는 리드가 위치될 수 있다.In addition, the base substrate may have a lead having a protruding terminal on a bottom surface of the semiconductor chip.
또한 상기 베이스기판은 상기 반도체칩의 저면에 칩탑재판이 위치될 수도 있다.In addition, the base substrate may be a chip mounting plate on the bottom surface of the semiconductor chip.
또한, 상기 베이스기판은 리드의 돌출단자 저면에 도전성 도금층 또는 도전성볼이 융착됨이 바람직하다.In addition, the base substrate is preferably a conductive plating layer or conductive ball is fused to the bottom surface of the protruding terminal of the lead.
또한, 상기 반도체칩의 하면과 리드의 상면은 대략 동일면이 되도록 함이 바람직하다.In addition, it is preferable that the lower surface of the semiconductor chip and the upper surface of the lead are approximately the same surface.
더불어, 상기 웰영역 외주연의 봉지재는 글래스가 용이하게 안착 및 접착될 수 있도록 단턱이 형성됨이 바람직하다.In addition, the encapsulant of the outer periphery of the well region is preferably formed with a step so that glass can be easily seated and bonded.
또한, 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 상면에 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩이 위치하도록 관통구가 형성된 수지층이 구비되고, 상기 수지층의 상면에는 본드핑거를 포함하는 회로패턴이, 하면에는 볼랜드를 포함하는 회로패턴이 형성되어 있으며, 상기 상,하면의 회로패턴은 도전성비아홀로 연결되고, 상기 수지층의 상면인 반도체칩의 외주연에는 소정 공간의 웰영역이 형성되도록 봉지재가 봉지된 베이스기판과; 상기 반도체칩의 입출력패드와 베이스기판의 본드핑거를 전기적으로 접속시키는 도전성와이어와; 상기 반도체칩의 외주연에 위치된 봉지재에 접착제로 접착된 글래스를 포함하여 이루어진 것을 특징으로 한다.In addition, the semiconductor package according to the present invention in order to achieve the above object is a semiconductor chip having a plurality of input and output pads on the upper surface; A resin layer having a through hole formed to position the semiconductor chip is provided. A circuit pattern including a bond finger is formed on an upper surface of the resin layer, and a circuit pattern including a ball land is formed on a lower surface of the resin layer. A base substrate connected to the conductive via hole and encapsulated with an encapsulant such that a well region of a predetermined space is formed at an outer circumference of the semiconductor chip, which is an upper surface of the resin layer; Conductive wires electrically connecting the input / output pads of the semiconductor chip to the bond fingers of the base substrate; It characterized in that it comprises a glass adhesively bonded to the encapsulant located on the outer periphery of the semiconductor chip.
여기서도, 상기 웰영역 외주연의 봉지재는 글래스가 용이하게 안착 및 접착될 수 있도록 단턱이 형성됨이 바람직하다.Here, the encapsulant of the outer periphery of the well region is preferably formed with a step so that glass can be easily seated and bonded.
또한, 상기 반도체칩의 저면에는 지지부재가 위치되고, 상기 지지부재는 상기 베이스기판의 관통공을 폐쇄할 수 있도록 접착제로 수지층 하면에 접착됨이 바람직하다.In addition, the support member is located on the bottom surface of the semiconductor chip, the support member is preferably adhered to the bottom surface of the resin layer with an adhesive so as to close the through hole of the base substrate.
또한 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지의 제조 방법은 하부를 향하여 다수의 돌출단자가 구비된 리드와, 상기 리드를 감싸는 동시에 리드의 상면 중앙에는 일정 공간의 웰영역이 형성되도록 하는 봉지재로 이루어진 베이스기판을 제공하는 단계와; 상기 웰영역에 다수의 입출력패드가 형성된 반도체칩을 접착제로 접착하여 탑재하는 단계와; 상기 반도체칩의 입출력패드와 리드를 도전성와이어로 접속하는 단계와; 상기 반도체칩 외주연에 위치하는 봉지재에 상기 반도체칩의 상부가 폐쇄되도록 접착제로 글래스를 부착하는 단계를 포함하여 이루어진 것을 특징으로 한다.In addition, the method for manufacturing a semiconductor package according to the present invention in order to achieve the above object is a lead having a plurality of protruding terminals toward the bottom, and wraps the lead to form a well region of a predetermined space in the center of the upper surface of the lead Providing a base substrate made of an encapsulant; Attaching and mounting a semiconductor chip having a plurality of input / output pads in the well region with an adhesive; Connecting the input / output pad and the lead of the semiconductor chip with conductive wires; And attaching a glass with an adhesive so that an upper portion of the semiconductor chip is closed to an encapsulant positioned at an outer circumference of the semiconductor chip.
여기서, 상기 리드의 돌출단자 하단에 도전성 플레이트층 또는 도전성볼을 형성하는 단계를 더 포함할 수도 있다.Here, the method may further include forming a conductive plate layer or conductive ball at the bottom of the protruding terminal of the lead.
상기와 같이 하여 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 고가의 회로기판 뿐만 아니라 저가의 리드프레임을 이용한 베이스기판을 이용할 수 있음으로써 가격이 저렴한 반도체패키지를 제공하게 된다.As described above, according to the semiconductor package and the manufacturing method of the present invention, it is possible to use not only an expensive circuit board but also a base board using a low-cost lead frame, thereby providing an inexpensive semiconductor package.
또한, 반도체칩의 탑재전에 미리 봉지재와 회로기판 또는 리드프레임을 일체로 한 베이스기판을 이용함으로써, 종래와 같이 글래스 상면이 오염될 위험이 없고 또한 글래스의 파손 문제를 최소화할 수 있게 된다.In addition, by using a base substrate in which an encapsulant, a circuit board, or a lead frame are integrated before the semiconductor chip is mounted, there is no risk of contamination of the upper surface of the glass as in the prior art, and the problem of glass breakage can be minimized.
또한, 베이스기판중 단턱이 형성된 봉지재에 글래스를 부착함으로써 반도체칩의 파손이나 오염문제를 대폭 저감시킬 수 있게 된다.In addition, by attaching the glass to the encapsulant having a stepped portion of the base substrate, it is possible to greatly reduce the damage or contamination of the semiconductor chip.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
먼저, 도2 내지 도4는 본 발명의 제1,2,3 실시예에 의한 반도체패키지(101,102,103)를 도시한 단면도이다.2 to 4 are cross-sectional views illustrating semiconductor packages 101, 102, and 103 according to the first, second, and third embodiments of the present invention.
먼저 도2,3의 제1,2실시예에 의한 반도체패키지(101,102)를 참조한다.First, the semiconductor packages 101 and 102 according to the first and second embodiments of FIGS. 2 and 3 will be referred.
도시된 바와 같이 상면에 다수의 입출력패드(12)가 구비된 반도체칩(10)이 위치되어 있으며, 상기 반도체칩(10)의 하면 및 측면으로는 베이스기판(B)이 위치되어 있다. 상기 반도체칩(10)과 베이스기판(B)은 에폭시 접착제나 양면접착테이프 등으로 접착되어 있다.As illustrated, a semiconductor chip 10 having a plurality of input / output pads 12 is positioned on an upper surface thereof, and a base substrate B is positioned on a lower surface and a side surface of the semiconductor chip 10. The semiconductor chip 10 and the base substrate B are bonded with an epoxy adhesive, a double-sided adhesive tape, or the like.
상기 베이스기판(B)은 하부를 향하여 다수의 돌출단자(22)가 구비된 리드(20)가 어레이(array)된 동시에, 상기 반도체칩(10)의 외주연에 소정 공간의 웰영역(44)이 구비되도록 상기 리드(20)를 포함하는 상면이 봉지재(40)로 감싸여져 있다. 물론, 상기 리드(20)의 돌출단자(22) 하면은 봉지재(40) 저면으로 노출 또는 돌출되도록 되어 있으며, 상기 반도체칩(10)의 저면과 상기 리드(20)의 상면은 대략 동일면상에 위치되어 있다.The base substrate B is arrayed with leads 20 having a plurality of protruding terminals 22 facing downward, and a well region 44 of a predetermined space at an outer circumference of the semiconductor chip 10. The upper surface including the lead 20 is wrapped in the encapsulant 40 so as to be provided. Of course, the bottom surface of the protruding terminal 22 of the lead 20 is exposed or protruded from the bottom surface of the encapsulant 40, and the bottom surface of the semiconductor chip 10 and the top surface of the lead 20 are substantially on the same surface. It is located.
더불어 상기 반도체칩(10)의 저면에도 도2에서와 같이 돌출단자(22)를 포함하는 리드(20)가 어레이되어 있음으로써 파인피치(fine pitch)화한 반도체칩(10)을 수용할 수 있게 되어 있고, 또한 도3에서와 같이 상기 반도체칩(10)이 저면에는 금속성 칩탑재판(24)이 위치될 수 있고, 이 칩탑재판(24)의 하면은 봉지재(40) 하면으로 노출되어 반도체칩(10)의 방열 성능을 향상시킬 수 있게 되어 있다.In addition, the lead 20 including the protruding terminal 22 is arranged on the bottom surface of the semiconductor chip 10 to accommodate the fine pitched semiconductor chip 10. In addition, as shown in FIG. 3, a metallic chip mounting plate 24 may be positioned on the bottom surface of the semiconductor chip 10, and the bottom surface of the chip mounting plate 24 may be exposed to the bottom surface of the encapsulant 40 so as to expose the semiconductor. The heat dissipation performance of the chip 10 can be improved.
여기서, 상기 리드(20)는 구리(Cu), 구리 합금(Cu alloy), 합금 37(니켈(Ni)37%, 철(Fe)55%), 또는 적용되는 분야에 따라 구리가 도금된 강철과 같은 통상적인 리드프레임으로부터 얻어진 것이다.Here, the lead 20 is made of copper (Cu), copper alloy (Cu alloy), alloy 37 (Ni 37% (Ni), iron (Fe) 55%), or copper plated steel according to the application field and It is obtained from the same conventional lead frame.
또한, 상기와 같이 돌출단자(22)가 구비된 리드(20)는 통상의 리드프레임을 할프에칭(half etching) 기술로 가공하여 형성될 수 있다. 예를 들면 리드프레임의 총체적 패턴(칩탑재판, 내부리드 및 외부리드 등)이 형성된 후 상기 내부리드 중에서 소정 영역에만 포토레지스트(photo resist)를 도포한 후 에칭용액을 분사시킴으로써, 두께가 서로 다른 리드(20) 즉, 돌출단자(22)를 얻을 수 있게 된다. 또한, 상기와 같은 돌출단자(22)는 리드(20)를 기계적으로 절곡하는 스탬핑(stamping) 기술에 의해서도 가공될 수 있으며, 이는 당업자의 임의적 선택사항에 불과하다.In addition, the lead 20 having the protruding terminal 22 as described above may be formed by processing a conventional lead frame by a half etching technique. For example, after the overall pattern of the lead frame (chip mounting plate, inner lead, outer lead, etc.) is formed, a photoresist is applied only to a predetermined region among the inner leads, and then the etching solution is sprayed to have different thicknesses. The lead 20, that is, the protruding terminal 22 can be obtained. In addition, the protruding terminal 22 as described above may also be processed by a stamping technique for mechanically bending the lid 20, which is merely an arbitrary option by those skilled in the art.
상기와 같이 리드(20)에 형성된 돌출단자(22)로 인하여 리드(20)와 봉지재(40) 사이의 접착면적이 증가하게 되고, 따라서 상기 리드(20)가 봉지재(40)에서 상,하 또는 측면 방향으로 이탈되지 않게 된다.Due to the protruding terminal 22 formed in the lid 20 as described above, the adhesion area between the lid 20 and the encapsulant 40 is increased, so that the lead 20 is formed on the encapsulant 40. There is no deviation in the downward or lateral direction.
또한, 상기 리드(20) 상면의 봉지재(40) 상면에는 반도체칩(10)의 상면과 대략 수평 방향으로 단턱(42)이 형성되어 있으며, 이러한 봉지재(40) 형상은 이를 봉지하는 몰드(하기에서 다시 설명함)의 형상에 의해 형성된 것들이다.In addition, the upper surface of the encapsulant 40 on the upper surface of the lead 20, the stepped 42 is formed in a substantially horizontal direction with the upper surface of the semiconductor chip 10, the encapsulant 40 is formed in the mold ( These are formed by the shape of the same).
또한, 상기 반도체칩(10)의 외주연에 위치하는 리드(20)의 일정 영역 역시 봉지재(40) 상면으로 노출되어 있고, 그 표면에는 은(Ag)이나 금(Au) 등이 도금될 수 있다.In addition, a predetermined region of the lead 20 positioned at the outer circumference of the semiconductor chip 10 is also exposed to the upper surface of the encapsulant 40, and the surface of the lead 20 may be plated with silver (Ag) or gold (Au). have.
계속해서, 상기 반도체칩(10)의 입출력패드(12)와 상기 리드(20)의 일정영역은 알루미늄와이어나 골드와이어와 같은 도전성와이어(30)에 의해 상호 본딩되어 있다.Subsequently, the input / output pad 12 and the predetermined region of the lead 20 of the semiconductor chip 10 are bonded to each other by a conductive wire 30 such as aluminum wire or gold wire.
또한, 상기 반도체칩(10)의 외주연에 웰영역(44)을 형성하는 봉지재(40)의 단턱(42)에는 접착제 또는 양면접착테이프 등에 의해 투명체의 글래스(50)가 접착되어 있음으로써 상기 반도체칩(10)의 상면 영역을 폐쇄하여 외부 환경으로부터 보호되도록 되어 있다.In addition, the glass 50 of the transparent body is adhered to the step 42 of the encapsulant 40 forming the well region 44 on the outer circumference of the semiconductor chip 10 by an adhesive or a double-sided adhesive tape. The upper region of the semiconductor chip 10 is closed to protect it from the external environment.
상기 봉지재(40) 하면으로 노출 또는 돌출된 돌출단자(22)에는 도전성 도금층(예를 들면 금(Au), 니켈(Ni), 팔라디엄(Pd), 인코넬(Inconel), 납(Pb)과 주석(Sn)의 솔더 또는 탄탈륨(Tantalum) 등) 또는 도전성볼(60)(예를 들면 솔더볼) 등이 형성되어 있음으로서 마더보드에 실장 가능하게 되어 있다. 도2,3에서는 도전성볼(60)이 융착된 상태를 도시하고 있다.The protruding terminal 22 exposed or protruding from the lower surface of the encapsulant 40 has a conductive plating layer (for example, gold (Au), nickel (Ni), palladium (Pd), inconel, lead (Pb) and Tin solder, tantalum, or the like, conductive balls 60 (for example, solder balls) and the like are formed to enable mounting on the motherboard. 2 and 3 illustrate a state in which the conductive balls 60 are fused.
한편 도4에 도시된 바와 같이 본 발명의 제3실시예에 의한 반도체패키지(103)는 회로기판(70)에 봉지재(40)가 미리 봉지된 베이스기판(B)을 이용할 수도 있다.Meanwhile, as shown in FIG. 4, the semiconductor package 103 according to the third embodiment of the present invention may use a base substrate B in which the encapsulant 40 is previously encapsulated in the circuit board 70.
이는 도시된 바와 같이, 상면에 다수의 입출력패드(12)가 형성된 반도체칩(10)이 구비되어 있고, 상기 반도체칩(10)의 외주연에는 회로기판(70)을 포함하는 베이스기판(B)이 위치되어 있다.As shown, the semiconductor substrate 10 is provided with a plurality of input and output pads 12 on the upper surface, and the base substrate (B) including a circuit board 70 on the outer periphery of the semiconductor chip 10 Is located.
상기 베이스기판(B)은 반도체칩(10)이 위치하도록 그 반도체칩(10)보다 큰 관통공(76)이 형성된 수지층(71)이 구비되고, 상기 수지층(71) 상면에는 본드핑거(72)를 포함하는 회로패턴이, 하면에는 볼랜드(73)를 포함하는 회로패턴이 형성되어 있다. 상기 상,하면의 회로패턴은 도전성비아홀(74)로 서로 연결되어 있다. 또한 상기 회로패턴중 본드핑거(72) 및 볼랜드(73)를 제외한 영역은커버코트(75)로 코팅되어 있으며, 상기 수지층(71)의 상면인 반도체칩(10)의 외주연에는 소정 공간의 웰영역(44)이 형성되도록 일정높이의 봉지재(40)가 봉지되어 있다. 상기 봉지재(40) 역시 상면에 단턱(42)이 형성되어 있으며, 이는 몰드의 형상에 의해 형성된 것이다.The base substrate B is provided with a resin layer 71 having a through hole 76 larger than the semiconductor chip 10 so that the semiconductor chip 10 is positioned. A bond finger is formed on the upper surface of the resin layer 71. The circuit pattern including 72 has a circuit pattern including a ball land 73 formed on its lower surface. The upper and lower circuit patterns are connected to each other by conductive via holes 74. In addition, a region of the circuit pattern except for the bond finger 72 and the borland 73 is coated with a cover coat 75, and a predetermined space is formed on the outer circumference of the semiconductor chip 10, which is the upper surface of the resin layer 71. The encapsulant 40 having a predetermined height is encapsulated so that the well region 44 is formed. The encapsulant 40 is also formed with a step 42 on the upper surface, which is formed by the shape of the mold.
상기 반도체칩(10)의 입출력패드(12)와 베이스기판(B)의 본드핑거(72)는 상기한 알루미늄와이어 및 골드와이어와 같은 도전성와이어(30)에 의해 상호 접속되어 있다.The input / output pads 12 of the semiconductor chip 10 and the bond fingers 72 of the base substrate B are connected to each other by conductive wires 30 such as aluminum wire and gold wire.
또한, 상기 반도체칩(10)의 외주연에 위치된 봉지재(40)의 단턱(42)에는 접착제 또는 양면접착테이프 등에 의해 투명체의 글래스(50)가 부착되어 있으며, 상기 반도체칩(10)의 저면에는 지지부재(80)가 위치되어 있다. 상기 지지부재(80)는 상기 베이스기판(B)의 관통공(76) 하면을 폐쇄할 수 있도록 접착제 등으로 수지층(71) 하면에 접착되어 있다. 여기서, 상기 지지부재(80)는 통상적인 접착테이프를 이용할 수도 있다. 또한 상기 지지부재(80)는 반도체칩(10)의 방열성능을 향상시키기 위해 금속재로 구비할 수도 있다.In addition, the stepped glass 42 of the encapsulant 40 positioned on the outer circumference of the semiconductor chip 10 is attached with a glass 50 of a transparent body by an adhesive or a double-sided adhesive tape. The support member 80 is located at the bottom. The support member 80 is adhered to the bottom surface of the resin layer 71 with an adhesive or the like so as to close the bottom surface of the through hole 76 of the base substrate B. Here, the support member 80 may use a conventional adhesive tape. In addition, the support member 80 may be provided with a metal material to improve the heat dissipation performance of the semiconductor chip 10.
상기와 같이하여, 상기 반도체칩(10)의 상,하면은 글래스(50) 및 지지부재(80)로 폐쇄되어 외부 환경으로부터 보호되며, 계속해서 상기 베이스기판(B)의 볼랜드(73)에는 도전성볼(60)이 융착됨으로써 마더보드에 실장 가능한 형태로 되어 있다.As described above, the upper and lower surfaces of the semiconductor chip 10 are closed by the glass 50 and the supporting member 80 to be protected from the external environment, and subsequently, the conductive material is connected to the ball lands 73 of the base substrate B. By fusion | melting the ball 60, it becomes the form which can be mounted on a motherboard.
한편, 도5a 내지 도5e는 본 발명의 제1실시예에 의한 반도체패키지의 제조 방법을 도시한 설명도이다.5A to 5E are explanatory views showing a method of manufacturing a semiconductor package according to the first embodiment of the present invention.
먼저, 도5a에 도시된 바와 같이 하부를 향하여 다수의 돌출단자(22)가 구비된 리드(20)와, 상기 리드(20)를 감싸는 동시에 리드(20)의 상면 중앙에는 일정 공간의 웰영역(44)이 형성되도록 하는 봉지재(40)로 이루어진 베이스기판(B)을 제공한다. 여기서, 상기 리드(20)의 돌출단자(22) 하면은 모두 봉지재(40) 하면으로 노출되어 있고, 상기 웰영역(44)에 위치하는 리드(20) 상면도 봉지재(40) 상면으로 노출되어 있다.First, as shown in FIG. 5A, a lid 20 having a plurality of protruding terminals 22 facing downward, and a well area having a predetermined space in the center of an upper surface of the lid 20 while surrounding the lid 20 are formed. It provides a base substrate (B) consisting of an encapsulant 40 so that 44 is formed. Here, all of the lower surface of the protruding terminal 22 of the lead 20 is exposed to the lower surface of the encapsulant 40, and the upper surface of the lead 20 positioned in the well region 44 is also exposed to the upper surface of the encapsulant 40. It is.
이러한 베이스기판(B)은 통상 도6에 도시된 바와 같이 양측면에 일정공간의 캐비티가 형성된 탑몰드(90)와 대략 평판형의 바텀몰드(92)를 구비하고, 상기 탑몰드(90) 및 바텀몰드(92) 사이에 리드(20)를 안착시킨 후 봉지재(40)로 봉지함으로써 얻어진 것이다. 즉, 상기 탑몰드(90)의 중앙 영역은 상기 리드(20)의 중앙부 표면에 직접 밀착되고, 그 외주연은 일정공간의 캐비티(94)가 형성된 것을 구비함으로써, 리드(20) 중앙 표면에는 차후 웰영역(44)이 형성되도록 봉지재(40)가 존재하지 않고 그 외주연인 상기 탑몰드(90)의 캐비티(94)와 대응하는 영역에만 봉지재(40)가 형성된다. 또한 상기 리드(20)의 돌출단자(22) 하면도 봉지재(40)로 봉지되지 않게 됨으로써 결국 리드(20)와 봉지재(40)가 일체화되는 베이스기판(B)을 구비할 수 있게 된다.As shown in FIG. 6, the base substrate B includes a top mold 90 having a cavity of a predetermined space formed on both sides thereof, and a bottom mold 92 having a substantially flat plate shape, and the top mold 90 and the bottom thereof. It is obtained by sealing the lead 20 between the mold 92 and sealing it with the sealing material 40. That is, the central region of the top mold 90 is in direct contact with the surface of the central portion of the lid 20, and the outer periphery of the top mold 90 is provided with a cavity 94 of a predetermined space, whereby The encapsulant 40 is not formed in the encapsulant 40 so that the well region 44 is formed, and is formed only in an area corresponding to the cavity 94 of the top mold 90, which is the outer periphery thereof. In addition, since the lower surface of the protruding terminal 22 of the lead 20 is not encapsulated with the encapsulant 40, the base substrate B may be provided in which the lead 20 and the encapsulant 40 are integrated.
이어서, 상기 웰영역(44)에 다수의 입출력패드(12)가 형성된 반도체칩(10)을 접착제 또는 양면 접착테이프 등을 이용하여 접착 및 탑재한다.Subsequently, the semiconductor chip 10 having the plurality of input / output pads 12 formed in the well region 44 is bonded and mounted using an adhesive or a double-sided adhesive tape.
이어서, 상기 반도체칩(10)의 입출력패드(12)와 리드(20)의 소정 영역을 골드와이어나 알루미늄와이어와 같은 도전성와이어(30)를 이용하여 상호 접속하다.Subsequently, a predetermined region of the input / output pad 12 and the lead 20 of the semiconductor chip 10 is interconnected using a conductive wire 30 such as a gold wire or an aluminum wire.
이어서, 상기 반도체칩(10)의 외주연에 위치하는 봉지재(40)의 단턱(42)에 상기 반도체칩(10)의 상부가 폐쇄되도록 접착제로 글래스(50)를 부착한다.Subsequently, the glass 50 is attached to the step 42 of the encapsulant 40 positioned at the outer circumference of the semiconductor chip 10 with an adhesive so as to close the upper portion of the semiconductor chip 10.
또한, 상기 봉지재(40) 하면으로 노출 또는 돌출되는 돌출단자(22)의 하면에 도전성 도금층이나 도전성볼(60)을 형성하는 단계를 더 수행할 수도 있다.In addition, the conductive plating layer or the conductive ball 60 may be further formed on the bottom surface of the protruding terminal 22 exposed or protruding from the bottom surface of the encapsulant 40.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
상기와 같이 하여 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 고가의 회로기판 뿐만 아니라 저가의 리드프레임을 이용한 베이스기판을 이용할 수 있음으로써 가격이 저렴한 반도체패키지를 얻을 수 있는 효과가 있다.As described above, according to the semiconductor package and the manufacturing method thereof according to the present invention, an inexpensive semiconductor package can be obtained by using not only an expensive circuit board but also a base board using an inexpensive lead frame.
또한, 반도체칩의 탑재전에 미리 봉지재와 회로기판 또는 리드프레임을 일체로 한 베이스기판을 이용함으로써, 종래와 같이 글래스 상면이 오염될 위험이 없고 또한 글래스의 파손 문제를 최소화할 수 있는 효과가 있다.In addition, by using a base substrate in which the encapsulant and the circuit board or lead frame are integrated before the semiconductor chip is mounted, there is no risk of contamination of the upper surface of the glass as in the prior art, and the glass breakage problem can be minimized. .
또한, 베이스기판중 단턱이 형성된 봉지재에 글래스를 부착함으로써 반도체칩의 파손이나 오염문제를 대폭 저감시킬 수 있는 효과가 있다.In addition, by attaching the glass to the encapsulant having a stepped portion of the base substrate, there is an effect that can significantly reduce the damage or contamination of the semiconductor chip.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020008244A (en) * | 2000-07-20 | 2002-01-30 | 마이클 디. 오브라이언 | Lead frame strip and semiconductor package using it and manufacturing method thereof |
| KR100748811B1 (en) * | 2003-10-10 | 2007-08-13 | 마츠시타 덴끼 산교 가부시키가이샤 | Optical device and method for manufacturing the same |
-
1999
- 1999-12-30 KR KR1019990065931A patent/KR20010058581A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020008244A (en) * | 2000-07-20 | 2002-01-30 | 마이클 디. 오브라이언 | Lead frame strip and semiconductor package using it and manufacturing method thereof |
| KR100748811B1 (en) * | 2003-10-10 | 2007-08-13 | 마츠시타 덴끼 산교 가부시키가이샤 | Optical device and method for manufacturing the same |
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