KR100370852B1 - semiconductor package - Google Patents
semiconductor package Download PDFInfo
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- KR100370852B1 KR100370852B1 KR10-1999-0059330A KR19990059330A KR100370852B1 KR 100370852 B1 KR100370852 B1 KR 100370852B1 KR 19990059330 A KR19990059330 A KR 19990059330A KR 100370852 B1 KR100370852 B1 KR 100370852B1
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- circuit board
- dam
- semiconductor chip
- semiconductor package
- circuit pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
이 발명은 반도체패키지에 관한 것으로, CCD용 반도체칩을 탑재한 반도체패키지에서 글래스를 장착하기 위한 댐 형성시 회로기판의 각종 회로패턴을 보호함은 물론 몰드 플래시를 억제하고 또한 댐과 회로기판 사이의 접착력을 향상시키기 위해, 일면에 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 저면에 접착제로 접착되어 있되, 수지층을 중심으로 상면에는 다수의 본드핑거를 포함하는 회로패턴이 형성되어 있고, 저면에는 다수의 랜드를 포함하는 회로패턴이 형성되어 있으며, 상기 상,하면의 회로패턴은 도전성 비아홀로 상호 연결되고, 상기 본드핑거 및 랜드를 제외한 회로패턴 전체는 커버코트로 코팅된 회로기판과; 상기 반도체칩의 입출력패드와 상기 회로기판의 본드핑거를 전기적으로 접속하는 도전성와이어와; 상기 반도체칩의 외주연인 회로기판 상면에 대략 상기 도전성와이어의 루프 높이보다 높게 형성된 댐과; 상기 반도체칩으로 외부의 빛이 수광될 수 있도록 상기 댐의 상면에 접착된 글래스와; 상기 회로기판 하면의 랜드에 형성된 도전성볼로 이루어진 반도체패키지에 있어서, 상기 회로기판의 본드핑거 외주연인 커버코트 상면에는 다수의 링이 일정 간격을 두고 형성되어 있고, 상기 링의 상면 일정 영역을 포함하여 상기 링 사이에 댐이 형성된 것을 특징으로 함.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, which protects various circuit patterns of a circuit board during dam formation for mounting glass in a semiconductor package equipped with a CCD semiconductor chip. A semiconductor chip having a plurality of input / output pads formed on one surface thereof to improve adhesion force; The circuit pattern is bonded to the bottom surface of the semiconductor chip with an adhesive, the circuit pattern including a plurality of bond fingers on the top surface of the resin layer, the circuit pattern including a plurality of lands on the bottom surface is formed, The circuit pattern of the lower surface is connected to each other by a conductive via hole, the entire circuit pattern except for the bond finger and the land is coated with a cover coat; Conductive wires electrically connecting the input / output pads of the semiconductor chip to the bond fingers of the circuit board; A dam formed on the upper surface of the circuit board, which is the outer circumference of the semiconductor chip, to be substantially higher than the loop height of the conductive wire; Glass bonded to an upper surface of the dam so that external light can be received by the semiconductor chip; In the semiconductor package consisting of a conductive ball formed in the land on the lower surface of the circuit board, a plurality of rings are formed on the upper surface of the cover coat, which is the outer periphery of the bond finger of the circuit board at regular intervals, including a certain area on the upper surface of the ring And a dam is formed between the rings.
Description
본 발명은 반도체패키지에 관한 것으로, 보다 상세하게 설명하면 CCD용 반도체칩을 탑재한 반도체패키지에서 글래스를 장착하기 위한 댐 형성시 회로기판의 각종 회로패턴을 보호함은 물론 몰드 플래시를 억제하고 또한 댐과 회로기판 사이의 접착력을 향상시킬 수 있는 반도체패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to protect various circuit patterns of a circuit board when dams are mounted for mounting glass in a semiconductor package equipped with a CCD semiconductor chip. The present invention relates to a semiconductor package capable of improving adhesion between a circuit board and a circuit board.
통상 CCD는 Charge Coupled Devices의 약어로 반도체 소자의 일종인 전하결합 소자를 말하며 하나의 소자로부터 인접한 다른 소자로 전하를 전송할 수 있는 소자를 말한다. 텔레비전 카메라의 영상신호 계통에서 피사체의 빛은 렌즈를 통과한 후 색분해 광학계에 의해 3원색으로 분해돼 각각 촬상 디바이스의 수광면에 결상되는데 그 상을 소자내에서 전자적으로 주사해 전기신호로 변환시켜 출력하는 소자가 고체촬상소자이다. 이러한 CCD의 응용분야는 촬상디바이스, 대용량메모리, 아날로그 신호처리의 세가지이며 구조적으로는 MOS집적회로이기 때문에 MOS프로세스 기술을 사용해 고집적회로(LSI)화도 용이하다. CCD는 특히 자기주사 기능과 광전변환 기능을 함께 갖추고 있기 때문에 촬상디바이스에 주로 응용되며 일차원의 라인센서와 이차원의 에이리어 센서가 있으며 그 화소수는 일반적으로 라인센서는 1,500화소, 에이리어센서는 512×320화소의 것이 있다.In general, CCD is an abbreviation of Charge Coupled Devices and refers to a charge coupled device, which is a kind of semiconductor device, and a device capable of transferring charges from one device to another adjacent device. In the video signal system of the television camera, the light of the subject passes through the lens and is decomposed into three primary colors by color separation optical systems, and is then formed on the light receiving surface of the imaging device. The device to be used is a solid state imaging device. There are three application fields of CCD such as imaging device, large-capacity memory, and analog signal processing, and because the structure is MOS integrated circuit, it is easy to make LSI using MOS process technology. CCD is mainly applied to imaging device because it has both self-scanning function and photoelectric conversion function, and there are one-dimensional line sensor and two-dimensional area sensor, and the number of pixels is generally 1,500 pixels for line sensor and 512 for area sensor. There is a thing of x320 pixels.
상기한 CCD 소자가 다수 형성된 CCD용 반도체칩을 탑재한 반도체패키지는 통상 그 반도체칩이 외부의 빛을 수광할 수 있도록 반도체칩의 상면에 글래스가 위치되어 있으며, 이러한 종래의 반도체패키지(100')를 도1a 및 도1b를 참조하여 간단히 설명하면 다음과 같다.In a semiconductor package equipped with a CCD semiconductor chip having a plurality of CCD elements, glass is usually placed on a top surface of the semiconductor chip so that the semiconductor chip can receive external light. Such a conventional semiconductor package 100 ' It will be described briefly with reference to Figures 1a and 1b as follows.
먼저 일면에 다수의 입출력패드(2a)가 형성된 반도체칩(2)이 구비되어 있다. 상기 반도체칩(2)의 저면에는 접착제에 의해 회로기판(10)이 접착되어 있다. 상기 회로기판(10)은 수지층(11)을 중심으로 상면에는 다수의 본드핑거(12)를 포함하는회로패턴이 형성되어 있고, 저면에는 다수의 랜드(13)를 포함하는 회로패턴이 형성되어 있으며, 상기 상,하면의 회로패턴은 도전성 비아홀(14)로 상호 연결되어 있다. 또한 상기 상면의 본드핑거(12) 및 저면의 랜드(13)를 제외한 모든 회로패턴은 커버코트(15) 등으로 코팅되어 있다.First, a semiconductor chip 2 having a plurality of input / output pads 2a formed on one surface thereof is provided. The circuit board 10 is adhered to the bottom of the semiconductor chip 2 by an adhesive. In the circuit board 10, a circuit pattern including a plurality of bond fingers 12 is formed on an upper surface of the resin layer 11, and a circuit pattern including a plurality of lands 13 is formed on a bottom surface of the circuit board 10. The upper and lower circuit patterns are interconnected by conductive via holes 14. In addition, all circuit patterns except for the bond finger 12 on the upper surface and the land 13 on the bottom are coated with a cover coat 15 or the like.
한편, 상기 반도체칩(2)의 입출력패드(2a)와 상기 회로기판(10)의 본드핑거(12)는 도전성와이어(20)에 의해 전기적으로 접속되어 있다.Meanwhile, the input / output pad 2a of the semiconductor chip 2 and the bond finger 12 of the circuit board 10 are electrically connected by conductive wires 20.
또한, 상기 반도체칩(2)의 외주연 즉, 본드핑거(12)의 외주연에는 회로기판(10)의 상면에 대략 상기 도전성와이어(20)의 루프 높이보다 높게 댐(30)이 형성되어 있으며, 상기 댐(30)에는 반도체칩(2)으로 외부의 빛이 수광될 수 있도록 투명체의 글래스(40)가 접착되어 있다. 더불어 상기 회로기판(10)의 저면인 랜드(13)에는 다수의 도전성볼(60)이 융착되어 있다.In addition, a dam 30 is formed on the outer circumference of the semiconductor chip 2, that is, on the outer circumference of the bond finger 12, and is substantially higher than the loop height of the conductive wire 20 on the upper surface of the circuit board 10. The glass 30 of the transparent body is bonded to the dam 30 so that external light can be received by the semiconductor chip 2. In addition, a plurality of conductive balls 60 are fused to the land 13, which is a bottom surface of the circuit board 10.
여기서, 상기 댐(30)은 통상 세라믹, 수지류, 금속류 및 봉지재중 어느 하나로 형성되며, 최근에는 가격이나 제조상의 잇점으로 인해 봉지재를 주로 사용한다. 즉, 상기 회로기판(10)에 반도체칩(2) 등을 접착하기 전에 미리 금형 및 봉지재를 이용하여 상기 반도체칩(2)의 외주연 즉, 회로기판(10)에서 본드핑거(12)의 외주연에 일정높이의 댐(30)을 형성한다. 상기와 같이 댐(30)이 형성된 후에는 통상적으로 실시되는 반도체칩 접착, 와이어 본딩 공정 등을 수행하고 있다.Here, the dam 30 is usually formed of any one of ceramics, resins, metals and encapsulating materials, and recently, encapsulating materials are mainly used due to price or manufacturing advantages. That is, before bonding the semiconductor chip 2 or the like to the circuit board 10, the outer edge of the semiconductor chip 2, that is, the bond finger 12 of the circuit board 10, is formed by using a mold and an encapsulant in advance. A dam 30 having a predetermined height is formed at the outer circumference. After the dam 30 is formed as described above, a semiconductor chip bonding, a wire bonding process, and the like, which are commonly performed, are performed.
그러나 상기 금형 및 봉지재를 이용하여 댐을 형성하는 공정중에 상기 봉지재에 의해 회로기판의 본드핑거가 오염되는 경우가 있다. 즉, 상기 봉지재는 고압으로 금형내에 충진되기 때문에 상기 압력에 의해 봉지재가 금형과 회로기판의 접촉 부분중에서 가장 약한 부분을 따라서 외부로 약간씩 분출하게 된다. 상기와 같이 사용자의 의도와는 상관없이 회로기판의 일정 영역으로 분출된 봉지재를 통상 몰드 플래시라한다.However, during the process of forming a dam using the mold and the encapsulant, the bond finger of the circuit board may be contaminated by the encapsulant. That is, since the encapsulant is filled in the mold at high pressure, the encapsulant is ejected slightly along the weakest portion of the contact portion between the mold and the circuit board by the pressure. As described above, an encapsulant ejected into a predetermined area of a circuit board regardless of a user's intention is generally referred to as a mold flash.
상기와 같은 몰드 플래시가 본드핑거 상면에 형성되면 상기 반도체칩의 입출력패드에 본딩된 도전성 와이어의 타단이 상기 본드핑거에 본딩되지 않게 되어 반도체패키지의 불량을 야기하게 된다.When the mold flash is formed on the upper surface of the bond finger, the other end of the conductive wire bonded to the input / output pad of the semiconductor chip is not bonded to the bond finger, thereby causing a defect of the semiconductor package.
또한, 상기 회로기판의 구조는 일반적인 리드프레임의 경우와는 달리 각종 회로패턴의 유무, 커버코트의 두께 편차 등에 의해 그 면이 고르지 않아 상기와 같은 몰드 플래시가 더욱 잘 발생하는 문제점이 있다.In addition, the structure of the circuit board, unlike the case of the general lead frame, the surface is not uniform due to the presence or absence of various circuit patterns, the thickness variation of the cover coat, there is a problem that the mold flash as described above is more likely to occur.
이와 같은 몰드 플래시를 억제하기 위해 상기 금형과 상기 회로기판의 접촉 압력을 높이는 수가 있는데 이럴 경우에는 상기 금형에 의해 회로기판의 각종 회로패턴들이 끊어지거나 또는 서로 쇼트되는 문제점도 있다.In order to suppress such a mold flash, the contact pressure between the mold and the circuit board may be increased. In this case, various types of circuit patterns of the circuit board may be broken or shorted by the mold.
더불어, 상기 봉지재로 형성되는 댐은 직접 상기 회로기판의 커버코트 등에 접착됨으로써 그 접착력이 매우 저조한 문제점이 있다.In addition, the dam formed of the encapsulant is directly adhered to the cover coat of the circuit board and the like, and thus has a very low adhesive strength.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, CCD용 반도체칩을 탑재한 반도체패키지에서 글래스를 장착하기 위한 댐 형성시 회로기판의 각종 회로패턴을 보호함은 물론 몰드 플래시를 억제하고 또한 댐과 회로기판 사이의 접착력을 향상시킬 수 있는 반도체패키지를 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned problems, and protects various circuit patterns of a circuit board when forming a dam for mounting a glass in a semiconductor package equipped with a CCD semiconductor chip as well as a mold flash. To provide a semiconductor package that can suppress and improve the adhesion between the dam and the circuit board.
도1a 및 도1b는 종래의 반도체패키지를 도시한 단면도 및 사시도이다.1A and 1B are a cross-sectional view and a perspective view showing a conventional semiconductor package.
도2a 및 도2b는 본 발명에 의한 반도체패키지를 도시한 단면도이다.2A and 2B are cross-sectional views showing a semiconductor package according to the present invention.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
100, 101; 본 발명에 의한 반도체패키지100, 101; Semiconductor package according to the present invention
2; 반도체칩 2a; 입출력패드2; Semiconductor chip 2a; I / O pad
10; 회로기판 11; 수지층10; Circuit board 11; Resin layer
12; 본드핑거 13; 랜드12; Bondfinger 13; rand
14; 비아홀 15; 커버코트14; Via hole 15; Cover coat
20; 도전성와이어 30; 댐20; Conductive wire 30; dam
40; 글래스 50,51; 링40; Glass 50,51; ring
53; 제3링 60; 도전성볼53; Third ring 60; Conductive ball
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 일면에 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 저면에 접착제로 접착되어 있되, 수지층을 중심으로 상면에는 다수의 본드핑거를 포함하는 회로패턴이 형성되어 있고, 저면에는 다수의 랜드를 포함하는 회로패턴이 형성되어 있으며, 상기 상,하면의 회로패턴은 도전성 비아홀로 상호 연결된 회로기판과; 상기 반도체칩의 입출력패드와 상기 회로기판의 본드핑거를 전기적으로 접속하는 도전성와이어와; 상기 반도체칩의 외주연인 회로기판 상면에 대략 상기 도전성와이어의 루프 높이보다 높게 형성된 댐과; 상기 반도체칩으로 외부의 빛이 수광될 수 있도록 상기 댐의 상면에 접착된 글래스와; 상기 회로기판 하면의 랜드에 형성된 도전성볼로 이루어진 반도체패키지에 있어서, 상기 회로기판의 본드핑거 외주연에는 다수의 링이 일정 간격을 두고 형성되어 있고, 상기 링의 상면 일정 영역을 포함하여 상기 링 사이에 댐이 형성된 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention includes a semiconductor chip having a plurality of input / output pads formed on one surface thereof; The circuit pattern is bonded to the bottom surface of the semiconductor chip with an adhesive, the circuit pattern including a plurality of bond fingers on the top surface of the resin layer, the circuit pattern including a plurality of lands on the bottom surface is formed, The circuit pattern on the bottom surface includes: a circuit board interconnected by conductive via holes; Conductive wires electrically connecting the input / output pads of the semiconductor chip to the bond fingers of the circuit board; A dam formed on the upper surface of the circuit board, which is the outer circumference of the semiconductor chip, to be substantially higher than the loop height of the conductive wire; Glass bonded to an upper surface of the dam so that external light can be received by the semiconductor chip; In the semiconductor package consisting of a conductive ball formed in the land on the lower surface of the circuit board, a plurality of rings are formed on the outer periphery of the bond finger of the circuit board at regular intervals, including a predetermined area on the upper surface of the ring between the rings The dam is characterized in that formed.
여기서, 상기 회로기판의 본드핑거 외주연에는 커버코트가 코팅되어 있고, 상기 커버코트 상에 다수의 링이 형성될 수 있다.Here, a cover coat is coated on the outer periphery of the bond finger of the circuit board, and a plurality of rings may be formed on the cover coat.
또한, 상기 비아홀은 상기 댐과 일정 거리 이격된 안쪽에 형성되어, 상기 댐의 저면인 수지층 상면에는 회로패턴이 형성되지 않음이 바람직하다.In addition, the via hole is formed inside the spaced apart from the dam a predetermined distance, it is preferable that the circuit pattern is not formed on the upper surface of the resin layer that is the bottom of the dam.
또한, 상기 댐과 접촉하는 링의 안쪽과 본드핑거 사이에는 상기 링과 일정 거리 이격되어 제3링이 더 형성될 수 있다.In addition, a third ring may be further formed between the inner side of the ring contacting the dam and the bond finger to be spaced apart from the ring by a predetermined distance.
상기 링 또는 제3링은 세라믹, 수지류 또는 금속류 중 어느 하나로 형성됨이 바람직하다.The ring or the third ring is preferably formed of any one of ceramics, resins or metals.
상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 회로기판의 본드핑거 외주연에 다수의 링이 형성되고, 상기 링의 일정 영역을 포함하여 상기 링 사이에 봉지재로 댐을 형성함으로써 몰드 플래시에 의해 상기 본드핑거가 오염될 확률이 작아지게 된다. 또한 상기 링의 안쪽에 일정거리 이격되어 제3링을 더 형성했을 경우에는 상기 몰드 플래시에 의한 본드핑거의 오염문제는 최소화된다.According to the semiconductor package according to the present invention as described above, a plurality of rings are formed on the outer periphery of the bond finger of the circuit board, and a dam is formed between the rings, including a predetermined region of the ring, to form a mold flash. As a result, the probability that the bond finger is contaminated becomes small. In addition, when the third ring is further formed to be spaced apart from the inside of the ring, contamination of the bond finger by the mold flash is minimized.
또한, 상기 댐의 저면인 커버코트와 수지층 사이에 회로패턴을 형성하지 않고 우회시켰을 경우에는 금형의 접촉 압력에 의해 종래와 같은 회로패턴의 쇼트나 단락 문제를 고려하지 않아도 된다.When the circuit pattern is bypassed without forming a circuit pattern between the cover coat, which is the bottom of the dam, and the resin layer, the short circuit or short circuit problem of the conventional circuit pattern may not be considered due to the contact pressure of the mold.
더구나, 상기 댐이 형성되는 영역에 커버코트를 오픈시켜 상기 댐이 수지층 상면에 직접 접착되도록 함으로써 그 접착력을 향상시킬 수 있게 된다.In addition, by opening a cover coat in the area where the dam is formed, the dam can be directly bonded to the upper surface of the resin layer, thereby improving its adhesion.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도2a 및 도2b는 본 발명에 의한 반도체패키지(100,101)를 도시한 단면도이다.2A and 2B are cross-sectional views illustrating semiconductor packages 100 and 101 according to the present invention.
먼저 도2a에 도시된 반도체패키지(100)는 일면에 다수의 입출력패드(2a)가 형성된 반도체칩(2)과, 상기 반도체칩(2)의 저면에 접착제로 접착되어 있되, 수지층(11)을 중심으로 상면에는 다수의 본드핑거(12)를 포함하는 회로패턴이 형성되어 있고, 저면에는 다수의 랜드(13)를 포함하는 회로패턴이 형성되어 있으며, 상기 상,하면의 회로패턴은 도전성 비아홀(14)로 상호 연결되고, 상기 본드핑거(12) 및랜드(13)를 제외한 회로패턴 전체는 커버코트(15)로 코팅된 회로기판(10)과, 상기 반도체칩(2)의 입출력패드(2a)와 상기 회로기판(10)의 본드핑거(12)를 전기적으로 접속하는 도전성와이어(20)와, 상기 반도체칩(2)의 외주연인 회로기판(10) 상면에 대략 상기 도전성와이어(20)의 루프 높이보다 높게 형성된 댐(30)과, 상기 반도체칩(2)으로 외부의 빛이 수광될 수 있도록 상기 댐(30)의 상면에 접착된 글래스(40)와, 상기 회로기판(10) 하면의 랜드(13)에 형성된 도전성볼(60)로 이루어져 있으며, 이러한 구조는 종래와 동일하다.First, the semiconductor package 100 shown in FIG. 2A is bonded to a semiconductor chip 2 having a plurality of input / output pads 2a formed on one surface thereof, and an adhesive to a bottom surface of the semiconductor chip 2, wherein the resin layer 11 is formed. A circuit pattern including a plurality of bond fingers 12 is formed on an upper surface thereof, and a circuit pattern including a plurality of lands 13 is formed on a lower surface thereof, and the upper and lower circuit patterns include conductive via holes. And a circuit board 10 interconnected by 14 and excluding the bond finger 12 and the land 13, the circuit board 10 coated with a cover coat 15, and an input / output pad of the semiconductor chip 2. 2a) and the conductive wire 20 electrically connecting the bond fingers 12 of the circuit board 10, and the conductive wire 20 on the upper surface of the circuit board 10, which is an outer circumference of the semiconductor chip 2; The dam 30 and the semiconductor chip 2 formed higher than the loop height of the image to receive the external light If with the glass 40 bonded on the upper surface of the dam (30), the circuit board 10 consists of a land 13, the conductive ball 60 is formed on, such a structure is the same as the prior art.
다만 본 발명은 상기 회로기판(10)의 본드핑거(12) 외주연인 커버코트(15) 상면에 다수의 링(50,51)이 일정 간격을 두고 형성되어 있고, 상기 링(50,51)의 상면 일정 영역을 포함하여 상기 링(50,51) 사이에 봉지재로 댐(30)이 형성된 것이 특징이다.However, in the present invention, a plurality of rings 50 and 51 are formed at regular intervals on the top surface of the cover coat 15, which is the outer periphery of the bond finger 12 of the circuit board 10. The dam 30 is formed of an encapsulant between the rings 50 and 51 including a predetermined upper surface.
또한, 상기 다수의 링(50,51) 내측과 본드핑거(12) 사이에는 상기 링(51) 및 본드핑거(12)와 일정 거리 이격되어 제3링(53)이 더 형성됨으로써 봉지재로 댐(30) 형성시에 몰드 플래시로부터 본드핑거(12)의 오염을 억제할 수 있도록 되어 있다.In addition, a third ring 53 is formed to be spaced apart from the ring 51 and the bond finger 12 by a predetermined distance between the plurality of rings 50 and 51 and the bond finger 12. At the time of formation, the contamination of the bond finger 12 from the mold flash can be suppressed.
즉, 봉지재로 댐(30) 형성시에 상기 다수의 링(50,51)에 의해 1차적으로 몰드플래시의 흐름을 억제하고, 더불어 상기 제3링(53)에 의해 2차적으로 몰드플래시의 흐름을 억제하게 되어 본드핑거(12)의 오염 문제를 해결하게 되는 것이다.That is, when the dam 30 is formed of an encapsulant, the flow of the mold flash is primarily suppressed by the plurality of rings 50 and 51, and secondly by the third ring 53. It is to suppress the flow to solve the contamination problem of the bond finger (12).
한편, 도2b의 반도체패키지(101)를 참조하면, 댐(30), 다수의 링(50,51) 및 제3링(53) 저면에는 어떠한 회로패턴도 형성되어 있지 않을 뿐만 아니라 커버코트(15)도 모두 오픈되어 있다. 따라서 상기 다수의 링(50,51) 및 제3링(53)은 상기 수지층(11) 상면에 직접 형성되어 있을 뿐만 아니라, 댐(30) 역시 상기 수지층(11)에 직접 형성됨으로써 그 접착력이 향상된다.Meanwhile, referring to the semiconductor package 101 of FIG. 2B, the bottom surface of the dam 30, the plurality of rings 50 and 51, and the third ring 53 is not formed with any circuit pattern, and the cover coat 15 may be formed. ) Are all open. Therefore, the plurality of rings 50 and 51 and the third ring 53 are not only directly formed on the upper surface of the resin layer 11, but also the dam 30 is also directly formed on the resin layer 11, and thus its adhesive force is achieved. This is improved.
또한, 상기 댐(30), 링(50,51) 및 제3링(53) 저면의 수지층(11)은 종래보다 더욱 평평한 면을 형성함으로써 금형과 강하게 밀착 가능하고 따라서 몰드 플래시가 종래보다 적게 발생한다. 더우기, 금형과 접촉하는 회로기판(10)의 상면에는 어떠한 회로패턴도 형성되어 있지 않음으로써 금형과의 과도한 밀착에 의해 발생하던 회로패턴의 쇼트 또는 단락 문제를 고려하지 않아도 된다.In addition, the resin layer 11 at the bottom of the dam 30, the rings 50, 51, and the third ring 53 forms a more flat surface than before, so that the dam 30, the rings 50, 51 and the bottom of the third ring 53 can be tightly adhered to the mold. Occurs. Furthermore, since no circuit pattern is formed on the upper surface of the circuit board 10 in contact with the mold, there is no need to consider short circuit or short circuit problem caused by excessive contact with the mold.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기 예만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, only the examples are not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
따라서 본 발명에 의한 반도체패키지에 의하면, 회로기판의 본드핑거 외주연에 다수의 링이 형성되고, 상기 링의 일정 영역을 포함하여 상기 링 사이에 봉지재로 댐을 형성함으로써 몰드 플래시에 의해 상기 본드핑거가 오염될 확률이 작아지게 된다. 또한 상기 링의 안쪽에 일정거리 이격되어 제3링을 더 형성했을 경우에는 상기 몰드 플래시에 의한 본드핑거의 오염문제는 최소화되는 효과가 있다.Therefore, according to the semiconductor package according to the present invention, a plurality of rings are formed on the outer periphery of the bond finger of the circuit board, and a bond is formed by a mold flash by forming a dam with an encapsulant between the rings, including a predetermined area of the ring. The probability of finger contamination is reduced. In addition, when the third ring is further formed by being spaced apart from the inside of the ring, the contamination problem of the bond finger by the mold flash may be minimized.
또한, 상기 댐의 저면인 커버코트와 수지층 사이에 회로패턴을 형성하지 않고 우회시켰을 경우에는 금형의 접촉 압력에 의해 종래와 같은 회로패턴의 쇼트나 단락 문제를 고려하지 않아도 된다.When the circuit pattern is bypassed without forming a circuit pattern between the cover coat, which is the bottom of the dam, and the resin layer, the short circuit or short circuit problem of the conventional circuit pattern may not be considered due to the contact pressure of the mold.
더구나, 상기 댐이 형성되는 영역에 커버코트를 오픈시켜 상기 댐이 수지층상면에 직접 접착되도록 함으로써 그 접착력을 향상시킬 수 있다.In addition, by opening a cover coat in the area where the dam is formed, the dam may be directly bonded to the resin layer upper surface, thereby improving its adhesion.
Claims (6)
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| KR20150101571A (en) * | 2014-02-27 | 2015-09-04 | 천병태 | Image sensor chip package |
| KR20170008088A (en) | 2015-07-13 | 2017-01-23 | 박성실 | The image sensor chip package and a method of manufacturing the same |
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| KR970046901U (en) * | 1995-12-05 | 1997-07-31 | 엘지반도체주식회사 | Chip on board package |
| KR970072363A (en) * | 1996-04-01 | 1997-11-07 | 황인길 | PCB substrate structure of BGA semiconductor package |
| KR19980058592A (en) * | 1996-12-30 | 1998-10-07 | 황인길 | PCB for BGA Semiconductor Package |
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| JPH06120418A (en) * | 1992-10-07 | 1994-04-28 | Nec Corp | Manufacture of hybrid integrated circuit |
| KR960026985A (en) * | 1994-12-20 | 1996-07-22 | 황인길 | Receiving Semiconductor Package |
| KR970046901U (en) * | 1995-12-05 | 1997-07-31 | 엘지반도체주식회사 | Chip on board package |
| KR970053754A (en) * | 1995-12-28 | 1997-07-31 | 황인길 | Semiconductor Package |
| KR970072363A (en) * | 1996-04-01 | 1997-11-07 | 황인길 | PCB substrate structure of BGA semiconductor package |
| KR19980058592A (en) * | 1996-12-30 | 1998-10-07 | 황인길 | PCB for BGA Semiconductor Package |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100686824B1 (en) * | 2001-08-17 | 2007-02-23 | 앰코 테크놀로지 코리아 주식회사 | Passive component mounting structure of system in package |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010064908A (en) | 2001-07-11 |
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