TWI652808B - Multi-chip package ball grid array structure - Google Patents

Multi-chip package ball grid array structure Download PDF

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TWI652808B
TWI652808B TW106112672A TW106112672A TWI652808B TW I652808 B TWI652808 B TW I652808B TW 106112672 A TW106112672 A TW 106112672A TW 106112672 A TW106112672 A TW 106112672A TW I652808 B TWI652808 B TW I652808B
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wafer
substrate
encapsulant
package structure
array package
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TW201813066A (en
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楊若薇
辛宗憲
杜修文
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勝麗國際股份有限公司
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Abstract

一種多晶片塑膠球狀陣列封裝結構包括:基板、第一晶片、第一封膠體、擋體、第二晶片、光學元件以及第二封膠體。基板具有上表面及與上表面相對的下表面。第一晶片設置於下表面且電性連接於基板。第一封膠體包覆第一晶片。擋體以第一表面設置於下表面並包圍第一封膠體。第二晶片設置於上表面且電性連接於基板。光學元件以共晶接合結構設置於第二晶片。第二封膠體包覆第二晶片、光學元件及共晶接合結構。光學元件使得與第二晶片所感測波長範圍一致的光線通過。藉由本發明的實施,晶片上的密封及真空效果良好。 A multi-chip plastic ball array package structure includes: a substrate, a first wafer, a first encapsulant, a stopper, a second wafer, an optical component, and a second encapsulant. The substrate has an upper surface and a lower surface opposite the upper surface. The first wafer is disposed on the lower surface and electrically connected to the substrate. The first gel coats the first wafer. The blocking body is disposed on the lower surface with the first surface and surrounds the first sealing body. The second wafer is disposed on the upper surface and electrically connected to the substrate. The optical element is disposed on the second wafer in a eutectic bonding structure. The second encapsulant encapsulates the second wafer, the optical element, and the eutectic bonding structure. The optical element passes light that coincides with the wavelength range sensed by the second wafer. With the practice of the present invention, the sealing and vacuum effects on the wafer are good.

Description

多晶片塑膠球狀陣列封裝結構  Multi-chip plastic spherical array package structure  

本發明為一種多晶片塑膠球狀陣列(MCPBGA)封裝結構,特別為一種基板上下兩面皆固著晶片而能提升封裝結構可靠度的多晶片塑膠球狀陣列(MCPBGA)封裝結構。 The invention relates to a multi-chip plastic ball array (MCPBGA) package structure, in particular to a multi-chip plastic ball array (MCPBGA) package structure capable of improving the reliability of a package structure by fixing a wafer on both sides of a substrate.

由於科技快速地進步,因此也加速了影音多媒體普及化的速度,加上數位相機、數位攝影機以及數位掃瞄器…等產品大量問世,使得影像數位化成為了必然的趨勢。而影像感測器則為這些數位產品中的關鍵元件,影像感測器可用以接收光信號或影像信號,並將所接收的信號轉換成電信號後,再將電信號傳送至電路板以進行分析,使得數位產品可提供照相、攝影…等功能。 Due to the rapid advancement of technology, it has also accelerated the popularity of audio and video multimedia, and the emergence of digital cameras, digital cameras and digital scanners, etc., has made image digitization an inevitable trend. The image sensor is a key component in these digital products. The image sensor can be used to receive optical signals or image signals, and convert the received signals into electrical signals, and then transmit the electrical signals to the circuit board for processing. Analysis, so that digital products can provide functions such as photography, photography, etc.

為了要使得數位產品可滿足輕薄短小的市場需求,因此目前主要使用的影像感測器,包括了:電荷耦合元件影像感測器(CCD)、互補式金屬氧化半導體影像感測器(CMOS)…等,因此如何改善影像感測器的封裝技術,並使得影像感測器的體積可微小化,變成了影響數位產品尺寸的關鍵。 In order to make digital products meet the needs of light, thin and short, the main image sensors currently used include: charge coupled device image sensor (CCD), complementary metal oxide semiconductor image sensor (CMOS)... Etc., therefore, how to improve the packaging technology of the image sensor, and make the size of the image sensor can be miniaturized, which becomes the key to affect the size of the digital product.

此外,影像感測器封裝技術除了須提供可大量生產以及材料成本低廉的優點以外,因為影像感測器上的感光區相當敏感,所以需要以適當封裝方式加以保護避免受到塵粒與水氣的影響,如此才可確保數位產品的使用壽命及品質,進而可提高影像感測器的成像性能及封裝可靠度。 In addition, in addition to the advantages of mass production and low material cost, image sensor packaging technology, because the photosensitive area on the image sensor is quite sensitive, it needs to be protected by proper packaging to avoid dust and moisture. The impact is to ensure the longevity and quality of the digital product, which in turn improves the imaging performance and package reliability of the image sensor.

有鑑於此,如何通過結構上的改良以發展出一種封裝結構, 可以提升感測靈敏度且簡化複雜的製作工藝,以降低成本,已然成為一個重要的課題。 In view of this, how to improve the sensing sensitivity and simplify the complicated manufacturing process to reduce the cost by structural improvement has become an important issue.

本發明要解決的技術問題是提供一種多晶片塑膠球狀陣列封裝結構,提高第二晶片上的密封及真空效果,減小整體封裝面積並避免基板產生翹曲,確保產品可靠度。 The technical problem to be solved by the present invention is to provide a multi-chip plastic spherical array package structure, which improves the sealing and vacuum effect on the second wafer, reduces the overall package area and avoids warpage of the substrate, and ensures product reliability.

本發明解決其技術問題是採用以下技術方案來實現的。 The technical problem solved by the present invention is achieved by the following technical solutions.

本發明公開一種多晶片塑膠球狀陣列封裝結構,該多晶片塑膠球狀陣列封裝結構包括:基板,該基板具有上表面及與該上表面相對的下表面;第一晶片,設置於該下表面且電性連接於該基板;第一封膠體,包覆該第一晶片;擋體,該擋體以其第一表面設置於該下表面並包圍該第一封膠體;第二晶片,設置於該上表面且電性連接於該基板;光學元件,該光學元件以共晶接合結構設置於該第二晶片;以及第二封膠體,包覆該第二晶片、該光學元件及該共晶接合結構。 The present invention discloses a multi-chip plastic ball array package structure, the multi-chip plastic ball array package structure comprising: a substrate having an upper surface and a lower surface opposite to the upper surface; a first wafer disposed on the lower surface And electrically connected to the substrate; a first encapsulant covering the first wafer; a blocking body having a first surface disposed on the lower surface and surrounding the first encapsulant; and a second wafer disposed on the second substrate The upper surface is electrically connected to the substrate; the optical element is disposed on the second wafer in a eutectic bonding structure; and the second encapsulant covers the second wafer, the optical element, and the eutectic bonding structure.

本發明解決其技術問題還可採用以下技術措施進一步實現。 The technical problem of the present invention can be further realized by the following technical measures.

上述的多晶片塑膠球狀陣列封裝結構,其中該光學元件以及該第二晶片之間通過該共晶接合結構以形成真空區域,且該第二晶片具有感測部位於該真空區域。 In the above multi-wafer plastic ball array package structure, the optical element and the second wafer pass through the eutectic bonding structure to form a vacuum region, and the second wafer has a sensing portion located in the vacuum region.

上述的多晶片塑膠球狀陣列封裝結構,其中該第一晶片通過至少一第一打線電性連接於該基板,該第一封膠體覆蓋該第一晶片以及該第一打線,且該第二晶片通過至少一第二打線電性連接於該基板,該第二封膠體包覆該第二晶片、該第二打線以及該光學元件。 The multi-chip plastic ball array package structure, wherein the first wafer is electrically connected to the substrate through at least one first wire, the first sealing body covers the first wafer and the first wire, and the second chip The substrate is electrically connected to the substrate by at least one second bonding wire, and the second sealing body covers the second wafer, the second bonding wire and the optical component.

上述的多晶片塑膠球狀陣列封裝結構,其中該擋體的週邊與該基板的週邊齊平。 The above multi-chip plastic ball array package structure, wherein the periphery of the block is flush with the periphery of the substrate.

上述的多晶片塑膠球狀陣列封裝結構,其中該第二封膠體的週邊與該基板的週邊切齊。 In the above multi-chip plastic ball array package structure, the periphery of the second encapsulant is aligned with the periphery of the substrate.

上述的多晶片塑膠球狀陣列封裝結構,其中該基板的厚度大於等於該第二封膠體最大厚度的20%。 The above multi-chip plastic spherical array package structure, wherein the thickness of the substrate is greater than or equal to 20% of the maximum thickness of the second encapsulant.

上述的多晶片塑膠球狀陣列封裝結構,其中該擋體的該第一表面以黏著層黏附固設於該基板的該下表面。 In the above multi-chip plastic ball array package structure, the first surface of the stopper is adhered to the lower surface of the substrate by an adhesive layer.

上述的多晶片塑膠球狀陣列封裝結構,其中該第一封膠體的厚度小於等於該擋體加上該黏著層的厚度。 In the above multi-chip plastic ball array package structure, the thickness of the first encapsulant is less than or equal to the thickness of the stopper plus the adhesive layer.

上述的多晶片塑膠球狀陣列封裝結構,其中該第二封膠體的上緣與該光學元件上緣延伸的平面形成介於0-60度之間的夾角。 In the above multi-wafer plastic ball array package structure, the upper edge of the second encapsulant forms an angle between 0 and 60 degrees with a plane extending from the upper edge of the optical element.

上述的多晶片塑膠球狀陣列封裝結構還包括至少一個被動元件,該被動元件電性連接於該基板,且該被動元件被該第二封膠體所覆蓋。 The multi-chip plastic ball array package structure further includes at least one passive component electrically connected to the substrate, and the passive component is covered by the second encapsulant.

本發明為多晶片塑膠球狀陣列封裝結構,該多晶片塑膠球狀陣列封裝結構包括:基板、第一晶片、第一封膠體、擋體、第二晶片、光學元件以及第二封膠體。該基板具有上表面及與該上表面相對的下表面。該第一晶片設置於該下表面且電性連接於該基板。該第一封膠體包覆該第一晶片。該擋體以其第一表面設置於該下表面並包圍該第一封膠體。該第二晶片設置於該上表面且電性連接於該基板。該光學元件以共晶接合結構設置於該第二晶片。第二封膠體包覆該第二晶片、該光學元件及該共晶接合結構結構。該光學元件使得與該第二晶片所感測波長範圍一致的光線通過。 The present invention is a multi-chip plastic ball array package structure comprising: a substrate, a first wafer, a first encapsulant, a stopper, a second wafer, an optical element, and a second encapsulant. The substrate has an upper surface and a lower surface opposite the upper surface. The first wafer is disposed on the lower surface and electrically connected to the substrate. The first encapsulant encapsulates the first wafer. The blocking body is disposed on the lower surface with its first surface and surrounds the first sealing body. The second wafer is disposed on the upper surface and electrically connected to the substrate. The optical element is disposed on the second wafer in a eutectic bonding structure. The second encapsulant encapsulates the second wafer, the optical element, and the eutectic bonding structure. The optical element passes light that coincides with a wavelength range sensed by the second wafer.

藉由本發明的實施,至少可以達到下列進步功效: With the implementation of the present invention, at least the following advancements can be achieved:

不須複雜製作工藝或昂貴製造設備,實施成本低廉。 It does not require complicated manufacturing processes or expensive manufacturing equipment, and the implementation cost is low.

第二晶片上的密封及真空效果良好。 The sealing and vacuum effect on the second wafer is good.

可以解決晶片小背大或是相鄰擺放大幅增加整體封裝面積的缺點。 It can solve the disadvantage that the small back of the wafer is large or the adjacent pendulum enlarges the overall package area.

可以避免基板產生翹曲,確保產品可靠度。 It can avoid warpage of the substrate and ensure product reliability.

擋體完全包覆第一晶片及第一打線,避免第一封膠體溢膠對 焊接端點產生污染。 The stopper completely covers the first wafer and the first wire to prevent the first sealant from overflowing the welding end.

第二封膠體上緣呈特定範圍夾角θ的傾斜,可以避免第二封膠體溢膠至光學元件表面產生污染。 The upper edge of the second seal body is inclined at a specific range angle θ, which can prevent the second sealant from overflowing to the surface of the optical element to cause contamination.

為使任何熟習相關技術者瞭解本發明的技術內容並據以實施,且根據本說明書所揭露的內容、申請專利範圍及圖式,任何熟習相關技術者可輕易地理解本發明相關的目的及優點,因此將在實施方式中詳細敘述本發明的詳細特徵以及優點。 In order to make the technical content of the present invention known to those skilled in the art and to implement it, and according to the content, the patent scope and the drawings disclosed in the specification, the related objects and advantages of the present invention can be easily understood by those skilled in the art. The detailed features and advantages of the present invention will be described in detail in the embodiments.

100‧‧‧多晶片塑膠球狀陣列封裝結構 100‧‧‧Multi-chip plastic ball array package structure

10‧‧‧基板 10‧‧‧Substrate

11‧‧‧上表面 11‧‧‧ upper surface

12‧‧‧下表面 12‧‧‧ Lower surface

20‧‧‧第一晶片 20‧‧‧First chip

21‧‧‧第一打線 21‧‧‧First line

25‧‧‧第三晶片 25‧‧‧ Third chip

27‧‧‧第三打線 27‧‧‧ third line

30‧‧‧第一封膠體 30‧‧‧First gel

40‧‧‧擋體 40‧‧ ‧ body

41‧‧‧第一表面 41‧‧‧ first surface

42‧‧‧第二表面 42‧‧‧ second surface

43‧‧‧黏著層 43‧‧‧Adhesive layer

50‧‧‧焊接端點 50‧‧‧ welding endpoint

60‧‧‧第二晶片 60‧‧‧second chip

61‧‧‧第二打線 61‧‧‧second line

62‧‧‧感測部 62‧‧‧Sensor

70‧‧‧光學元件 70‧‧‧Optical components

80‧‧‧共晶接合結構 80‧‧‧ Eutectic bonding structure

81‧‧‧真空區域 81‧‧‧vacuum area

90‧‧‧第二封膠體 90‧‧‧Second seal

95‧‧‧被動組件 95‧‧‧ Passive components

d‧‧‧第一厚度 D‧‧‧first thickness

D‧‧‧第二厚度 D‧‧‧second thickness

h1‧‧‧基板厚度 H1‧‧‧ substrate thickness

h2‧‧‧第二封膠體90的最大厚度 h2‧‧‧Maximum thickness of the second seal 90

圖1為本發明實施例的一種多晶片塑膠球狀陣列封裝結構的剖視示意圖。 1 is a cross-sectional view showing a multi-chip plastic ball array package structure according to an embodiment of the present invention.

圖2為本發明實施例的另一種多晶片塑膠球狀陣列封裝結構的剖視示意圖。 2 is a cross-sectional view showing another multi-wafer plastic ball array package structure according to an embodiment of the present invention.

圖3為本發明實施例的一種第二封膠體具有傾斜角及限定第一封膠體的厚度的剖視示意圖。 3 is a cross-sectional view showing a second encapsulant having a tilt angle and defining a thickness of the first encapsulant according to an embodiment of the invention.

圖4為本發明實施例的一種基板上進一步設置被動元件的多晶片塑膠球狀陣列封裝結構的剖視示意圖。 4 is a cross-sectional view showing a multi-chip plastic ball array package structure in which a passive component is further disposed on a substrate according to an embodiment of the present invention.

圖5為本發明實施例的一種基板下表面設置兩個晶片的多晶片塑膠球狀陣列封裝結構的剖視示意圖。 FIG. 5 is a cross-sectional view showing a multi-chip plastic ball array package structure in which two wafers are disposed on a lower surface of a substrate according to an embodiment of the invention.

請參考圖1所示,為實施例的一種多晶片塑膠球狀陣列封裝結構100,其具有:基板10(Base Core);第一晶片20;第一封膠體30(First Compound);擋體40(Dam Core);第二晶片60;光學元件70;以及第二封膠體90(Second Compound)。 Please refer to FIG. 1 , which is a multi-chip plastic spherical array package structure 100 of the embodiment, which has a substrate 10 (Base Core), a first wafer 20 , a first sealing body 30 (First Compound), and a blocking body 40 . (Dam Core); second wafer 60; optical element 70; and second sealant 90 (Second Compound).

如圖1所示,基板10,其可以為塑膠基板,具有上表面11及與上表面11相對的下表面12,而基板10也可以是一個具有至少一組電路(Electric Traces)結合至少一個貫孔(Through Hole)的塑膠電路基板(Plastic PCB)。 As shown in FIG. 1, the substrate 10, which may be a plastic substrate, has an upper surface 11 and a lower surface 12 opposite to the upper surface 11, and the substrate 10 may also have at least one set of electrical traces combined with at least one pass. Plastic circuit board (Through Hole).

如圖1所示,第一晶片20,設置於基板10的下表面12,並 且可以通過至少一條第一打線21(First Bonding Wire)與基板10電性連接,至於第一晶片20設置於下表面12的方式則可以是以固設或黏著的方式為之。 As shown in FIG. 1, the first wafer 20 is disposed on the lower surface 12 of the substrate 10, and can be electrically connected to the substrate 10 through at least one first bonding wire 21 (first bonding wire), and the first wafer 20 is disposed on the lower surface. The way of 12 can be fixed or adhered.

第一晶片20可以為系統晶片,舉例來說:數位文書處理器晶片(DSP,Digital Signal Processor)或是紅外線信號處理晶片(IR Signal Processor),且第一晶片20的厚度可以大於100微米,在本實施例中,第一晶片20的厚度選擇在200微米加減10%的範圍。 The first wafer 20 can be a system wafer, for example, a digital signal processor (DSP) or an infrared signal processing chip (IR Signal Processor), and the thickness of the first wafer 20 can be greater than 100 micrometers. In this embodiment, the thickness of the first wafer 20 is selected to be in the range of 200 μm plus or minus 10%.

另一方面,將第一晶片20與基板10電性連接的第一打線21可以使用金線、銅線、導電合金線或是其他導電性佳且不易產生氧化或化學作用的金屬線。 On the other hand, the first bonding wires 21 electrically connecting the first wafer 20 and the substrate 10 may use gold wires, copper wires, conductive alloy wires or other metal wires which are excellent in conductivity and are not easily oxidized or chemically acted upon.

同樣如圖1所示,第一封膠體30(First Compound),可以完整包圍且覆蓋第一晶片20。第一封膠體30的材料可以選自為液態封膠體(Liquid Compound)或是熱固型封膠體,而且第一封膠體30具有能完全包覆並覆蓋第一晶片20的厚度,藉此達到保護第一晶片20的功效。 As also shown in FIG. 1, the first sealant 30 (First Compound) can completely surround and cover the first wafer 20. The material of the first colloid 30 may be selected from a liquid compound or a thermosetting sealant, and the first sealant 30 has a thickness that can completely cover and cover the first wafer 20, thereby achieving protection. The efficacy of the first wafer 20.

再如圖1所示,擋體40(Dam Core)具有第一表面41以及相對於第一表面41的第二表面42。擋體40通過第一表面41設置於基板10的下表面12,並且擋體40直接包圍第一封膠體30。擋體40的第二表面42上設置有與基板10電性連接的多個焊接端點50,其中焊接端點50可以為焊接球(Solder Ball)或是焊接腳墊(Solder Pad)。 As further shown in FIG. 1, the body 40 has a first surface 41 and a second surface 42 opposite the first surface 41. The blocking body 40 is disposed on the lower surface 12 of the substrate 10 through the first surface 41, and the blocking body 40 directly surrounds the first sealing body 30. A plurality of soldering end points 50 electrically connected to the substrate 10 are disposed on the second surface 42 of the blocking body 40. The soldering end points 50 may be solder balls or solder pads.

如圖1至圖3所示,擋體40的週邊可以與基板10的週邊齊平,而且擋體40的第一表面41可以透過黏著層43黏附固設於基板10的下表面12,藉由黏著層43可以用來保護基板10下表面12的電路或貫孔(圖中未顯示)。 As shown in FIG. 1 to FIG. 3, the periphery of the stopper 40 may be flush with the periphery of the substrate 10, and the first surface 41 of the stopper 40 may be adhered to the lower surface 12 of the substrate 10 through the adhesive layer 43 by The adhesive layer 43 can be used to protect the circuitry or through holes (not shown) of the lower surface 12 of the substrate 10.

如圖3所示,在本實施例當中,第一封膠體30具有第一厚度d小於等於擋體40的厚度加上黏著層43厚度所形成的第二厚度D,如此擋體40便能防止第一封膠體30溢流至擋體40的第二表 面42,進而導致焊接端點50或焊接腳墊產生污染,影響其正常功能。 As shown in FIG. 3, in the present embodiment, the first sealant 30 has a first thickness d that is less than or equal to the thickness of the stopper 40 and the second thickness D formed by the thickness of the adhesive layer 43, so that the stopper 40 can be prevented. The first gel 30 overflows to the second surface 42 of the block 40, which in turn causes contamination of the solder end 50 or the solder pads, affecting its normal function.

仍請參考圖1所示,第二晶片60例如為影像感測晶片(Image Sensor Chip),設置於(固設、黏著)基板10的上表面11,所述的第二晶片60通過第二打線61與基板10電性連接。 Still referring to FIG. 1 , the second wafer 60 is, for example, an image sensor chip disposed on the upper surface 11 of the substrate 10 , and the second wafer 60 passes through the second wire. 61 is electrically connected to the substrate 10.

再者,第二晶片60還具有感測部62,且第二晶片60以與感測部62相對的一面固設於基板10的上表面11,如此,感測部62可接收感測媒介並正常運作。 In addition, the second wafer 60 further has a sensing portion 62, and the second wafer 60 is fixed on the upper surface 11 of the substrate 10 on a side opposite to the sensing portion 62. Thus, the sensing portion 62 can receive the sensing medium and working normally.

而與第二晶片60以及基板10電性連接的第二打線61可以使用金線、銅線、導電合金線或是其他導電性佳且不易產生氧化或化學作用的金屬線。 The second wire 61 electrically connected to the second wafer 60 and the substrate 10 may be a gold wire, a copper wire, a conductive alloy wire or other metal wire which is excellent in conductivity and is not susceptible to oxidation or chemical action.

由於第二晶片60的尺寸(第二晶片60與基板10接觸面積)通常大於第一晶片20的尺寸(第一晶片20與基板10接觸面積),且第二晶片60必須以感測部62感測影像信號,如上所述的第二晶片60及第一晶片20分別固設於基板10的上表面11及下表面12,可以避免兩者相鄰擺放大幅增加整體封裝面積的缺點或是由第一晶片20上方疊置第二晶片60所產生晶片小背大的問題。 Since the size of the second wafer 60 (the contact area of the second wafer 60 and the substrate 10) is generally larger than the size of the first wafer 20 (the contact area of the first wafer 20 and the substrate 10), and the second wafer 60 must be sensed by the sensing portion 62 The image signal is as described above, and the second wafer 60 and the first wafer 20 are respectively fixed on the upper surface 11 and the lower surface 12 of the substrate 10, thereby avoiding the disadvantage that the adjacent pendulum enlargement width increases the overall package area or The problem that the wafer generated by the second wafer 60 is superposed on the first wafer 20 has a small back.

而為了可以負擔第二晶片60及第一晶片20,並且在封裝製作工藝中不會產生翹曲導致多晶片塑膠球狀陣列封裝結構100異常或失效,基板10在設計上需要具有特定的厚度h1。第二封膠體90的最大厚度h2,則是指第二封膠體90上緣與光學元件70相接處至基板10的上表面11的垂直距離。因此,基板10的厚度h1以大於等於第二封膠體90的最大厚度h2的20%為原則。在本實施例中,可以選用大於等於0.3毫米(mm)的基板10,或是選用厚度為第二封膠體90厚度的30%到80%之間的基板10。 In order to be able to afford the second wafer 60 and the first wafer 20, and no warpage in the package fabrication process causes the multi-wafer plastic ball array package structure 100 to be abnormal or failed, the substrate 10 is designed to have a specific thickness h1. . The maximum thickness h2 of the second encapsulant 90 refers to the vertical distance from the upper edge of the second encapsulant 90 to the upper surface 11 of the substrate 10 where the optical element 70 meets. Therefore, the thickness h1 of the substrate 10 is based on 20% or more of the maximum thickness h2 of the second encapsulant 90. In the present embodiment, the substrate 10 of 0.3 mm or more may be selected, or the substrate 10 having a thickness of between 30% and 80% of the thickness of the second encapsulant 90 may be selected.

而前述的第一晶片20或第二晶片60,可以為互補式金氧半導體晶片(CMOS Chip),其製作工藝成熟、使用量大、且成本較為低廉。 The first wafer 20 or the second wafer 60 may be a complementary CMOS chip, which has a mature manufacturing process, a large amount of use, and a relatively low cost.

請再參考圖1所示,光學元件70(Filter),其是以共晶接合結構80(Eutectic Joining Ring)固設於第二晶片60上,且不遮蔽第二晶片60的感測部62。 Referring to FIG. 1 again, the optical element 70 (Filter) is fixed on the second wafer 60 by the Eutectic Joining Ring 80 and does not shield the sensing portion 62 of the second wafer 60.

光學元件70可以提供特定波長範圍的光線通過,而濾除其他的光信號,消除雜光干擾並確保第二晶片60的影像感測功能。所述特定波長範圍則是與第二晶片60所能感測的光線的波長範圍一致。 The optical component 70 can provide light through a particular range of wavelengths, filtering out other optical signals, eliminating stray light interference, and ensuring image sensing functionality of the second wafer 60. The particular wavelength range is consistent with the wavelength range of light that the second wafer 60 can sense.

如此,光學元件70以及第二晶片60通過共晶接合結構80圍繞形成一個真空區域81,而第二晶片60的感測部62位於真空區域81內且不受遮蔽。 As such, the optical element 70 and the second wafer 60 are surrounded by a eutectic bonding structure 80 to form a vacuum region 81, while the sensing portion 62 of the second wafer 60 is located within the vacuum region 81 and is unobstructed.

所述的共晶接合結構80,可以選擇為一個具有真空密封的效果的焊錫環(Solder Ring),或其他金屬材質或合金材質所形成的共晶接合結構80。 The eutectic bonding structure 80 may be selected as a solder ring having a vacuum sealing effect or a eutectic bonding structure 80 formed of other metal materials or alloy materials.

以金屬材質或合金材質所形成的共晶接合結構80,其真空密封效果較業界使用的有機接著體(Organic Seal Material)更為優異,可以避免水氣進入真空區域81,並使真空區域81維持在有效的真空狀態。 The eutectic bonding structure 80 formed of a metal material or an alloy material has a vacuum sealing effect superior to that of an organic sealing material used in the industry, and can prevent moisture from entering the vacuum region 81 and maintaining the vacuum region 81. In an effective vacuum state.

請再參考圖1所示,第二封膠體90包覆第二晶片60、光學元件70及共晶接合結構80的周圍。 Referring again to FIG. 1, the second encapsulant 90 covers the periphery of the second wafer 60, the optical element 70, and the eutectic bonding structure 80.

第二封膠體90的週邊可以與基板10的週邊齊平,且第二封膠體90的材料可以選自為液態封膠體(Liquid Compound)或是熱固型封膠體,本發明並不以此為限制。 The periphery of the second encapsulant 90 may be flush with the periphery of the substrate 10, and the material of the second encapsulant 90 may be selected from a liquid compound or a thermosetting sealant, and the present invention does not limit.

請參考圖1至圖3所示,第二封膠體90的上緣可以呈特定範圍夾角θ的傾斜,且高度自第二封膠體90與光學元件70上緣交接處向邊緣遞減,如此,第二封膠體90的上緣與光學元件70上緣延伸的平面便形成一夾角θ,可以控制使第二封膠體90不會爬膠(溢膠)到光學元件70上而影響第二晶片60的感測功能,其中夾角θ可以選擇為介於0-60度之間。 Referring to FIG. 1 to FIG. 3, the upper edge of the second encapsulant 90 may be inclined at a specific range of angle θ, and the height is decreased from the junction of the second encapsulant 90 and the upper edge of the optical element 70 toward the edge. The upper edge of the second encapsulant 90 forms an angle θ with the plane extending from the upper edge of the optical element 70, and the second encapsulant 90 can be controlled to prevent the second encapsulant 90 from creeping onto the optical component 70 to affect the second wafer 60. Sensing function, wherein the angle θ can be selected to be between 0-60 degrees.

接著,請參考圖4所示,多晶片塑膠球狀陣列封裝結構的基板10的上表面11可以進一步設置一個以上的被動元件95,被動元件95除了與基板10電性相連接之外,也同時受第二封膠體90所覆蓋與保護。進一步來說,被動元件95可以為電容、電阻或其他的被動式電子元件。 Next, referring to FIG. 4, the upper surface 11 of the substrate 10 of the multi-chip plastic ball array package structure may further be provided with more than one passive component 95. In addition to being electrically connected to the substrate 10, the passive component 95 is simultaneously Covered and protected by the second sealant 90. Further, passive component 95 can be a capacitor, resistor, or other passive electronic component.

再如圖5所示,在應用需要時,多晶片塑膠球狀陣列封裝結構100的基板10下表面12也可以設置多個晶片。在本實施例中,基板10的下表面設置第一晶片20以及設置於第一晶片20上的第三晶片25,且第一晶片20以第一打線21電性連接於基板10且第三晶片25以第三打線27電性連接於基板10。 As shown in FIG. 5, a plurality of wafers may be disposed on the lower surface 12 of the substrate 10 of the multi-chip plastic ball array package structure 100 as needed for application. In this embodiment, the first wafer 20 and the third wafer 25 disposed on the first wafer 20 are disposed on the lower surface of the substrate 10, and the first wafer 20 is electrically connected to the substrate 10 and the third wafer by the first bonding wires 21 25 is electrically connected to the substrate 10 by a third wire 27 .

而設置所述第一晶片20及第三晶片25的總厚度或是第一封膠體30的第一厚度d,會小於等於擋體40的厚度加上黏著層43的厚度以形成的第二厚度D。 The total thickness of the first wafer 20 and the third wafer 25 or the first thickness d of the first encapsulant 30 is set to be less than or equal to the thickness of the stopper 40 plus the thickness of the adhesive layer 43 to form a second thickness. D.

總而言之,多晶片塑膠球狀陣列封裝結構100因為具有所述的特徵:將面積較小的第一晶片20與面積較大的第二晶片60放在基板10的兩面,第一晶片20並被擋體40所包圍;僅可讓紅外光穿透的光學元件70並以真空密封良好的共晶接合結構80固著於外線感測晶片60並露出感測部62;第二封膠體90完全包覆第二打線61並包覆於與第二晶片60及光學元件70的邊緣,第一封膠體30則完全包覆住第一晶片20以及第一打線21;第二封膠體90上緣呈特定範圍夾角θ的傾斜,亦即與光學元件70具有0-60度的夾角θ,以防止溢膠到光學元件70;基板10的厚度選擇大於0.3mm,而能承受第一晶片20及第二晶片60兩個晶片的重量,並且於製作工藝中不產生翹曲(warpage);以及第一封膠體30完全包覆第一晶片20及第一打線21,且其厚度不大於擋體40加上黏著層43的厚度,因此具備了不須複雜製作工藝或昂貴製造設備,實施成本低廉;第二晶片60的密封及真空效果良好;可以解決晶片疊置上因面積小背負面積大而使得可靠度下降,或是相鄰擺放大 幅增加整體封裝面積的缺點;可以避免基板10產生翹曲,確保產品可靠度;擋體40完全包覆第一晶片20及第一打線21,避免第一封膠體30溢膠對焊接端點50或焊接腳墊產生污染;以及第二封膠體90上緣呈特定範圍夾角θ的傾斜,可以避免第二封膠體90溢膠至光學元件70表面產生污染的優點及進步功效。 In summary, the multi-chip plastic ball array package structure 100 has the feature that the first wafer 20 having a smaller area and the second wafer 60 having a larger area are placed on both sides of the substrate 10, and the first wafer 20 is blocked. Surrounded by the body 40; only the optical element 70 through which the infrared light can pass is fixed to the outer line sensing wafer 60 and exposed to the sensing portion 62 by a vacuum-sealed eutectic bonding structure 80; the second encapsulant 90 is completely covered The second bonding wire 61 is wrapped around the edge of the second wafer 60 and the optical component 70. The first sealing body 30 completely covers the first wafer 20 and the first bonding wire 21; the upper edge of the second sealing body 90 has a specific range. The inclination of the included angle θ, that is, the angle θ of 0-60 degrees with the optical element 70, prevents the glue from overflowing to the optical element 70; the thickness of the substrate 10 is selected to be greater than 0.3 mm, and can withstand the first wafer 20 and the second wafer 60. The weight of the two wafers, and no warpage is generated in the manufacturing process; and the first encapsulant 30 completely covers the first wafer 20 and the first bonding wire 21, and the thickness thereof is not greater than the blocking body 40 plus the adhesive layer 43 thickness, so it does not require complicated manufacturing process or The manufacturing cost of the manufacturing equipment is low; the sealing and vacuum effect of the second wafer 60 is good; the reliability of the wafer stacking due to the small area of the backing area is reduced, or the reliability of the adjacent pendulum is increased. The substrate 10 can be prevented from being warped to ensure product reliability; the blocking body 40 completely covers the first wafer 20 and the first bonding wire 21 to prevent the first sealing body 30 from overflowing the welding end 50 or the welding pad; And the inclination of the upper edge of the second seal body 90 at a specific range angle θ can avoid the advantage that the second sealant 90 overflows to the surface of the optical element 70 to produce pollution and improve the effect.

而上述各實施例中,第一晶片20與第二晶片60並可以分別以晶片結合樹脂(die bond epoxy)分別固設於基板10的下表面12與上表面11。 In the above embodiments, the first wafer 20 and the second wafer 60 may be respectively fixed on the lower surface 12 and the upper surface 11 of the substrate 10 by die bond epoxy.

上述各實施例是用以說明本發明的特點,其目的在使熟習該技術者能瞭解本發明的內容並據以實施,而非限定本發明的專利範圍,故凡其他未脫離本發明所揭示的精神而完成的等效修飾或修改,仍應包含在申請專利範圍中。 The above-described embodiments are intended to be illustrative of the present invention, and are intended to be understood by those skilled in the art, and the invention is not limited by the scope of the invention. The equivalent modifications or modifications made by the spirit of the spirit should still be included in the scope of the patent application.

Claims (9)

一種多晶片塑膠球狀陣列封裝結構,包括:基板,該基板具有上表面及與該上表面相對的下表面;第一晶片,設置於該下表面且電性連接於該基板;第一封膠體,包覆該第一晶片;擋體,該擋體以其第一表面設置於該下表面並包圍該第一封膠體;第二晶片,設置於該上表面且電性連接於該基板;光學元件,該光學元件以共晶接合結構設置於該第二晶片;以及第二封膠體,包覆該第二晶片、該光學元件及該共晶接合結構;其中,該光學元件以及該第二晶片之間通過該共晶接合結構以形成真空區域,且該第二晶片具有感測部位於該真空區域。 A multi-chip plastic ball array package structure comprising: a substrate having an upper surface and a lower surface opposite to the upper surface; a first wafer disposed on the lower surface and electrically connected to the substrate; the first encapsulant The second wafer is disposed on the lower surface and surrounds the first encapsulant; the second wafer is disposed on the upper surface and electrically connected to the substrate; An element disposed on the second wafer in a eutectic bonding structure; and a second encapsulant covering the second wafer, the optical element, and the eutectic bonding structure; wherein the optical element and the second wafer The eutectic bonding structure is passed between to form a vacuum region, and the second wafer has a sensing portion located in the vacuum region. 根據請求項1所述的多晶片塑膠球狀陣列封裝結構,其中該第一晶片通過至少一第一打線電性連接於該基板,該第一封膠體覆蓋該第一晶片以及該第一打線,且該第二晶片通過至少一第二打線電性連接於該基板,該第二封膠體包覆該第二晶片、該第二打線以及該光學元件。 The multi-chip plastic ball array package structure according to claim 1, wherein the first wafer is electrically connected to the substrate through at least one first wire, the first sealing body covering the first wafer and the first wire. The second wafer is electrically connected to the substrate through at least one second wire, and the second sealing body covers the second wafer, the second wire and the optical component. 根據請求項1所述的多晶片塑膠球狀陣列封裝結構,其中該擋體的週邊與該基板的週邊齊平。 The multi-chip plastic ball array package structure according to claim 1, wherein a periphery of the stopper is flush with a periphery of the substrate. 根據請求項1所述的多晶片塑膠球狀陣列封裝結構,其中該第二封膠體的週邊與該基板的週邊切齊。 The multi-chip plastic ball array package structure according to claim 1, wherein a periphery of the second encapsulant is aligned with a periphery of the substrate. 根據請求項1所述的多晶片塑膠球狀陣列封裝結構,其中該基板的厚度大於等於該第二封膠體最大厚度的20%。 The multi-chip plastic ball array package structure according to claim 1, wherein the substrate has a thickness greater than or equal to 20% of a maximum thickness of the second encapsulant. 根據請求項1所述的多晶片塑膠球狀陣列封裝結構,其中該擋體的該第一表面以黏著層黏附固設於該基板的該下表面。 The multi-chip plastic ball array package structure according to claim 1, wherein the first surface of the stopper is adhered to the lower surface of the substrate by an adhesive layer. 根據請求項6所述的多晶片塑膠球狀陣列封裝結構,其中該第 一封膠體的厚度小於等於該擋體加上該黏著層的厚度。 The multi-chip plastic ball array package structure according to claim 6, wherein the first The thickness of a gel is less than or equal to the thickness of the body plus the adhesive layer. 根據請求項1所述的多晶片塑膠球狀陣列封裝結構,其中該第二封膠體的上緣與該光學元件上緣延伸的平面形成介於0-60度之間的夾角。 The multi-chip plastic ball array package structure according to claim 1, wherein an upper edge of the second encapsulant and an upper surface of the optical element extend at an angle of between 0 and 60 degrees. 根據請求項1所述的多晶片塑膠球狀陣列封裝結構,其還包括至少一個被動元件,該被動元件電性連接於該基板,且該被動元件被該第二封膠體所覆蓋。 The multi-chip plastic ball array package structure of claim 1, further comprising at least one passive component electrically connected to the substrate, and the passive component is covered by the second encapsulant.
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