KR100447254B1 - Manufacturing method for metal line contact plug of semiconductor devices - Google Patents
Manufacturing method for metal line contact plug of semiconductor devices Download PDFInfo
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- KR100447254B1 KR100447254B1 KR10-2001-0089211A KR20010089211A KR100447254B1 KR 100447254 B1 KR100447254 B1 KR 100447254B1 KR 20010089211 A KR20010089211 A KR 20010089211A KR 100447254 B1 KR100447254 B1 KR 100447254B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
Abstract
본 발명은 반도체소자의 금속배선 콘택 플러그 형성방법에 관한 것으로, 질화막에 대하여 산화막과 금속층의 연마 선택비가 큰 슬러리(slurry)를 이용한 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정으로 금속배선 콘택플러그를 형성함으로써 CMP 장비에 대한 의존성을 최소화하고, 웨이퍼의 주변회로영역에 형성되어 있는 비트라인이 손상되는 것을 방지하여 후속공정을 용이하게 하고, 비트라인과 저장전극 간에 브리지가 발생하는 것을 방지하여 그에 따른 소자의 동작 특성 및 신뢰성을 향상시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring contact plug of a semiconductor device, wherein the metal wiring is formed by a chemical mechanical polishing (CMP) process using a slurry having a high polishing selectivity of an oxide film and a metal layer with respect to a nitride film. Forming a contact plug minimizes dependence on CMP equipment and prevents damage to the bit lines formed in the peripheral circuit area of the wafer, facilitating subsequent processing and preventing bridges between bit lines and storage electrodes. This is a technique for improving the operation characteristics and reliability of the device accordingly.
Description
본 발명은 반도체소자의 금속배선 콘택플러그 형성방법으로서, 보다 상세하게 질화막에 대하여 금속층과 산화막의 연마 선택비가 큰 슬러리를 이용한 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정으로 금속배선 콘택플러그를 형성함으로써 패턴의 밀집도에 관계없이 금속 콘택플러그를 용이하게 분리할 수 있는 반도체소자의 화학적 기계적 연마용 슬러리 및 이를 이용한 금속배선 형성방법에 관한 것이다.The present invention provides a method for forming a metallization contact plug of a semiconductor device, and more specifically, a metallization contact plug using a chemical mechanical polishing (CMP) process using a slurry having a high polishing selectivity between a metal layer and an oxide film with respect to a nitride film. The present invention relates to a slurry for chemical mechanical polishing of a semiconductor device capable of easily separating a metal contact plug regardless of the density of a pattern by forming a and a method for forming a metal wiring using the same.
집적회로의 발달은 단위 면적(㎠) 당 약 8백만 개의 트랜지스터를 포함할 수 있을 정도로 소자 밀도가 증가되었고, 이러한 고집적화를 위해 소자 간의 연결을 가능하게 하는 고수준의 금속배선은 필수적인 것이 되었다. 이러한 다층배선의 실현은 금속배선 사이에 삽입되는 유전체를 얼마나 효과적으로 평탄화 시키느냐에 달려 있다고 할 수 있다.Advances in integrated circuits have increased device densities to include about 8 million transistors per unit area (cm 2), and high levels of metallization to enable device-to-device connections are essential for such high integration. The realization of such multilayer wiring depends on how effectively the planarization of the dielectric inserted between the metal wirings is made.
이러한 이유에서 정밀한 웨이퍼 평탄화 공정이 필요하고, 기계적 공정과 화학적인 제거를 하나의 방법으로 혼합한 CMP공정이 개발되었다. 상기 CMP공정은 나노 세라믹 입자의 화학적 작용 및 패드(pad)에 가해지는 물질적인 외력이 복합화된 기계적 제거 가공 기술이다. 상기 CMP공정은 슬러리와 패드를 이용하여 웨이퍼 표면을 정밀하게 연마시키는 공정으로 웨이퍼의 뒷면을 진공을 이용하여 부착시킨 후 웨이퍼 앞면을 패드에 압력을 가해 회전시키거나 오비탈(orbital) 또는 직선운동으로 마찰시켜 웨이퍼의 앞면을 정밀하게 연마하는 것이다.For this reason, a precise wafer planarization process is required, and a CMP process that combines mechanical and chemical removal in one method has been developed. The CMP process is a mechanical removal processing technique in which the chemical action of the nano ceramic particles and the material external force applied to the pad are combined. In the CMP process, the surface of the wafer is precisely polished by using a slurry and a pad, and the back side of the wafer is attached by vacuum, and then the front surface of the wafer is rotated by applying pressure to the pad or rubbing by orbital or linear motion. To precisely polish the front surface of the wafer.
또한, 상기 다층배선은 금속 CMP 기술에 의한 새로운 배선 기술을 필요로 하게 되었다.In addition, the multilayer wiring requires a new wiring technology by the metal CMP technology.
상기 금속 CMP에 사용되는 슬러리의 경우 금속의 표면을 식각하는 식각액(etchant)과 산화막을 형성시키는 산화제(oxidizing agent)로 구성되어있다. 금속을 CMP공정으로 제거하는 경우 단차가 낮은 부분에는 보호막(passivation layer)이 형성되어 식각액에 의해 보호되고, 단차가 높은 부분에는 보호막이 패드에 닿아 연마제의 기계적인 작용에 의해 제거되어 식각액에 노출된다. 이러한 작용이 반복되면서 금속의 CMP공정이 진행된다.The slurry used for the metal CMP is composed of an etchant for etching the surface of the metal and an oxidizing agent for forming an oxide film. When the metal is removed by the CMP process, a passivation layer is formed at the low level to protect it by the etching solution, and at the high level, the protective film touches the pad and is removed by the mechanical action of the abrasive and exposed to the etching solution. . As this action is repeated, the metal CMP process proceeds.
이하, 첨부된 도면을 참고로 하여 종래기술에 대하여 설명한다.Hereinafter, with reference to the accompanying drawings will be described in the prior art.
도 1a 내지 도 1d 는 종래기술에 따른 금속배선 콘택플러그 형성방법을 도시한 공정 단면도로서, 반도체기판(11)은 셀영역(Ⅰ) 및 주변회로영역(Ⅱ)으로 구분되어 있다.1A to 1D are cross-sectional views illustrating a method for forming a metallization contact plug according to the prior art, in which a semiconductor substrate 11 is divided into a cell region I and a peripheral circuit region II.
먼저, 반도체기판(11) 상부에 마스크절연막패턴(15)이 적층되어 있는 비트라인(13)을 형성한다. 이때, 상기 마스크절연막패턴(15)은 질화막으로 형성되고, 두께는 (t3)이다.First, the bit line 13 having the mask insulating film pattern 15 stacked thereon is formed on the semiconductor substrate 11. In this case, the mask insulating film pattern 15 is formed of a nitride film and has a thickness of (t3).
다음, 전체표면 상부에 층간절연막(17)을 형성한다. 이때, 상기 층간절연막(17)은 산화막으로 형성되고, 상기 반도체기판(11)의 셀영역(Ⅰ)에서 층간절연막(17)의 두께는 (t1)이고, 주변회로영역(Ⅱ)에서 층간절연막(17)의 두께는 (t2)로 셀영역(Ⅰ)보다 두껍게 형성된다. (도 1a 참조)Next, an interlayer insulating film 17 is formed over the entire surface. In this case, the interlayer insulating film 17 is formed of an oxide film, the thickness of the interlayer insulating film 17 in the cell region I of the semiconductor substrate 11 is (t1), and the interlayer insulating film 17 in the peripheral circuit region II. The thickness of 17 is (t2), which is thicker than the cell region (I). (See Figure 1A)
그 다음, 금속배선 콘택마스크를 식각마스크로 상기 층간절연막(17)을 식각하여 셀영역(Ⅰ)에 금속배선 콘택홀(19)을 형성한다.Next, the interlayer insulating layer 17 is etched using the metallization contact mask as an etch mask to form the metallization contact hole 19 in the cell region I.
다음, 전체표면 상부에 소정 두께의 산화막을 증착한 후 전면식각하여 상기 금속배선 콘택홀(19) 및 비트라인(13)의 측벽에 산화막 스페이서(21)를 형성한다. 이때, 상기 금속배선 콘택홀(19) 내에 형성되어 있는 비트라인(13) 상의 마스크절연막패턴(15)은 금속배선 콘택홀(19) 식각공정 및 산화막 스페이서(21)를 형성하기 위한 식각공정으로 두께가 (t4)로 감소된다. (도 1b 참조)Next, an oxide film having a predetermined thickness is deposited on the entire surface, and then etched to form an oxide film spacer 21 on sidewalls of the metal wire contact hole 19 and the bit line 13. In this case, the mask insulating film pattern 15 on the bit line 13 formed in the metal wire contact hole 19 is a thickness of the metal wire contact hole 19 and the etching process for forming the oxide spacer 21. Is reduced to (t4). (See FIG. 1B)
그 다음, 전체표면 상부에 금속층(23)을 증착한다. 이때, 상기 금속층(23)은 금속배선 콘택홀(19) 내에서 (t5) 만큼의 단차가 형성되고, 상기 마스크절연막패턴(15)으로부터 (t6)의 단차를 갖는다. (도 1c 참조)Then, the metal layer 23 is deposited on the entire surface. In this case, the metal layer 23 is formed with a step (t5) in the metal wiring contact hole 19 and has a step (t6) from the mask insulating film pattern 15. (See Figure 1C)
다음, 상기 금속층(23), 층간절연막(17) 및 소정 두께의 마스크절연막패턴(15)을 CMP공정으로 제거하여 금속배선 콘택플러그(25)를 형성한다. 이때, 상기 CMP공정으로 금속배선 콘택플러그(25)를 (P1)과 (P2)로 분리시키기 위해서는 금속을 제거하기 위한 슬러리를 이용하여 적어도 (t6)만큼의 연마공정을 실시해야 한다. 상기 슬러리는 산성이고, 산화제, 안정화제 및 연마재 등이 함유되어 있다.Next, the metal layer 23, the interlayer insulating layer 17, and the mask insulating layer pattern 15 having a predetermined thickness are removed by a CMP process to form a metal wiring contact plug 25. At this time, in order to separate the metal wire contact plug 25 into (P1) and (P2) by the CMP process, at least (t6) polishing process should be performed using a slurry for removing metal. The slurry is acidic and contains oxidizing agents, stabilizers, abrasives and the like.
그러나, CMP공정은 패턴의 밀도가 낮은 영역에서 연마속도가 빠르기 때문에 주변회로영역(Ⅱ)에 형성되어 있는 비트라인(13) 상의 마스크절연막패턴(15)이 손실되어 비트라인(13)이 노출된다. (도 1d 참조)However, in the CMP process, since the polishing speed is high in a low density region of the pattern, the mask insulating film pattern 15 on the bit line 13 formed in the peripheral circuit region II is lost and the bit line 13 is exposed. . (See FIG. 1D)
상기와 같이 종래기술에 따른 반도체소자의 금속배선 콘택 플러그 형성방법은, 금속을 제거하기 위한 슬러리를 이용하여 CMP공정을 실시하는 경우 금속층에 대한 연마속도가 산화막에 비하여 20배 이상 높기 때문에 산화막이나 질화막의 연마속도가 느려 단차가 낮은 부분의 금속층이 제대로 제거되지 않아서 금속배선 콘택플러그가 분리되지 않고, 장비 진동 현상이 발생하여 공정의 안정성이 저하되는 문제점이 있다. 또한, CMP공정은 패턴 밀도가 낮은 주변회로영역에서 연마 속도가 빠르기 때문에 금속배선 콘택플러그를 완전히 분리하기 전에 주변회로영역에 형성되어 있는 비트라인 상의 마스크절연막패턴이 손실되어 비트라인이 노출되고, 그로 인하여 소자 간에 브리지가 형성되거나, 누설전류가 증가하여 소자의 동작 특성 및 신뢰성을 저하시키는 문제점이 있다.As described above, in the method of forming a metal interconnection contact plug of a semiconductor device according to the related art, when the CMP process is performed using a slurry for removing metal, the polishing rate for the metal layer is 20 times higher than that of the oxide film. Due to the slow polishing speed, the metal layer of the low stepped portion is not properly removed, and thus the metal wire contact plug is not separated, and the vibration of equipment occurs, thereby degrading the stability of the process. In addition, since the CMP process has a high polishing rate in the peripheral circuit region having a low pattern density, the mask insulating film pattern on the bit line formed in the peripheral circuit region is lost before the metal wiring contact plug is completely disconnected, thereby exposing the bit line. Due to this, there is a problem in that bridges are formed between devices, or leakage currents increase, thereby degrading operation characteristics and reliability of the devices.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 질화막에 대하여 금속층 및 산화막의 선택비가 큰 슬러리를 이용한 CMP공정으로 금속배선 콘택플러그를 형성함으로써 금속배선 콘택플러그의 분리를 용이하게 하고, 주변회로영역에서의 연마속도를 감소시켜 공정의 안정성을 향상시키는 반도체소자의 금속배선 콘택플러그 형성방법을 제공하는데 그 목적이 있다.The present invention facilitates the separation of the metal wiring contact plug by forming a metal wiring contact plug by a CMP process using a slurry having a large selectivity of the metal layer and the oxide film with respect to the nitride film, in order to solve the above problems of the prior art. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metallization contact plug of a semiconductor device which reduces the polishing rate in a region to improve process stability.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 금속배선 콘택플러그 형성방법을 도시한 공정 단면도.1A to 1D are cross-sectional views illustrating a method for forming a metallization contact plug of a semiconductor device according to the related art.
도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 금속배선 콘택플러그 형성방법을 도시한 공정 단면도.2A to 2D are cross-sectional views illustrating a method for forming a metallization contact plug of a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>
11, 101 : 반도체기판 13, 103 : 비트라인11, 101: semiconductor substrate 13, 103: bit line
15, 105 : 마스크절연막패턴 17, 107 : 층간절연막15, 105: mask insulating film pattern 17, 107: interlayer insulating film
19, 109 : 금속배선 콘택홀 21, 111 : 산화막 스페이서19, 109: metal wiring contact holes 21, 111: oxide film spacer
23, 113 : 금속층 25, 115 : 금속배선 콘택플러그23, 113: metal layer 25, 115: metal wire contact plug
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 금속배선 콘택플러그 형성방법은,반도체기판 상부에 마스크절연막패턴이 적층되어 있는 비트라인을 형성하는 공정과,전체표면 상부에 층간절연막을 형성하는 공정과,금속배선 콘택마스크를 이용한 사진식각공정으로 상기 층간절연막을 식각하여 금속배선 콘택홀을 형성하는 공정과,상기 금속배선 콘택홀 및 비트라인 측벽에 절연막 스페이서를 형성하는 공정과,상기 금속배선 콘택홀을 매립하는 금속층을 전체표면상부에 형성하는 공정과,In order to achieve the above object, the method for forming a metal wiring contact plug of a semiconductor device according to the present invention includes forming a bit line on which a mask insulating film pattern is stacked on a semiconductor substrate, and forming an interlayer insulating film on an entire surface of the semiconductor substrate. And forming a metal wiring contact hole by etching the interlayer insulating layer by a photolithography process using a metal wiring contact mask, forming an insulating film spacer on the sidewalls of the metal wiring contact hole and the bit line. Forming a metal layer filling the holes on the entire surface;
상기 마스크절연막패턴을 노출시키는 화학적 기계적 연마공정으로 금속배선 콘택플러그를 형성하되, 질화막에 흡착이 잘되는 폴리머가 함유된 슬러리로 실시하는 공정을 포함하는 것과,Forming a metallization contact plug by a chemical mechanical polishing process of exposing the mask insulation layer pattern, and performing a slurry containing a polymer having good adsorption on the nitride layer;
상기 마스크절연막패턴은 질화막으로 형성되는 것과,The mask insulating film pattern is formed of a nitride film,
상기 층간절연막은 고밀도 플라즈마 산화막으로 형성되는 것과,The interlayer insulating film is formed of a high density plasma oxide film,
상기 금속층은 원자층증착방법에 의해 증착된 TiN막인 것과,The metal layer is a TiN film deposited by an atomic layer deposition method,
상기 슬러리는 질화막에 대한 산화막과 금속층의 선택비가 5 ∼ 20인 것과,The slurry has a selectivity ratio of 5 to 20 between the oxide film and the metal layer with respect to the nitride film,
상기 슬러리는 산도가 2 ∼ 12이고, 산화제로 H2O2가 1 ∼ 12vol% 함유되고, 안정화제로 -NH2기를 포함하는 유기분자가 0.1 ∼ 1wt% 함유되어 있는 것을 특징으로 한다.The slurry has an acidity of 2 to 12, 1 to 12 vol% of H 2 O 2 as an oxidizing agent, and 0.1 to 1 wt% of organic molecules containing -NH 2 groups as a stabilizing agent.
본 발명의 원리는 패턴의 밀도가 낮은 주변회로영역에서 CMP공정의 연마속도가 빠르기 때문에 질화막에 대하여 산화막과 금속층의 선택비가 큰 슬러리를 이용한 CMP공정으로 금속배선 콘택플러그를 형성함으로써 주변회로영역에서 연마속도를 감소시켜 금속배선 콘택플러그의 분리를 용이하게 하고, 주변회로영역에 형성되어 있는 비트라인 상의 마스크절연막패턴의 손실을 방지하는 것이다.The principle of the present invention is that in the peripheral circuit region where the density of the pattern is low, the polishing speed of the CMP process is fast, so that the metal wire contact plug is formed by the CMP process using a slurry having a high ratio of the oxide film and the metal layer to the nitride film. The speed is reduced to facilitate the removal of the metallization contact plugs and to prevent the loss of the mask insulating film pattern on the bit lines formed in the peripheral circuit region.
이하, 첨부된 도면을 참고로 하여 본 발명에 따른 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail according to the present invention.
도 3a 내지 도 3d 는 본 발명에 따른 반도체소자의 금속배선 콘택플러그 형성방법을 도시한 공정 단면도로서, 반도체기판(101)은 셀영역(Ⅰ) 및 주변회로영역(Ⅱ)으로 구분되어 있다.3A to 3D are cross-sectional views illustrating a method for forming a metal wiring contact plug of a semiconductor device according to the present invention, wherein the semiconductor substrate 101 is divided into a cell region I and a peripheral circuit region II.
먼저, 반도체기판(101) 상부에 마스크절연막패턴(105)이 적층되어 있는 비트라인(103)을 형성한다. 이때, 상기 비트라인(103)은 텅스텐으로 형성되고, 그 하부에 확산방지막인 Ti/TiN막이 형성된다. 상기 Ti/TiN막은 TiCl4를 소스로 이용하는 화학기상증착방법에 의해 형성된다.First, a bit line 103 having a mask insulating film pattern 105 stacked on the semiconductor substrate 101 is formed. In this case, the bit line 103 is formed of tungsten, and a Ti / TiN film, which is a diffusion barrier film, is formed under the bit line 103. The Ti / TiN film is formed by a chemical vapor deposition method using TiCl 4 as a source.
그리고, 상기 마스크절연막패턴(105)은 500 ∼ 600℃에서 화학기상증착방법에 의해 형성되며, (t3)의 두께로 형성된다.The mask insulating film pattern 105 is formed by a chemical vapor deposition method at 500 to 600 ° C., and has a thickness of t3.
다음, 전체표면 상부에 층간절연막(107)을 형성한다. 이때, 상기 층간절연막(107)은 산화막으로 형성되고, 상기 반도체기판(101)의 셀영역(Ⅰ)에서 층간절연막(107)의 두께는 (t1)이고, 주변회로영역(Ⅱ)에서 층간절연막(107)의 두께는 (t2)로 셀영역(Ⅰ)보다 두껍게 형성된다. (도 2a 참조)Next, an interlayer insulating film 107 is formed over the entire surface. At this time, the interlayer insulating film 107 is formed of an oxide film, the thickness of the interlayer insulating film 107 in the cell region (I) of the semiconductor substrate 101 is (t1), and the interlayer insulating film (II) in the peripheral circuit region (II). The thickness of 107 is (t2), which is thicker than the cell region (I). (See Figure 2A)
그 다음, 금속배선 콘택마스크를 식각마스크로 상기 층간절연막(107)을 식각하여 셀영역(Ⅰ)에 금속배선 콘택홀(109)을 형성한다.Next, the interlayer insulating layer 107 is etched using the metallization contact mask as an etch mask to form the metallization contact hole 109 in the cell region (I).
다음, 전체표면 상부에 소정 두께의 산화막을 증착한 후 전면식각하여 상기 금속배선 콘택홀(109) 및 비트라인(103)의 측벽에 산화막 스페이서(111)를 형성한다. 이때, 상기 금속배선 콘택홀(109) 내에 형성되어 있는 비트라인(103) 상의 마스크절연막패턴(105)은 금속배선 콘택홀(109) 식각공정 및 산화막 스페이서(111)를 형성하기 위한 식각공정으로 두께가 (t4)로 감소된다. (도 2b 참조)Next, an oxide film having a predetermined thickness is deposited on the entire surface, and then etched to form an oxide film spacer 111 on sidewalls of the metal wire contact hole 109 and the bit line 103. In this case, the mask insulating film pattern 105 on the bit line 103 formed in the metal wiring contact hole 109 is formed by an etching process for etching the metal wiring contact hole 109 and an oxide spacer 111. Is reduced to (t4). (See Figure 2b)
그 다음, 전체표면 상부에 금속층(113)을 증착한다. 이때, 상기 금속층(113)은 TiN을 원자층증착방법으로 형성한 것으로, 금속배선 콘택홀(109) 내에서 (t5) 만큼의 단차가 형성되고, 상기 마스크절연막패턴(105)으로부터 (t6)의 단차를 갖는다. (도 2c 참조)Next, a metal layer 113 is deposited on the entire surface. At this time, the metal layer 113 is formed by the atomic layer deposition method of TiN, a step of (t5) is formed in the metal wiring contact hole 109, the (t6) of the mask insulating film pattern 105 Have a step. (See Figure 2c)
다음, 상기 금속층(113), 층간절연막(107) 및 소정 두께의 마스크절연막패턴(105)을 CMP공정으로 제거하여 금속배선 콘택플러그(115)를 형성한다. 이때, 상기 CMP공정으로 금속배선 콘택플러그(115)를 (P1)과 (P2)로 분리시키기 위해서는 적어도 (t6)만큼의 연마공정을 실시해야 한다.Next, the metal layer 113, the interlayer insulating layer 107, and the mask insulating layer pattern 105 having a predetermined thickness are removed by a CMP process to form a metal wiring contact plug 115. At this time, in order to separate the metal wire contact plug 115 into (P1) and (P2) by the CMP process, at least (t6) polishing process should be performed.
상기 CMP공정은 질화막에 대한 산화막과 금속층의 선택비가 5 ∼ 20이고, 산도가 2 ∼ 12이고, 산화제로 H2O2가 1 ∼ 12vol% 함유되고, 안정화제로 EDTA(ethylene diamine tetra acetic acid)와 같이 -NH2기를 포함하는 유기분자가0.1 ∼ 1wt% 함유되고, 연마재로서 50 ∼ 300㎚ 크기의 실리카 또는 알루미나가 함유되어 있는 슬러리를 이용하여 실시된다. 이때, 상기 안정화제는 H2O2가 슬러리에 반응하는 것을 방지하기 위해 함유된다.In the CMP process, the selectivity ratio of the oxide film and the metal layer to the nitride film is 5 to 20, the acidity is 2 to 12, the H 2 O 2 is contained as an oxidant, and the stabilizer is EDTA (ethylene diamine tetra acetic acid) and Similarly, an organic molecule containing -NH 2 groups is contained in an amount of 0.1 to 1 wt%, and is carried out using a slurry containing silica or alumina having a size of 50 to 300 nm as an abrasive. At this time, the stabilizer is contained to prevent H 2 O 2 from reacting with the slurry.
특히, 상기 슬러리에 질화막에 흡착이 잘되는 폴리옥시에틸렌 알킬 에테르 계열의 폴리머를 함유시켜 질화막에 대한 산화막과 금속층의 연마선택비를 증가시킨다. 이때, 상기 폴리머는 질화막에 흡착되어 슬러리에 대한 보호막을 형성한다.In particular, the slurry contains a polyoxyethylene alkyl ether-based polymer that is easily adsorbed to the nitride film to increase the polishing selectivity of the oxide film and the metal layer with respect to the nitride film. At this time, the polymer is adsorbed on the nitride film to form a protective film for the slurry.
따라서, 상기 CMP공정은 질화막의 연마속도를 감소시켜 연마속도가 빠른 주변회로영역(Ⅱ)에서의 연마를 지연시킴으로써 셀영역(Ⅰ)에서 금속배선 콘택플러그(115)가 분리되기 전에 주변회로영역(Ⅱ) 상의 비트라인(103)이 노출되는 현상을 방지할 수 있다. (도 2d 참조)Therefore, the CMP process reduces the polishing rate of the nitride film and delays polishing in the peripheral circuit region (II) having a high polishing rate, thereby removing the peripheral circuit region (I) before the metallization contact plug 115 is separated from the cell region (I). It is possible to prevent the phenomenon in which the bit line 103 on II) is exposed. (See FIG. 2D)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 금속배선 콘택 플러그 형성방법은, 질화막에 대하여 산화막과 금속층의 연마 선택비가 큰 슬러리(slurry)를 이용한 CMP공정으로 금속배선 콘택플러그를 형성함으로써 CMP 장비에 대한 의존성을 최소화하고, 웨이퍼의 주변회로영역에 형성되어 있는 비트라인이 손상되는 것을 방지하여 후속공정을 용이하게 하고, 비트라인과 저장전극 간에 브리지가 발생하는 것을 방지하여 그에 따른 소자의 동작 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, the method for forming a metal wiring contact plug of a semiconductor device according to the present invention comprises forming a metal wiring contact plug by a CMP process using a slurry having a large polishing selectivity of an oxide film and a metal layer with respect to a nitride film. Minimize the dependency on the wafer, and prevent the bit line formed in the peripheral circuit area of the wafer from being damaged, thereby facilitating subsequent processes, and preventing the occurrence of bridges between the bit line and the storage electrode. There is an advantage of improving reliability.
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| EP1106663A1 (en) * | 1999-12-08 | 2001-06-13 | Eastman Kodak Company | Slurry for chemical mechanical polishing silicon dioxide |
| KR20020029158A (en) * | 2000-10-12 | 2002-04-18 | 주식회사 동진쎄미켐 | Chemical mechanical polishing slurry composition and planarization method using same for semiconductor device |
| KR20020051166A (en) * | 2000-12-22 | 2002-06-28 | 윤종용 | Chemical mechnical polishing slurry |
| KR20020077636A (en) * | 2001-04-05 | 2002-10-12 | 삼성전자 주식회사 | Chemical mechanical polishing slurry, and chemical mechanical polishing process and shallow trench isolation process employing the same |
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| US6114249A (en) * | 1998-03-10 | 2000-09-05 | International Business Machines Corporation | Chemical mechanical polishing of multiple material substrates and slurry having improved selectivity |
| WO2000079577A1 (en) * | 1999-06-18 | 2000-12-28 | Hitachi Chemical Co., Ltd. | Abrasive compound for cmp, method for polishing substrate and method for manufacturing semiconductor device using the same, and additive for cmp abrasive compound |
| EP1106663A1 (en) * | 1999-12-08 | 2001-06-13 | Eastman Kodak Company | Slurry for chemical mechanical polishing silicon dioxide |
| KR20020029158A (en) * | 2000-10-12 | 2002-04-18 | 주식회사 동진쎄미켐 | Chemical mechanical polishing slurry composition and planarization method using same for semiconductor device |
| KR100398141B1 (en) * | 2000-10-12 | 2003-09-13 | 아남반도체 주식회사 | Chemical mechanical polishing slurry composition and planarization method using same for semiconductor device |
| KR20020051166A (en) * | 2000-12-22 | 2002-06-28 | 윤종용 | Chemical mechnical polishing slurry |
| KR20020077636A (en) * | 2001-04-05 | 2002-10-12 | 삼성전자 주식회사 | Chemical mechanical polishing slurry, and chemical mechanical polishing process and shallow trench isolation process employing the same |
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