KR100429421B1 - Shallow Trench Forming Method for Semiconductor Isolation - Google Patents

Abstract

After forming a silicon oxide film, a polycrystalline silicon or amorphous silicon film, a silicon nitride film on the semiconductor substrate, the photosensitive film is coated, and a portion of the lower layers of the photosensitive film formed on the substrate is etched using the patterned photosensitive film. A polymer spacer is formed on sidewalls of the etched film and the photosensitive film, and trenches are formed up to a predetermined thickness of the substrate using the polymer spacers. Steps are formed between the substrate and the lower photoresist film by the spacers. Next, the polysilicon or amorphous silicon consisting of trench sidewalls, bottoms, and steps is converted into a thermal oxide film by an oxidation process. Therefore, the leakage current of the semiconductor device can be effectively suppressed, and there is an advantage that the device region becomes larger than the conventional invention due to the step difference.

Description

Shallow Trench Forming Method for Semiconductor Isolation

The present invention relates to a device isolation method for separating semiconductor devices, and more particularly to a semiconductor device separation method using a shallow trench.

Conventionally, a LOCOS (Local Oxidation of Silicon) method has been used as a semiconductor device isolation method. Since the LOCOS method uses a silicon nitride film as a mask to thermally oxidize a silicon substrate itself, the process is simple and the silicon oxide film produced is good. However, when the LOCOS method is used, a bird's beak is generated to increase the area occupied by the device isolation region, and thus the semiconductor device is arranged for high integration of semiconductor devices.

In order to overcome this problem, shallow trench isolation (STI) has been studied as a device isolation technique that replaces the LOCOS method. In the shallow trench isolation method, since trenches are made in the semiconductor substrate to fill insulators, the STI method is advantageous for miniaturization of device isolation regions, that is, high integration of semiconductor devices, since the area occupied by the device isolation regions is reduced.

A conventional method of creating the shallow trench isolation regions by creating FIGS. 1A-1D is described.

First, as shown in FIG. 1A, a silicone oxide film 2 and a silicon nitride film 3 are sequentially deposited on the semiconductor substrate 1, and then a photosensitive film is coated. Then, the photoresist film is exposed / developed through a photolithography process through a device isolation mask (not shown) to form the photoresist pattern 4 defining the semiconductor device isolation region F1.

Next, as shown in FIG. 1B, by using the photoresist pattern 4 as a mask, the exposed silicon nitride film 3, the underneath silicon oxide film 2, and the predetermined thickness of the silicon substrate 1 are etched. Form the trench 10.

Then, as shown in Fig. 1C, the photosensitive film pattern 4 on the silicon nitride film 3 is removed. Next, a thermal oxidation process is performed to form a silicon oxide film 5 on the sidewalls and bottom of the trench 10.

Subsequently, an insulating material (9 in FIG. 1D) is deposited by chemical vapor deposition on the entire surface of the semiconductor substrate 1 on which the silicon oxide film 5 is formed, to fill the trench 10, and mechanically polished for planarization. (CMP: Chemical Mechanical Polishing) is performed to remove the silicon nitride film 3 remaining on the semiconductor substrate 1, and thereafter, the remaining silicon oxide film 2 is removed to thereby remove the device isolation film (9 in FIG. 1D). Complete

Next, as shown in FIG. 1D, the gate dielectric film 6 and the polysilicon layer 7 of the transistor are sequentially formed in the element region A1 of the semiconductor substrate 1.

However, in the planarization process after filling the trench 10 with an insulating material, a predetermined thickness of the silicon oxide films 2 and 5 is essentially removed until the polycrystalline silicon film 7 is formed, so that the top edge of the device isolation film 9 is removed. Fall, so that a depression is formed as indicated by reference numeral 8.

Therefore, when a voltage is applied to the polycrystalline silicon film 7 to be the gate electrode, an electric field is concentrated in the depression 8, thereby causing a leakage current of the transistor.

Accordingly, an object of the present invention is to provide a semiconductor device isolation method capable of preventing the occurrence of leakage current due to electric field concentration at the upper edges of the device region and the device isolation region.

Another object of the present invention is to provide a semiconductor device separation method suitable for high integration by increasing the area of the device region.

1A to 1D are diagrams illustrating a semiconductor device isolation method according to the related art.

2A to 2H are diagrams illustrating a first embodiment of a method of separating a semiconductor device according to the present invention.

3A and 3B are diagrams illustrating a second embodiment of a semiconductor device isolation method according to the present invention.

4A to 4E are diagrams illustrating a third embodiment of a semiconductor device isolation method according to the present invention.

5A and 5B are diagrams illustrating a fourth embodiment of a semiconductor device isolation method according to the present invention.

6A to 6D are diagrams illustrating a fifth embodiment of a semiconductor device isolation method according to the present invention.

7A to 7D are diagrams illustrating a sixth embodiment of a semiconductor device isolation method according to the present invention.

As one example for achieving the technical problem to be achieved by the present invention, after forming a silicon oxide film, a first material layer containing a silicon component and a silicon nitride film in order on the entire surface of the semiconductor substrate, the photoresist film is coated on the silicon nitride film. Subsequently, after patterning the coated photoresist using an element isolation mask, at least one of the films under the patterned photoresist is etched, but the range from near the bottom surface of the silicon nitride film to near the top surface of the semiconductor substrate. Etch to any one of the points, and then form a polymer spacer on the sidewalls of the patterned photoresist and at least one etched lower film. The trench is formed by etching the lower layer and the semiconductor substrate which are not etched by a predetermined depth using the polymer spacer and the patterned photoresist as a mask.

As another example for achieving the technical problem to be achieved by the present invention, after forming a first silicon oxide film, a first material layer containing a silicon component, a second silicon oxide film and a silicon nitride film in order on the entire surface of the semiconductor substrate, The photosensitive film is coated on the nitride film. After patterning the coated photoresist using an element isolation mask, at least one of the films under the patterned photoresist is etched, but any of the ranges from near the bottom surface of the silicon nitride film to near the top surface of the semiconductor substrate. Etch to one point, and then form a polymer spacer on the sidewalls of the patterned photoresist and at least one etched lower film. Next, using the polymer spacer and the patterned photoresist as a mask, a trench is formed by etching an unetched lower layer and the semiconductor substrate by a predetermined depth.

In both embodiments, after the trench forming step, the patterned photoresist and the polymer spacer are removed so that a step appears on the substrate. Subsequently, the patterned photoresist and the polymer spacer are removed under an oxygen atmosphere. Oxidation may form volume-expanded oxides on the inner walls and bottom of the trench and on the sides of the first material layer. The first material layer may be used as polycrystalline silicon or amorphous silicon.

And in both embodiments, after the trench forming step, removing the patterned photoresist and the polymer spacer so that a step appears on the substrate, and in front of the resultant from which the patterned photoresist and the polymer spacer are removed. The method may further include forming a second material layer capable of forming an oxide by a thermal process under an oxygen atmosphere, and converting the material layer into a thermal oxide by oxidizing the second material layer. Here, the second material layer may be used as polycrystalline silicon or amorphous silicon.

As another example of the present invention, a silicon oxide film and a nitride film are sequentially formed on the entire surface of a semiconductor substrate, and then a photosensitive film is coated on the nitride film. The nitride film is etched after patterning the coated photoresist using an element isolation mask. In addition, a polymer having a predetermined thickness is formed on the photoresist sidewall and the nitride sidewall in a dry etching apparatus. Subsequently, the silicon oxide film and the semiconductor substrate are etched to a predetermined depth by using the photoresist film and the polymer as a mask, thereby implementing a shallow trench device isolation method in which a step is started in the silicon oxide film.

In another example, a silicon oxide film and a nitride film are sequentially formed on the entire surface of a semiconductor substrate, and then a photosensitive film is coated on the nitride film. After the patterned photoresist is patterned using an isolation mask, a predetermined thickness of the nitride film is etched. A polymer having a predetermined thickness is formed on the photoresist sidewall and the etched nitride sidewall in a dry etching apparatus. The nitride film, the silicon oxide film, and the semiconductor substrate, which are not etched, are etched to a predetermined depth by using the photosensitive film and the polymer as a mask, and a trench is etched to start a step in the nitride film. Here, the thickness of the nitride film remaining after etching a predetermined thickness of the nitride film is preferably 5% to 20% of the thickness of the deposited nitride film.

In all the above-described embodiments, the angle between the sidewall of the patterned nitride film and the lower film is 80 ° to 100 °, and the polymer spacer is bromine (Br), chlorine (Cl), fluorine (F), or nitrogen (N). ), Which is formed in dry etching equipment using at least one of the gases containing argon (Ar) or hydrogen (H). In addition, the pressure of the etching chamber for forming the polymer spacer is 2 to 100mT, the power is 150 to 700W, the etching gas ratio is CF4: CHF3: Ar is formed in the dry etching equipment under the conditions of 1: 1 to 5: 10-20. It is preferable.

In addition, in the above four examples, when the size of the patterned device isolation region F111 is 0.2 μm, the size of the step of the first material layer or the nitride film, the silicon oxide film, or the silicon substrate by the polymer spacer is It is preferable that they are 5 Hz-200 Hz. The silicon oxide film, the first silicon oxide film, or the second silicon oxide film is an oxide film formed by a thermal oxidation film by a thermal oxidation process, a chemical vapor deposition method, or an atomic layer deposition method, and the silicon oxide film, the first silicon oxide film, or the The thickness of the second silicon oxide film is 30 kPa to 300 kPa.

In addition, the polycrystalline silicon film or the amorphous silicon film may be doped with arsenic (As), black phosphorus (P) or boron (B), ion implanted, or not doped, and the thickness of the polycrystalline silicon film or amorphous silicon film may be used. Is from 10Å to 500Å.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(First embodiment)

2A to 2H, a silicon oxide film 112, a material layer 113 including a silicon component, and a silicon nitride film 114 are sequentially formed on the semiconductor substrate 111.

As the material layer 113 including the silicon component, a polycrystalline silicon film or an amorphous silicon film may be used. In this embodiment, a polycrystalline silicon film is used. The silicon oxide film 112 may be formed by a thermal oxidation process, chemical vapor deposition, or atomic layer deposition (ALD), and the thickness is preferably formed in a thickness of 30 kPa to 300 kPa. The polycrystalline silicon film (or amorphous silicon film) 113 may be doped with phosphorous or may be ion implanted with any one of arsenic (As), phosphorus (P), and boron (B). It is preferable to deposit so that the thickness may be 10 micrometers-500 micrometers. Subsequently, the photoresist layer is patterned by using a photolithography process to coat the photoresist layer on the silicon nitride layer 114 and to define the device isolation region F111.

As shown in FIG. 2B, the silicon nitride film 114 exposed by using the photosensitive film 115 as a mask is etched and removed. In this case, the angle 116 formed between the polycrystalline silicon film 113 and the sidewalls of the silicon nitride film 114 may be 80 ° to 100 °.

Next, as shown in FIG. 2C, when the polycrystalline silicon film 113 is exposed, a polymer spacer 117 having a predetermined thickness is disposed on the sidewall of the photoresist pattern 115 and the sidewall of the silicon nitride film 114 using dry etching equipment. Form. In this case, the polymer spacer 117 may be formed before etching the polycrystalline silicon film (or amorphous silicon film) 113, and may be formed during etching or after etching.

The polymer spacer may be formed of at least one or more of a gas containing bromine (Br), chlorine (Cl), fluorine (F), nitrogen (N), argon (Ar), or hydrogen (H) and dry etching equipment. It is preferable to form. For example, the polymer spacer having a thickness of 5 μm to 200 μm with a pressure of 2 to 100 mT, a power of 150 to 700 W, and an etching gas ratio of CF 4: CHF 3: Ar = 1: 1 to 5:10 to 20 ) Can be formed.

Next, as shown in FIG. 2D, the polycrystalline silicon film (or amorphous silicon film) 113 and the silicon oxide film 112 exposed by using the photosensitive film 115 and the polymer spacer 117 as a mask are etched and removed. The semiconductor substrate 111 of the device isolation region F111 is exposed.

As illustrated in FIG. 2E, the trench 128 is formed by etching the semiconductor substrate 111 exposed to a predetermined depth by using the photoresist pattern 115 and the polymer spacer 117 generated as a mask. As shown in FIG. 2F, the photosensitive film pattern 115 and the polymer spacer 117 are removed together. At this time, it is preferable that the step size (W in FIG. 2F) of the polycrystalline silicon film 113 is formed to be 5 mW to 200 mW when the element isolation region F111 is 0.2 µm.

Next, as shown in FIG. 2G, heat treatment is performed in an oxygen atmosphere to oxidize the inner wall and sidewall of the trench and the sidewall of the polysilicon layer 113 to form a thermal oxide film 123. Thus, the top edge of the trench is covered with the thermal oxide film 122.

Subsequently, an insulating film is deposited on the entire surface of the semiconductor substrate 111 using chemical vapor deposition to fill the trench. The silicon nitride film 114 and the polysilicon film 113 are removed using CMP or the like, and the substrate is planarized to form the device isolation film 121 as shown in FIG. 2H.

(Second embodiment)

After passing through the steps of FIGS. 2A to 2F, as shown in FIG. 3A, a material layer including a material capable of forming an oxide film on the entire surface of the semiconductor substrate 111 by an oxygen atmosphere, that is, a silicon component ( 118). As the material layer 118 including the silicon component, a polycrystalline silicon film or an amorphous silicon film may be used. In this embodiment, a polycrystalline silicon film of 10 Å to 500 Å was used.

Next, a thermal oxidation process is performed to thermally oxidize the polycrystalline silicon film 118 and the semiconductor substrate 111, as shown in FIG. 3B, to form the trench inner walls and the bottom, the silicon oxide film 112, and the polycrystalline silicon film 113. And a thermal oxide film 119 on the surface of the silicon nitride film 14. At this time, a part of the side surface of the polycrystalline silicon film 113 interposed between the silicon oxide film 112 and the silicon nitride film 114 is also oxidized by thermal oxidation. Therefore, the top edge 120 of the trench is also covered with the thermal oxide film 119.

However, as shown in FIG. 3B, since the trench upper edge 120 is covered with the thermal oxide film 119 having a lower etching rate or removal rate than the device isolation film 121, as shown in FIG. 2H, even after the planarization process, the device isolation film is formed. (121) The phenomenon that the upper edge is recessed does not occur.

Meanwhile, in the first to second embodiments, the polymer spacer 117 was formed before etching the polysilicon film 113. However, the polymer spacer may be formed during the etching of the polycrystalline silicon film 113, after the etching of the polysilicon film 113, during the etching of the silicon oxide film 112, or after the etching of the silicon oxide film 112.

(Third embodiment)

The process steps disclosed in FIGS. 4A to 4E are substantially the same as those in FIGS. 2A to 2H, except that the second silicon oxide film 214 is formed on the first silicon oxide film 212 in addition to the polysilicon film 213. Only the more formed points are different. The second silicon oxide film 214 is preferably an oxide film by a chemical vapor deposition method or an atomic layer deposition method, and the thickness of the second silicon oxide film 214 is preferably 30 to 300 kPa.

Reference numerals 211, 212, 213, 215, 216, 217, 219 and 220 correspond to reference numerals 111, 112, 113, 114, 115, 117, 119 and 120 of the first and second embodiments.

(Example 4)

5A and 5B, in the third embodiment, after the STI etching, the photoresist film and the polymer spacer are removed, and then the polysilicon film 218 is formed (FIG. 5A), and the thermal process is performed in an oxygen atmosphere. As shown in 5b, an oxide film 221 is formed on the trench inner walls and sidewalls and on the sides of the polysilicon film 213. Therefore, since the top edge of the trench is covered with the thermal oxide film 221, the phenomenon in which the top edge of the device isolation layer is recessed does not occur.

Meanwhile, in the third and fourth embodiments, the polymer spacer 217 was formed before etching the second silicon oxide film 214. However, the polymer spacer is, after the etching of the second silicon oxide film 214 during the etching of the second silicon oxide film 214, after the etching of the polysilicon film 213 during the etching of the polysilicon film 213, the silicon oxide film It may be formed during the etching of 212 or after the etching of the silicon oxide film 212 (FIG. 7F).

(Example 5)

6A to 6D, as shown in FIG. 6A, a silicon oxide film 312 is grown on a semiconductor substrate 311 and a silicon nitride film 313 is stacked. Next, a photoresist is coated on the silicon nitride layer 313 and the photoresist is patterned using a photolithography process to form the photoresist pattern 314. 6B, the exposed silicon nitride layer 313 is etched and removed using the photoresist pattern 314 as a mask to expose the silicon oxide layer 312 on the device isolation region F111. do.

As shown in FIG. 6C, when the silicon oxide film 312 is exposed, a polymer spacer 315 having a predetermined thickness is formed on the sidewall of the photoresist pattern 314 and the sidewall of the silicon nitride layer 313 using dry etching equipment. In this case, the polymer spacer 315 is formed before the silicon oxide layer 312 is etched, but may be formed during the etching of the silicon oxide layer 312.

Next, as shown in 6d, the silicon oxide film 312 is etched using the photoresist pattern 314 and the polymer spacer 315 as a mask, and then the exposed semiconductor substrate 311 is etched to a predetermined depth to form a trench ( 318).

Next, although not shown, a step is formed by removing the polymer spacer 315 and the photoresist pattern 314.

(Example 6)

In the fifth embodiment, all of the silicon nitride film 313 exposed using the photosensitive film pattern 314 is etched. However, in the present exemplary embodiment illustrated in FIGS. 7A to 7D, the silicon nitride film 413 is formed using the photosensitive film pattern 414. There is only a difference where only some thickness of is etched (FIG. 7B). At this time, the thickness of the silicon nitride film which is etched and remains is preferably 5% to 20% of the thickness of the deposited silicon nitride film 413. The polymer spacer 415 may be formed before etching the remaining nitride film 413 or may be formed during the nitride film etching. Reference numerals 411, 412, 413, 414 and 415 correspond to reference numerals 311, 312, 313, 314 and 315 of the fifteenth embodiment.

Table 1, shown below, compares the device characteristics of transistors having dimensions of 0.22 μm × 0.16 μm separated by device isolation films formed according to the first embodiment of the present invention and the techniques disclosed in FIGS. 1A-1D. Here the resistance value was measured by borderless contact. In forming the device isolation region according to the first embodiment and FIGS. 1A to 1D, a silicon oxide film of 150 kV, a polycrystalline silicon film of 450 kV, and a nitride film of 1500 kV were used.

TABLE 1

As described above, in the shallow trench formation process for semiconductor device isolation, the silicon substrate edge portion of the boundary between the device region and the device isolation region protrudes by a predetermined size from the sidewall of the device isolation layer through a polymer spacer and a thermal oxidation process. Current can be suppressed effectively. In addition, the device region formed by the step formed by the polymer spacer is larger than the device region of the semiconductor device having the device isolation region according to the prior art. Thus, for transistors having the same dimensions, a larger amount of current can flow through the application of the present invention, and process margins increase when forming contacts with bit lines or storage electrodes, and also device regions. This increase has the advantage that the contact resistance can be reduced.

Claims (17)

(a) forming a silicon oxide film, polycrystalline silicon or amorphous silicon and a silicon nitride film in order on the entire surface of the semiconductor substrate, and then coating a photoresist film on the silicon nitride film; (b) patterning the coated photoresist using a device isolation mask, followed by etching to any point in the range from near the top surface of the polycrystalline silicon or amorphous silicon to near the bottom surface of the silicon oxide film. Forming a polymer spacer on the sidewalls of the lower layer; (c) forming a trench by etching the unetched lower layer and the semiconductor substrate by a predetermined depth using the polymer spacer and the patterned photoresist as a mask; (d) removing the patterned photoresist and the polymer spacer so that a step is formed at a point near the bottom surface of the silicon oxide film from near the top surface of the polycrystalline silicon or amorphous silicon. Semiconductor Device Separation Method (a) forming a first silicon oxide film, polycrystalline silicon or amorphous silicon, a second silicon oxide film, and a silicon nitride film in order on the entire surface of the semiconductor substrate, and then coating a photoresist film on the silicon nitride film; (b) patterning the coated photoresist using a device isolation mask, followed by etching to any point in the range from near the top surface of the polycrystalline silicon or amorphous silicon to near the bottom surface of the silicon oxide film. Forming a polymer spacer on the sidewalls of the lower layer; (c) forming a trench by etching the unetched lower layer and the semiconductor substrate by a predetermined depth using the polymer spacer and the patterned photoresist as a mask; (d) removing the patterned photoresist and the polymer spacer so that a step is formed at a point near the bottom surface of the silicon oxide film from near the top surface of the polycrystalline silicon or amorphous silicon. Semiconductor Device Separation Method 3. The method of claim 1 or 2, wherein after the step forming step, the patterned photoresist and the resultant polymer spacer removed are oxidized in an oxygen atmosphere to have a volume on the inner wall and bottom of the trench and on the sides of polycrystalline silicon or amorphous silicon. A method for separating semiconductor devices comprising forming an expanded oxide film delete The method of claim 1 or 2, further comprising, after the step forming step, depositing polycrystalline silicon or amorphous silicon on the entire surface of the patterned photoresist and the resultant polymer spacer removed, and oxidizing the polycrystalline silicon or amorphous silicon. Method for separating a semiconductor device comprising the step of converting to a thermal oxide film delete delete delete delete The semiconductor device isolation method according to claim 1 or 2, wherein after the nitride film is etched, an angle between the sidewall of the nitride film and the lower film is 80 ° to 100 °. The method of claim 1 or 2, wherein the polymer spacer is at least one of a gas containing bromine (Br), chlorine (Cl), fluorine (F), nitrogen (N), argon (Ar) or hydrogen (H). Separation method of a semiconductor device, characterized in that formed in the dry etching equipment using more than one type of gas 12. The method of claim 11, wherein the etching chamber for forming the polymer spacer is 2 ~ 100mT, the power is 150 ~ 700W, the etching gas ratio is dry etching under the condition that the CF 4: CHF 3: Ar is 1: 1 to 5: 10-20. A method of separating a semiconductor device, characterized in that formed in the equipment. The semiconductor device isolation method according to claim 1 or 2, wherein the size of the step is 5 mW to 200 mW when the device isolation region is 0.2 µm. The method of claim 1, wherein the silicon oxide film is a thermal oxide film formed by a thermal oxidation process, an oxide film formed by a chemical vapor deposition method, or an atomic layer deposition method. 15. The method of claim 14, wherein the silicon oxide film has a thickness of 30 kPa to 300 kPa. delete The method of claim 1 or 2, wherein the polycrystalline silicon film or amorphous silicon film has a thickness of 10 kV to 500 kV.