KR100412992B1 - Ferroelectric random access memory - Google Patents

Abstract

Taking advantage of the fact that the size of the switching charge of the ferroelectric capacitor increases in proportion to the reading time, when the plateline signal of the reference cell is activated later than the plateline of the memory cell is activated, it is not possible until the detection amplifier operates. Since the switching charge of the reference cell induced in the bit line is smaller than the switching charge of the memory cell induced in the positive bit line, the reference voltage may be adjusted to come to the median value of the data "1" and "0" signals. The ferroelectric memory device of the present invention may include a memory cell including a first ferroelectric capacitor and a first switching transistor for transferring a data signal stored in the first ferroelectric capacitor to a positive bit line; A reference cell comprising a second ferroelectric capacitor having a size substantially the same as that of the first ferroelectric capacitor, and a second switching transistor for transmitting a reference signal stored in the second ferroelectric capacitor to a sub bit line; And driving means for first activating a first play line connected to a terminal of the first ferroelectric capacitor and a second play line connected to a terminal of the second ferroelectric capacitor during a predetermined time. It features.

Description

Ferroelectric memory device {FERROELECTRIC RANDOM ACCESS MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric random access memory device (FERAM), and more particularly, to a method of generating a reference voltage which is a reference for a sense amplification operation during 'read' driving of stored information.

FeRAM is a nonvolatile memory device that uses the polarization reversal and hysteresis characteristics of ferroelectric material. It has the advantage of storing the stored information even when the power is cut off. It is an ideal memory to have low power.

Ferroelectrics have two stable remnant polarization states, so that they are thinned and applied to nonvolatile memory devices. Nonvolatile memory devices using a ferroelectric thin film use the principle of inputting a signal by adjusting the direction of polarization in the direction of an applied electric field and storing digital signals 1 and 0 by the direction of residual polarization remaining when the electric field is removed. .

1 is a diagram showing a hysteresis relationship between a voltage across a capacitor using a ferroelectric material as a dielectric and an amount of induced charges.

In the ferroelectric capacitor, when the voltage at both ends is "0" V, the amount of charged charge exists in two states, thereby storing binary data even without a power supply. That is, the data "1" signal can be obtained using the switching charge Q1 and the data "0" signal can be obtained using the nonswitching charge Q0. Used as

FIG. 2 is a circuit diagram illustrating a unit cell including one capacitor 205 and one transistor 200 of a ferroelectric memory device.

The bit line BL in the color direction, the word line WL in the row direction, and the cell plate line CP are connected to the unit cell, and the unit cell has a capacitor at the intersection of the bit line and the word line. And a switching transistor connected between the one electrode of the bit line and the bit line to respond to a signal applied to the word line. A ferroelectric capacitor 205 having one electrode connected to the switching transistor and the other electrode coupled to the plate line is provided.

A voltage is applied from the cell plate line CP to the ferroelectric capacitor to induce switching charges and non-switching charges, and by controlling the transistor connected to the word line WL, data "1" or data "0" is applied to the bit line BL. send.

In the process of reading information stored in the ferroelectric memory device, if a word line (WL) is activated and a voltage is applied across the capacitor, the positive bit line BL according to the information ("0" or "1") stored in the cell is It will have different voltages V0 or V1. Since the voltages V0 and V1 are small signals, they must be amplified using a sense amplifier. In order to amplify the voltages V0 and V1, the reference voltage Vref having a value between V0 and V1 is a negative bit line. / BL). That is, the sensing amplifier detects and amplifies whether the voltage of the positive bit line BL is lower or higher than the reference voltage Vref applied to the sub bit line / BL, and amplifies the information stored in the cell. It reads whether it is "1".

Therefore, the reference voltage Vref should be made to have a value between V0 and V1, and various methods for obtaining a reference voltage having an intermediate voltage between V0 and V1 have been proposed.

3A and 3B show a reference voltage generator of a FeRAM according to the prior art.

FIG. 3A illustrates a reference cell using a ferroelectric capacitor of the same size as a ferroelectric capacitor of a memory cell, but generating a reference voltage using an average value of a data "1" signal and a data "0" signal. A reference cell 300 in which "low" data is stored and a reference cell 310 in which "high" data are stored are provided to generate a reference voltage required for a data read operation of the ferroelectric memory device. The two reference cells 300 and 310 are made up of one ferroelectric capacitor C0 or C1 and one switching transistor N0 or N1, similarly to ferroelectric memory cells.

In principle, however, this means that the mean value of the two signals must be exactly centered, but in practice the data in the memory cell is "0" due to problems such as differences in the deterioration rate of the switching charge and the nonswitching charge of the ferroelectric capacitor. There is a problem in that it is difficult to make an accurate reference signal because it does not have a median of "and data" 1. Also, a more complicated circuit is required to always write and read two reference cells as data "1" and "0", respectively.

3B is a reference cell 320 composed of one ferroelectric capacitor C2 and one switching transistor N2 according to the related art, and has the same configuration as a memory cell, but the ferroelectric capacitor C2 is a ferroelectric capacitor of a memory cell. Larger size ferroelectric capacitors. The nonswitching charge from the ferroelectric capacitor produces a reference voltage that is larger than the data "0" signal and smaller than the data "1" signal of the memory cell. The data "0" comes from the nonswitching charge, but because the capacitor is larger than that of the memory cell, a signal of the middle size between the data "0" and the data "1" is obtained, but the ferroelectric capacitor of the reference cell Since the size of the memory cell is larger than that of the memory cell, the reference cell is further affected by the deterioration of the capacitor, which adversely affects the reliability of the memory.

The present invention has been made to solve the above problems, to provide a ferroelectric memory device that can reduce the time and cost required to optimize the size of the capacitor of the reference cell using a capacitor of the same size as the memory cell. There is a purpose.

Another object of the present invention is to provide a ferroelectric memory device for reducing the change in the reference voltage due to deterioration of the capacitor to increase product life and improve reliability.

Another object of the present invention is to provide a ferroelectric memory device capable of reading data by making an accurate reference voltage with a simple circuit configuration.

1 is a diagram showing a hysteresis curve of a ferroelectric capacitor;

FIG. 2 is a circuit diagram illustrating a unit cell of a ferroelectric memory device composed of one capacitor and one transistor;

Figure 3a is a reference cell using the average value according to the prior art.

3b is a reference cell composed of one ferroelectric capacitor and one switching transistor according to the prior art;

4 shows as a function of time reading the magnitude of the switching charge of a ferroelectric capacitor according to the invention,

5 is a main circuit of FeRAM according to the present invention;

6 illustrates a delay box connected to a FeRAM main circuit according to the present invention;

7 is an exemplary view showing a delay box according to the present invention;

8 is a timing diagram of a read operation of a cell of a FeRAM according to the present invention.

* Explanation of symbols for the main parts of the drawings

600: memory cell 610: reference cell

620: address portion 630: delay box

A ferroelectric memory device of the present invention for achieving the above object comprises a memory cell comprising a first ferroelectric capacitor and a first switching transistor for transmitting a data signal stored in the first ferroelectric capacitor to a positive bit line; A reference cell comprising a second ferroelectric capacitor having a size substantially the same as that of the first ferroelectric capacitor, and a second switching transistor for transmitting a reference signal stored in the second ferroelectric capacitor to a sub bit line; And driving means for first activating a first play line connected to a terminal of the first ferroelectric capacitor and a second play line connected to a terminal of the second ferroelectric capacitor during a predetermined time. It features.

Preferably, the driving means of the present invention comprises a plate line signal for controlling the first play line; An odd number of serially connected inverter chains receiving the plate line signal; A NAND gate receiving the plate line signal as one input and receiving the output of the inverter chain as a type force; And an inverter for inverting an output of the NAND gate to provide the second plate line, wherein the first and second switching transistors are en-mo transistors, and the word line signal is a high active signal. The reference cell stores the 'high' level value charge (data "1" signal).

The reference cell may further include a third switching transistor for restoring the 'high' level voltage after the read driving is completed.

As described above, the present invention uses only the switching charge (data "1" signal) of the same size cell as the memory cell as a reference signal for sensing and amplifying the data signal of the positive bit line. Taking advantage of the fact that the size of the switching charge of the ferroelectric capacitor increases in proportion to the reading time, when the plateline signal of the reference cell is activated later than the plateline of the memory cell is activated, it is not possible until the detection amplifier operates. Since the switching charge of the reference cell induced in the bit line is smaller than the switching charge of the memory cell induced in the positive bit line, the reference voltage may be adjusted to come to the median value of the data "1" and "0" signals.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram showing the magnitude of the switching charge (data "1") of a ferroelectric capacitor according to the present invention as a function of read drive time.

As can be seen from FIG. 4, since the switching charge induced in the bit line increases in proportion to time after the plate line is activated, the bit line voltage level rises.

5 is a main circuit of the FeRAM according to the present invention. The memory cell array units 500a and 500b and the reference cell array units 510a and 510b are disposed above and below the sensing amplifier array unit 520. When the memory cell is selected in the upper portion, the data is read from the sense amplifier by comparing with the upper bit line BL voltage and the lower bit line / BL which is a reference voltage of the lower reference cell.

The reference cell is connected between the one side electrode and the bit line of the ferroelectric capacitor and the one side electrode and the reference cell connected to the switching transistor 511 in response to a signal applied to the reference word line, similarly to the memory cell. A ferroelectric capacitor 512 having the other electrode coupled to the plate line RPL of the semiconductor cell, and the ferroelectric capacitor of the reference cell has the same size as the ferroelectric capacitor of the memory cell. The reference cell is coupled between the storage node and the precharge line RPE, which are the connection terminals of the switching transistor 511 and the ferroelectric capacitor 512, to restore the voltage level of the logic 'high' value after the read drive. And a switching transistor 513 responsive to RES.

WLT and WLTB, which are not described in the drawing, are word lines, RWLT and RWLTB are word lines of reference cells, PLT and PLTB are plate lines, and REST and RESTB are restore lines. Subscripts T and B at the back of each line represent Top and Bottom.

6 is a diagram illustrating a delay box 630 connected to a FeRAM main circuit according to the present invention.

The plate line (PL enable) signal in the reference cell 610 passes through the delay box 630. Therefore, the time at which the plate line RPL of the reference cell 610 is activated becomes later than the time at which the plate line PL selected by the address unit 620 of the memory cell 600 is activated.

7 is an exemplary diagram illustrating a delay box according to the present invention.

Odd-numbered serially connected inverter chain 720 receiving a plate line enable signal, NAND gate 710 receiving the word line enable signal as one input and receiving the output of the inverter chain 720 as a type force And an inverter 700 that receives the output of the NAND gate 710 and outputs the output of the NAND gate 710 to a plate line of the reference cell 610, thereby delaying a plate line enable signal.

The characteristic of NAND logic outputs a "low" signal only when the input potentials are all "high", and outputs a "high" signal in other cases. In FIG. 7, since the NAND logics are inverted from each other, the output stage maintains a high potential when there is no signal change. However, when the input signal changes to high potential, the two input signals maintain the high potential for a predetermined delay time, and thus output a "low" signal only for a predetermined time.

8 illustrates a read drive timing diagram of the FeRAM according to the present invention.

Importantly, after the plateline signal PLT of the memory cell is activated, the detection amplifier after the plateline signal RPLB of the reference cell is activated, rather than the time width AA until the detection amplifier enable SAN is activated. The time span BB until the enable SAN is activated is short.

The overall read driving method of the present invention will be described with reference to FIG. When the lower memory cell block is selected, the method of selecting and driving the upper reference cell block is the same as in the related art. In the following description, the upper and lower parts are not distinguished.

First, the chip is enabled by the chip enable signal CEB, and the word line WLT and plate line PLT of the memory cell and the word line RWLB and plate line RPLB of the reference cell are respectively activated. At this time, as described above, the plate line PLT of the memory cell is activated first, and the plate line RPLB of the reference cell is activated after a predetermined time delay. As a result, the voltage corresponding to the data of the memory cell is induced in the positive bit line BLT, and the data of the reference cell (precharged to the 'high' level) is induced in the sub bit line after a predetermined time. Thereafter, when the sense amplifier enable signal SAN is activated before the charge of the reference cell is fully charged with the charge of the subbit line, the signal of the positive bit line is amplified by the sense amplifier so that the data value can be read. After enough data has been read, the precharge line PREB and restore line REBS of the reference cell are activated, and the word line and plateline of the memory cell and the plateline of the reference cell are disabled so that the reference cell has a 'high' level. Restore the value.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

According to the present invention, the reference voltage required for fabricating the FeRAM of one transistor 1 capacitor (1T1C) is a ferroelectric capacitor having the same size as that of a memory cell, and the width of the operational read time of the FeRAM. By adjusting, the time and cost required to optimize the size of the reference capacitor can be reduced to configure the reference signal to an optimal value between the data "1" and the data "0" of the memory cell.

In addition, compared to the case where the data "0" signal of the ferroelectric capacitor larger than the conventional memory cell is used as the reference signal, the change in the reference signal due to deterioration can be reduced, thereby increasing the life of the product and improving reliability.

In addition, since only one cell is used as compared with the conventional method of making a reference signal using an average of data "1" and data "0" signals, only a simple circuit is required and it is convenient to make an accurate reference signal.

In addition, the present invention can be applied to various types of FeRAM reference circuits, which are conventionally used, and has an advantageous effect in optimizing the size of the reference signal by merely adjusting the read time widths of the memory cells and the reference cells differently.

Claims (4)

A memory cell comprising a first ferroelectric capacitor and a first switching transistor for transmitting a data signal stored in the first ferroelectric capacitor to a positive bit line; A reference cell comprising a second ferroelectric capacitor having a size substantially the same as that of the first ferroelectric capacitor, and a second switching transistor for transmitting a reference signal stored in the second ferroelectric capacitor to a sub bit line; And Driving means for firstly activating a first play line connected to a terminal of the first ferroelectric capacitor during a read drive, and a second play line connected to a terminal of the second ferroelectric capacitor after a predetermined time. Ferroelectric memory device comprising a. The method of claim 1, The drive means, A plate line signal for controlling the first play line; An odd number of serially connected inverter chains receiving the plate line signal; A NAND gate receiving the plate line signal as one input and receiving the output of the inverter chain as a type force; And And an inverter for inverting the output of the NAND gate to provide the second plate line. The method of claim 2, And the plate line signal is a high active signal and the reference cell stores a 'high' level value. The method of claim 1, And the reference cell further comprises a third switching transistor for restoring a 'high' level voltage after the read driving is completed.