KR100318423B1 - Ferroelectric memory device - Google Patents

Abstract

According to the present invention, a plurality of word lines and a plurality of positive and sub bit lines cross each other in order to provide a ferroelectric memory device having a large voltage difference between positive and negative bit lines to increase a sensing margin of a sense amplifier and improve device reliability. And a ferroelectric memory array configured in a matrix form and arrayed into a plurality of unit memory cells including one or more ferroelectric capacitors and one or more switching elements per cell, and sensing for sensing and amplifying small signals of the positive bit line and the sub bit line. A ferroelectric memory device having an amplifier, comprising: means for driving a voltage of a plate line connected to one side of the ferroelectric capacitor to a first voltage higher than a power supply voltage of the sense amplifier before an amplifying operation of the sense amplifier.

Description

Ferroelectric memory device {FERROELECTRIC MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device using a ferroelectric memory element, and more particularly, to a ferroelectric memory device having increased sensing margin of a sense amplifier for sensing and amplifying a voltage difference between a positive bit line and a sub bit line.

For reference, the present applicant, in the application of the ferroelectric memory device and its operation method (Application No. 97-77876) filed December 30, 1997, has a higher (Vcc + The invention relates to a bit line driving method for reading data stored in a ferroelectric memory device by applying a voltage difference across both ferroelectric capacitors after precharging with a voltage, and then opening a word line. On the other hand, it is about the plate line driving that reads the data stored in the ferroelectric memory element by raising the connection cell plate line on one side of the ferroelectric capacitor to a voltage higher than the power supply voltage (Vcc + α) and applying a voltage difference across the ferroelectric capacitor.

First, the characteristics of the ferroelectric capacitor will be described.

FIG. 1 is a diagram showing the relationship between the symbols of ferroelectric capacitors and the voltages of the ferroelectric capacitor terminals A and B, showing that there is a hysteresis relationship between the voltage across the capacitor and the amount of charged charges using the ferroelectric material as a dielectric. In the ferroelectric capacitor, when the voltage at both ends is '0' V, the induced charges exist in two states, P1 and P2, so that data in binary form can be stored even without a power supply. By utilizing these characteristics, ferroelectric capacitors are used as storage means for nonvolatile memory devices. In addition, the polarization state in the ferroelectric is changed according to the direction and magnitude of the voltage applied to both ends of the ferroelectric capacitor. When a sufficiently large negative voltage V3 is applied to the ferroelectric capacitor that maintains the polarization in the 'P1' state, FIG. As the capacitor is switched along the hysteresis curve of, the polarization state changes in the 'P3' direction. If this negative voltage is removed, the voltage across the capacitor is set to '0' V, and then the state is moved to the 'P2' state. That is, in the ferroelectric capacitor, the polarization state changes in the direction of the arrow according to the voltage, and the information stored in the ferroelectric capacitor detects the magnitude of the amount of charge moved when the voltage is applied across the capacitor and makes data.

In the process of reading the information stored in the ferroelectric capacitor, if a word line is opened and a voltage difference is applied across the capacitor, the bit line (BL) is called according to the information ('0' or '1') stored in the cell. Will have different voltages V0 or V1. Since these voltages V0 and V1 are small signals, they are amplified by a sense amplifier connected between the BL line and the sub bit line (hereinafter referred to as / BL).

At this time, it is necessary to increase the sensing margin by increasing the voltage difference between the BL line and / BL for the accurate sensing operation of the sense amplifier.

Disclosure of Invention The present invention has been made based on the above-mentioned requirements, and an object thereof is to provide a ferroelectric memory device which increases sensing margin of a sense amplifier by increasing the voltage difference between positive and negative bit lines, and improves device reliability. .

1 is a diagram showing the relationship between the symbol of a ferroelectric capacitor and the amount of organic charge according to the voltage between the ferroelectric capacitor terminals A and B. FIG.

2 is a circuit schematic diagram of a ferroelectric memory device according to an embodiment of the present invention having a 2T2C cell structure.

FIG. 3 is a signal timing diagram of the ferroelectric memory device of FIG. 2 for supporting a plate line driving scheme. FIG.

4 is a diagram illustrating a voltage variation of BL with respect to a Q-V curve of a ferroelectric capacitor in a manner of overlapping the conventional case with the present invention.

5A is a diagram of a voltage change of a bit line according to the prior art for driving a plate line at Vcc.

5b is a voltage change diagram of the bit line in accordance with the present invention driving the plate line at Vcc + α.

6 is a circuit diagram of a ferroelectric memory device according to another embodiment of the present invention having a 1T1C cell structure.

7 is a diagram of a voltage change of a bit line in a ferroelectric memory device having a 1T1C cell structure.

* Description of the main parts of the drawing

200: main memory cell 201: storage cell

202: reference cell 210: sense amplifier

220: word line driver

230: plate line driving unit

In order to achieve the above object, the present invention provides a plurality of unit memory cells in which a plurality of word lines and a plurality of positive and sub bit lines cross each other to form a matrix and include one or more ferroelectric capacitors and one or more switching elements per cell. A ferroelectric memory device including an arrayed ferroelectric memory array and a sense amplifier configured to sense and amplify small signals of the positive bit line and the sub bit line, the ferroelectric memory device being connected to one side of the ferroelectric capacitor before an amplification operation of the sense amplifier. Means for driving the voltage on the plate line to a first voltage higher than the power supply voltage of the sense amplifier.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

In order to read data stored in the ferroelectric capacitor, a voltage is applied to both ends of the capacitor. The voltage is divided into a bit line drive method and a plate line drive method described above according to the application direction of the voltage. As described above, the plate line driving method maintains both voltages of the ferroelectric capacitor at ground power (0 V, hereinafter referred to as Vss) in the initial state, and then precharges BL to Vss to open the cell switching transistor. The voltage difference is applied across the ferroelectric capacitor by raising the cell plate voltage to the power supply voltage (hereinafter referred to as Vcc). In the bit line driving method, the voltage difference across the ferroelectric capacitor is maintained by maintaining both voltages of the ferroelectric capacitor at Vss in the initial state and precharging BL to Vcc and opening the word line while maintaining the cell plate voltage at Vss. Apply.

FIG. 2 is a schematic circuit diagram of a ferroelectric memory device having a 2T2C cell structure, and FIG. 3 is a signal timing diagram of the ferroelectric memory device of FIG. 2 for supporting a plate line driving scheme.

In the ferroelectric memory device according to an embodiment of the present invention, a plurality of word lines and a plurality of bit lines cross each other to form a matrix, and two ferroelectrics connected between the cell plate line PL and BL and / BL, respectively. A cell array including a plurality of main memory cells 200 including capacitors C1 and C2 and two switching transistors T1 and T2, and a sense amplifier 210 for sensing and amplifying minute signal differences between BL and / BL. Include.

The main memory cell 200 is connected between the BL and the node A and a switching transistor T1 having a word line WLN connected to the gate, and a ferroelectric capacitor connected between the node A and the plate line PL. A storage cell 201 having a C1, a switching transistor T2 connected between / BL and a node B and a word line WLN connected to a gate, and a node B and a plate line PL. It consists of a reference cell 202 with a ferroelectric capacitor C2 connected therebetween. That is, the 2T2C main memory cell 200 configured as described above is the same as two 1T1C, and the two ferroelectric capacitors C1 and C2 are always kept in opposite states to compare information with each other. I can read it. Therefore, it can be said that one 1T1C reference cell 202 is allocated to one 1T1C storage cell 201. In addition, in a 1T1C-structure DRAM and a 1T1C-structure ferroelectric memory device, which bit line is a positive bit line or a sub-bit line depending on which word line is selected, whereas in a 2T2C structure ferroelectric memory device, a BL And / BL are always fixed.

In addition, the ferroelectric memory device may further include a word line driver 220 for driving the word line WL0 or WLN and a plate line driver 230 for driving the plate line PL. do.

2 and 3, an operation of a ferroelectric memory device of a plate line driving method according to an embodiment of the present invention will be described.

First, the bit line pairs BL and / BL are floated to the 'Vss' level in the standby state (the 'A' section in FIG. 3).

Next, when the word line WL is opened and the plate line PL is driven at a high voltage (Vcc + α), a large amount of voltage is applied across the ferroelectric capacitors C1 and C2. Different voltages are induced on the ferroelectric capacitors C1 and C2 so that the state of the ferroelectric capacitors C1 and C2 is shifted from the point 'a' to the point 'b' and from the point 'a' to the point 'b' in the QV curve. In the 'B' section, the word line WL and the plate line PL are simultaneously driven, but the same result can be obtained by driving one of the two lines first.

Next, when the sense amplifier 210 is driven, the state of the ferroelectric capacitors C1 and C2 is shifted to the 'c' point and the 'c' in the QV curve, respectively, and the voltage difference between BL and / BL increases, thereby increasing the data of the cell. Will be displayed ('C' in Fig. 3).

Next, when the voltage of the plate line PL is changed to 'Vss' in order to restore the data to the cell, the state of the ferroelectric capacitors C1 and C2 is shifted to the 'd' point and the 'd' point in the QV curve, respectively. ('D' in Fig. 3)

Finally, by disabling the sense amplifier 210 and discharging BL and / BL to the 'Vss' level, the state of the ferroelectric capacitors C1 and C2 is 'e' point, 'e' respectively in the QV curve. Is transferred to the same state as the original state of capacitors C1 and C2. After the word line WL is closed, one read operation is completed ('E' in FIG. 3).

4 is a diagram illustrating a voltage change pattern of a BL with respect to a QV curve of a ferroelectric capacitor, overlapping the conventional and the present invention, and FIG. 5A illustrates a voltage change of a bit line according to the related art for driving a plate line to Vcc. 5b is a diagram of the voltage change of the bit line according to the invention driving the plate line at Vcc + α. The principle of the present invention will be described in more detail with reference to FIGS. 4, 5A and 5B.

In the initial state, if the voltage across the capacitors C1 and C2 is equal to Vss, there is no voltage difference between the two electrodes, so the two ferroelectric capacitors C1 and C2 are positioned at the points '0' and '1', respectively. Will be on.

Referring to the case where the plate line PL is driven at Vcc as in the related art, when the word line WL and the plate line PL are driven, charge flows into the BL through the switching transistor so that one side of the ferroelectric capacitor The connected voltage) becomes Vcc, whereas the BL voltage increases to equal the voltage of the other side of the ferroelectric capacitor (i.e., the storage node, A in FIG. 2), where the final voltage is the capacitance of the BL and the QV of the ferroelectric capacitor. Depends on the curve In the case of the ferroelectric capacitor whose initial state is located at the point '0', the charge amount of Q0 is moved through the switching transistor so that the storage node voltage of the ferroelectric capacitor moves from the point '0' to V0, and the BL has the initial Vss voltage. Is moved to the point V0 having a voltage of V0. At this time, the absolute value of the slope of the line connecting the points Vss0 and V0 is the capacitance of BL.

When the other one of the two ferroelectric capacitors is initially at the point '1' opposite to the capacitor, when the word line WL and the plate line PL are driven, the amount of charge of Q1 through the switching transistor This shift causes the voltage at the storage node to move from point '1' to V1, and the BL moves from the point Vss1 state with the voltage Vss to the point V1 with the voltage V1. Here, since the average slope of the Q-V curve is different depending on the initial state of the ferroelectric capacitor, Q0 and Q1 are different values, and thus V0 and V1 are different values. As a result, the initial state of the two ferroelectric capacitors differs from '0' and '1', so the voltages of the BL pair become V0 and V1, respectively.

In the present invention, the plate line PL is not driven at Vcc but at a higher voltage Vcc + α. In this case, if the initial state of the ferroelectric capacitor is' 0 ', the charge amount of Q0' is shifted when the plate line PL and the word line WL are driven, and the state of the storage node is changed from the point '0' to the point V0, In this case, it moves from the point Vss + α0 having the initial Vss voltage to V0 '. The reason why Q0 'is larger than Q0, that is, the voltage of V0' is higher than V0 is because the capacitance of BL is higher than that of plate line PL. Since the initial state of the other ferroelectric capacitor is '1', the charge amount of Q1 'is moved through the switching transistor during the driving of the word line WL and the plate line PL, so that the state of the storage node is changed from the point' 1 'to the point V1'. In the case of BL, it moves from the point Vss + α1 having the initial Vss voltage to V1 '. At this time, the voltage V1 'is higher than V1.

Here, it can be seen that the voltage difference between V1 'and V0' (V1'-V0 ', ΔV') is greater than the voltage difference between V1 and V0 (V1-V0, ΔV), because the QV curve of the ferroelectric capacitor Because the slope of the straight line connecting points V0 and V0 'is always smaller than the slope of the straight line connecting points V1 and V1', the width of the voltage where V0 changes to V0 'is the width of the voltage that V1 changes to V1'. It is always larger, and consequently V1'-V0 'is always larger than V1-V0. As described above, in the present invention, the voltage difference between BL pairs corresponding to '0' and '1' is increased by increasing the driving voltage of the plate line PL, thereby increasing the sensing margin, thereby increasing the reliability of the device. To improve.

6 is a circuit diagram of a ferroelectric memory device according to another embodiment of the present invention having a 1T1C cell structure, and FIG. 7 is a diagram illustrating a voltage change of a bit line in a ferroelectric memory device having a 1T1C cell structure.

The read timing diagram of the 1T1C memory cell of FIG. 6 is the same as the timing chart of 2T2C of FIG. 3. However, in the 1T1C memory cell structure, the / BL voltage just before the sense amplifier is turned on is made the reference voltage (Vref) having a voltage level between V0 and V1, which is the BL voltage just before the turn on of the sense amplifier, and the BL voltage is The information is read by comparing with the / BL voltage. In this case, as the voltage difference between V1 and V0 increases, the sensing margin increases by increasing the difference between V1 and Vref or V0 and Vref. In the present invention, the principle of expanding the difference between V1 and V0 is described with reference to FIG. 4. Is the same as The BL voltage change in this case is as shown in FIG.

The principle of the present invention is not limited to the structure of the unit cell of the above-described 1T1C or 2T2C ferroelectric memory device, and can be applied to various structures.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention made as described above, the voltage of the plate line is driven to a voltage Vcc + α higher than Vcc to increase the sensing margin, thereby improving the reliability of the device.

Claims (7)

In a ferroelectric memory device, One or more ferroelectric capacitors and one or more switching units per cell, wherein a plurality of word lines and a plurality of positive and sub bit lines cross each other to form a matrix, and are connected between the cell plate line and the positive bit line and the sub bit line, respectively. A ferroelectric memory array arrayed into a plurality of unit memory cells composed of elements; and And a sense amplifier configured to sense and amplify small signals of the positive bit line and the sub bit line. The first voltage higher than the power supply voltage of the sense amplifier is applied to the cell plate line immediately before the sense amplification of the sense amplifier during the read operation of the data stored in the main memory cell, and the cell plate line during the sense amplification of the sense amplifier. The ferroelectric memory device for applying a power supply voltage of the sense amplifier to the. In a ferroelectric memory device, A plurality of word lines and a plurality of bit lines cross each other to form a matrix, wherein the first and second ferroelectric capacitors and the first and second switching transistors connected between the cell plate line, the positive bit line, and the sub bit line, respectively. A memory cell array unit arrayed into a plurality of main memory cells including a; And And sensing amplification means for sensing and amplifying a minute signal difference between the positive bit line and the sub bit line. The first voltage higher than the power supply voltage of the sense amplifier is applied to the cell plate line immediately before the sense amplification of the sense amplifier during the read operation of the data stored in the main memory cell, and the cell plate line during the sense amplification of the sense amplifier. The ferroelectric memory device for applying a power supply voltage of the sense amplifier to the. The method of claim 7, wherein the main memory cell, A first switching transistor connected between the positive bit line and the first node and having a word line coupled to a gate end thereof, and having the first ferroelectric capacitor connected between the first node and the cell plate line. Cell; And A reference having the second switching transistor connected between the sub-bit line and the second node and the word line connected to a gate terminal, and the second ferroelectric capacitor connected between the second node and the cell plate line. Contains cells, The storage cell and the reference cell, A ferroelectric memory device, characterized in that for storing data states opposite to each other. The method of claim 7, wherein Word line driving means for driving the word line; And Cell plate line driving means for driving the cell plate line to the first voltage or a power supply voltage of the sense amplifier A ferroelectric memory device further comprises. The method of claim 7, wherein the sense amplification means, And a sensing amplification operation using a potential of the sub bit line induced and changed by a voltage difference across the second ferroelectric capacitor as a reference voltage. In a ferroelectric memory device, A plurality of main memories including a first ferroelectric capacitor and a first switching transistor connected to each other between a plurality of word lines and a plurality of bit lines in a matrix form and connected between a cell plate line and a positive bit line and a sub bit line, respectively. A memory cell array unit arranged into cells; And And sensing amplification means for sensing and amplifying a minute signal difference between the positive bit line and the sub bit line. In the read operation of the data stored in the main memory cell, a first voltage higher than the power supply voltage of the sense amplifier is applied to the cell plate line immediately before the sense amplification of the sense amplifier, and the cell plate line during the sense amplification of the sense amplifier. And applying a power supply voltage of the sense amplifier. The method of claim 11, Word line driving means for driving the word line; Cell plate line driving means for driving said cell plate line to said first voltage or a power supply voltage of said sense amplifier; And Reference voltage generating means for generating a reference voltage of the sense amplifier A ferroelectric memory device further comprises.