JP3020297B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory comprising a plurality of memory cells, and more particularly, a plurality of memory cells each comprising a ferroelectric capacitor and a gate transistor for reading information. The present invention relates to a semiconductor memory in which a dummy memory cell is omitted by pre-charging a bit line.

[0002]

2. Description of the Related Art Conventionally, a capacitor having an insulating layer made of a ferroelectric material (hereinafter referred to as a ferroelectric capacitor).
Has been developed for each memory cell. This type of semiconductor memory is disclosed in, for example,
201998, JP-A-64-66897, JP-A-Hei 1
No. 158691.

FIG. 8 is a circuit diagram showing one memory cell portion in a conventional semiconductor memory of this type.

In the figure, 1 is a memory cell, 10 is a dummy memory cell, 11 is a gate transistor, 12 is a ferroelectric capacitor, 30 is a word line, 35 is a plate line, and 40 is a plate line. A bit line 43 indicates an inverted bit line, and a memory cell 1 has one ferroelectric capacitor 12 and 1
The gate transistors 11 constitute a 1-bit memory cell.

First, an operation of writing information to the memory cell 1 will be described.

[0006] As shown in FIG.
When the write signal 50 of a positive voltage is supplied to the bit line 40 in the state where the voltage is maintained, and a control pulse 51 of the same positive voltage is supplied to the word line 30 during the supply period of the write signal 50, the transistor 11 A positive voltage signal 52
Occurs, and this voltage signal 52 is applied to the ferroelectric capacitor 12.
Is applied in between. At this time, in the ferroelectric capacitor 12, an electric field is applied to the ferroelectric material in the ferroelectric material by the voltage signal 52 to cause polarization. This polarization vector is directed to the transistor 11, and thereby the ferroelectric capacitor is turned on. This means that the information “1” is stored in No. 12.

On the other hand, as shown in FIG.
Is maintained at 0 V, a positive voltage write signal 54 is supplied to the plate line 35, and a positive voltage control pulse 55 is also supplied to the word line 30 during the supply period of the write signal 54.
Is supplied, the source S of the transistor 11 is maintained at the same 0 V as the bit line 40, so that a positive voltage signal is applied between the ferroelectric capacitors 12. At this time, in the ferroelectric capacitor 12, an electric field is applied to the ferroelectric material by the voltage signal to cause polarization similarly, but the polarization vector is directed to the plate line 35 in the opposite direction to the previous case. And the ferroelectric capacitor 12
Is stored as information "0".

FIG. 11 shows a hysteresis curve representing the history of the electric field and the polarization in the ferroelectric material of the ferroelectric capacitor 12.

[0009] In this figure, the horizontal axis represents the electric field, and the vertical axis represents the polarization.
Information "1" when facing to direction 1, plate line 3
5, the information "0" is stored. When the charges at that time are Q1 and Q0 (where Q1 = -Q0), these charges Q1 and Q0 are stored.
0 corresponds to the remanent polarization of the ferroelectric material. Since the remanent polarization is held even when no potential difference is applied to both ends of the ferroelectric capacitor 3, the charges Q1, By holding either of Q0, the information “1” or “0” is stored in the ferroelectric capacitor 12.
Can be stored in a nonvolatile state.

Next, an operation of reading information from the memory cell 1 will be described.

[0011] As shown in FIG.
In this state, a positive voltage read signal 56 is supplied to the word line 30, and a positive voltage control pulse 57 is supplied to the plate line 35 during the supply period of the read signal 56.
At this time, when information "1" (charge Q1) is stored in the ferroelectric capacitor 12, the voltage of the drain D of the transistor 11 changes as shown by a curve 58 in the figure, and the potential of the bit line 40 is changed. The voltage is increased in the positive direction by ΔV (= ΔQ1), and information “0” (charge Q
If (0) is stored, the voltage of the drain D of the transistor 11 changes as shown by the curve 59 in the figure, and the potential of the bit line 40 is increased in the positive direction by ΔV (= ΔQ0).

In this case, as shown, there is a relationship of ΔQ1> ΔQ0 between the potential increments ΔQ1 and ΔQ0, and the potential change of the bit line 40 is changed by the ferroelectric capacitor 12.
Is larger when the information "1" (charge Q1) is stored therein, and if this potential change in the bit line 40 is detected by the sense amplifier, the information in the ferroelectric capacitor 12 is determined by its magnitude. "1" or "0" can be read.

[0013]

In the conventional semiconductor memory, when reading information, it is necessary to determine whether the information is "1" or "0". As shown in FIG. 8, information complementary to the information stored in the memory cell 1 from which the reading is performed is stored in the inverted bit line 43 (when the information “1” is stored in the memory cell 1, the information “0” is stored). In addition, when the information “0” is stored, the dummy memory cell 10 storing the information “1”) is connected, and at the time of one read operation,
The memory cell 1 and the dummy memory cell 10 are simultaneously read, and the potential change of the inverted bit line 43 when the information of the dummy memory cell 10 is read and the potential change of the bit line 40 when the information of the memory cell 1 is read. It has been determined whether the information of the memory cell 1 is "1" or "0" by comparing the potential change.

Therefore, the conventional semiconductor memory has two memory cells 1, 10 for storing 1-bit information.
Is required, and the storage capacity for storing the original information is reduced by half.

In order to solve the above problem, a common dummy memory cell having a built-in capacitor having a capacity different from the capacity of the capacitor 12 built in each memory cell 1 is provided. By connecting to one bit line 40 together with each memory cell 1,
Readout means with a reduced number of memory cells have already been proposed.

FIG. 13 is a signal waveform diagram of each section used in the reading means for determining the storage information of the memory cell 1 to be read by using the reference potential obtained from the common dummy memory cell. .

The read signal 60, the control pulse 61, and the information "1" in the ferroelectric capacitor 12 shown in FIG.
Is stored, the drain D of the transistor 11 is stored.
12 and the voltage change curve 64 of the drain D of the transistor 11 when the information “0” is stored in the ferroelectric capacitor 12, the read signal 56, the control pulse 57, and the information It corresponds to the voltage change curve 58 when “1” and the voltage change curve 59 when information is “0”. Note that a curve 65 is a voltage obtained by a common dummy memory cell.

The read operation of the read means is substantially the same as the read operation of the memory cell 1 using the different dummy memory cells 10 described above, but the read means uses a common dummy memory cell. The reference potential 65 obtained by the information "1" and "1"
Since the potential obtained by reading "0" becomes substantially the middle potential, if the magnitude of the potential obtained from the memory cell 1 is determined based on the middle potential 65, the information of the memory cell 1 becomes "1". Or “0” can be determined.

However, the read means relatively increases the number of memory cells used for storing the original information, as compared with the read means using the read means using each of the dummy memory cells 10. However, since the number of inversions (reading) of the dummy memory cell becomes extremely large, when a ferroelectric capacitor is used as a capacitor of the dummy memory cell, the sharpness of polarization becomes large. This causes a new problem that the reference potential obtained in the dummy memory cell changes.

To solve this problem, it is conceivable to use a capacitor other than a ferroelectric capacitor as a capacitor constituting the dummy memory cell. For example, silicon dioxide (SiO ₂ ) may be used as a dielectric material of the capacitor.
If silicon dioxide is used, the capacitor becomes large because silicon dioxide has a small dielectric constant, and if a dielectric material having a higher dielectric constant than silicon dioxide is used, a new manufacturing process is required. Therefore, there is a disadvantage that the manufacturing cost of the semiconductor memory increases. Further, in the above-mentioned means, since it is necessary to generate a further intermediate potential of a minute potential obtained at the time of reading information “1” or “0”, when the new manufacturing process is adopted, Another problem arises that the intermediate potential fluctuates due to variations in conditions at the time of adoption.

[0021] The present invention has been devised to solve the problems of the various, without using a dummy memory cell, reads information from the memory cell "
The main object of the present invention is to provide a semiconductor memory capable of determining “1” and “0”.

Also, the present invention provides a method of reading or re-reading information.
It is another object to provide a semiconductor memory which can perform writing .

[0023]

In order to achieve the above-mentioned main object, the present invention provides first and second memory cells each comprising a ferroelectric capacitor and a transistor;
A first plate line connected to the ferroelectric capacitor of the memory cell, a second plate line connected to the ferroelectric capacitor of the second memory cell, and a gate of the transistor of the first memory cell. A first word line connected;
A second word line connected to the gate of the transistor of the second memory cell; a first bit line connected to the transistor of the first memory cell; and a second word line connected to the transistor of the second memory cell. 2 bit lines, and the first and second bit lines.
Semiconductor formed from the connected sense amplifier to the bit line
A memory, prior to reading of the information, the first and
The second bit line is connected to the ferroelectric capacitor of the ferroelectric capacitor.
Field and Ru comprising means for <br/> precharged to approximately equal the precharge potential to the product of the film thickness.

According to another aspect of the present invention, there is provided a ferroelectric capacitor.
And second memory cells each comprising a transistor and a transistor
Connected to the ferroelectric capacitor of the first memory cell
The first plate line and the ferroelectric core of the second memory cell.
The second plate line connected to the capacitor and the first note
A first word line connected to the gate of the transistor of the recell
Line to the gate of the transistor of the second memory cell.
Connected to the second word line and the first memory cell.
A first bit line connected to the transistor and a second memory cell;
A second bit line connected to the first transistor and a first bit line.
And a sense amplifier connected to the second bit line.
Prior to reading the information , the first and second bits
Wire and ferroelectric material of ferroelectric capacitor and its film
Precharge to precharge potential approximately equal to product of thickness
Semiconductor memory, comprising a second or first bit line
Is the inverted bit line and the second or first plate line is open.
Release the potential of the first or second plate line to 0 V
After changing the voltage to 0 V, the second or first bit line
Of the first or second bit line with the potential of
When detecting the potential with a sense amplifier, the sense amplifier
The potential of the first or second bit line immediately before the
If the voltage is higher than the precharge voltage, the first or second
Leave the potential of the plate line at 0 V and
If the voltage is lower than the voltage of the first or second plate line,
Means for performing rewriting by setting the voltage to the power supply voltage.

[0025]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIGS. 2 and 3 are hysteresis curves of an electric field and a polarization in a ferroelectric material, and a charge history diagram on the curves. It is.

The operation of the semiconductor memory according to the present invention will be described below with reference to these drawings.

First, the precharge voltage V is applied to the bit line 40.
b, and the control pulse signal 6
Supply 0. At this time, the voltage value Vp of the control pulse signal 60 is equal to the power supply voltage (Vcc), and the precharge voltage Vb is a voltage Vc (here, Vc) corresponding to the coercive electric field Ec of the ferroelectric material film of the ferroelectric capacitor 12. Therefore, when the thickness of the ferroelectric material film is d, the voltage Vc is equal to Ec × d.

Next, when a read signal 61 is supplied to the word line 30, the voltage between the ferroelectric capacitors 12 is substantially (V).
A potential of p-Vb) is applied. Here, the magnitude of the electric field in which the polarization direction in the ferroelectric material is completely inverted is represented by E
When the value is max, the coercive electric field Ec is generally about one-third of Emax, so that the following equation is satisfied: Vc = Emax / 3 (1)

Now, when the information "1" is stored in the ferroelectric capacitor 12 as an initial state and the charge Q1 is held, in order to completely invert the polarity of the charge Q1, the ferroelectric capacitor is required. 12 (V
Since p-Vb) should be larger than Emax, it suffices that Vp-Vb> Emax (2).

Here, Vp = Vcc, Vb = Vc = Vcc-
Since there is a relationship of Emax / 3, when equation (2) is modified, Vcc−Emax / 3> Emax (3) is obtained. From equation (3), Vcc> (4/3) × Emax, Or, Vcc> 4 × Vc (4) holds.

From equation (4), if Vb = Vc = Vcc / 4, that is, if the precharge voltage Vb is changed to the power supply voltage Vcc
, The polarity of the electric charge Q1 is completely inverted, the electric charge of the ferroelectric capacitor 12 changes to the position of the point A in FIG. 2, and the potential of the bit line 40 changes to the curve 62 in FIG. It changes like.

At this time, when the potential of the plate line 35 is returned to 0 V, the potential difference between the ferroelectric capacitors 12 becomes almost (-
Vb) = (− Vc), and the ferroelectric capacitor 12
Is almost 0, the difference between the current charge and the charge Q1 in the initial state becomes substantially Q1> 0, and the potential of the bit line 40 changes as shown by a curve 64 in FIG.

On the other hand, when information "0" is stored in the ferroelectric capacitor 12 as an initial state and the electric charge Q0 is held, a potential (Vp-Vb) equal to or higher than Emax is applied between the ferroelectric capacitors 12. Even if supplied, the voltage (V
Since the direction of the electric field formed by (p−Vb) is the same as the polarization direction already held, the voltage (Vp−Vb)
Vb) The charge is not inverted even by the supply, and the charge Q0
Merely changes to the position of the point A in FIG. 3, and the potential of the bit line 40 changes as shown by the curve 63 in FIG.

When the potential of the plate line 35 is returned to 0 V at this time, the electric charge of the ferroelectric capacitor 12 becomes almost 0 as in the previous case, and the difference between the current electric charge and the electric charge Q0 in the initial state is obtained. The sign is inverted so that (−Q0) <0, and the potential of the bit line 40 changes as shown by a curve 65 in FIG.

Accordingly, the charge Q stored in the initial state
1, the state of the charge changes in accordance with the polarity of Q0, and the potential of the bit line 40 also changes in proportion thereto. That is, the charge Q
When 1 is stored, the charge increases and the bit line 4
The potential of 0 is higher than the previous state as shown by the curve 62, and the charge decreases when the charge Q0 is stored, so that the potential of the bit line 40 becomes higher as shown by the curve 63. It falls from the state of.

On the other hand, the line 68 shown in FIG. 4 is the other bit line 4 to which the reference voltage (precharge voltage Vb) is supplied.
1 indicates that the reference voltage (precharge voltage Vb) is maintained at the time of reading information from the memory cell 1. Therefore, a bit is generated using this reference voltage (precharge voltage Vb). If the information on the line 40 is detected, it is possible to determine whether the information is “1” or “0”.

As described above, if the information of the memory cell 1 is detected using the precharge voltage Vb as the reference voltage, the information stored in the memory cell 1 can be read without preparing a dummy memory cell. , The judgment of "1" or "0" becomes possible.

In this case, the inverted bit line 41 used as a criterion for determination is another bit line having exactly the same configuration as the bit line 40 to be determined.
Is used as a bit line for writing or reading information in another certain period even if it is selected as an inversion bit line in a certain period.

Further, in order to rewrite information in the memory cell 1 after sensing (sensing) the information from the memory cell 1, if the information to be rewritten is “1”, the charge The state may be changed to the point A ′ of the hysteresis curve, and if the information of the rewriting is “0”, the state of the charge may be changed to the point A of the curve. That is, if the rewriting information is "1", -Emax is applied to the ferroelectric capacitor 12, and if the rewriting information is "0", Emax is applied to the ferroelectric capacitor 12. .

Therefore, when the information is "1", the potential of the bit line 40 is set to Vcc as shown by the curve 66 in FIG.
In addition, the potential of the plate line 35 is set to 0 V, and when the information is "0", the potential of the bit line 40 is set to FIG.
As shown in curve 67 of FIG.
The potential of 5 may be set to Vcc.

At the time of rewriting the information, if the information is "1", the potential of the other bit line 41 is set to 0 V as shown by a curve 70 in FIG.
If it is "0", the potential of the other bit line 41 is set to Vcc as shown by a curve 69 in FIG.

The operation of the semiconductor memory according to the present invention has been described above. For comparison with the operation described above, the operation when the precharge voltage Vb is not supplied to the bit line 40 will be described with reference to FIGS. 16 will be described.

FIG. 14 is a diagram showing a transition on the hysteresis curve when the charge in the initial state of the ferroelectric capacitor 12 is Q1, and FIG. FIG. 9 is a diagram showing a transition on a hysteresis curve when the condition is. FIG. 16 is a signal waveform diagram of each part corresponding to FIG.

The read signal 71 is supplied to the word line 30 without supplying the precharge voltage Vb to the bit line 40,
When a control pulse 72 is supplied to the plate line 35,
As shown in FIGS. 14 and 15, the state of the charge changes to point A on the hysteresis curve regardless of the initial state,
The potential of the bit line 40 rises as shown by the curve 73 in FIG. Also, the potential of the inversion bit line 41 slightly increases as shown by a curve 74 in FIG.

Next, when the plate line 35 returns to 0V, as shown in FIGS. 14 and 15, the state of the electric charge of the ferroelectric capacitor 12 is on the hysteresis curve regardless of the initial state. It changes to Q0 point. That is, when the charge in the initial state is Q1, the change in charge is Q0-Q1 (= 2 × Q
0), and the potential of the bit line 40 rises above 0 V as shown by the curve 73 in FIG.
In the case of 0, Q0-Q0 (= 0) and bit line 4
The potential of 0 returns to 0 V similarly to the potential of the inversion bit line 41.

As described above, in the semiconductor memory in which the precharge voltage Vb is not supplied to the bit line 40, the function of the semiconductor memory of the present invention as described above cannot be expected, and the information in the memory cell 1 cannot be correctly detected. Things.

That is, in order for the bit line potential to be divided into positive and negative depending on the initial state, the bit line must be precharged.

[0048]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the semiconductor memory of the present invention, and FIG. 4 is an operation signal waveform diagram of each part in the embodiment of FIG.

In the figure, 1 is a first memory cell, 2 is a second memory cell, 11 and 13 are gate transistors, 12 and 14 are ferroelectric capacitors, and 30 and 31 are first and second. Word lines 35 and 36 are connected to the first and second
And 40 and 41 are first and second bit lines, and 45 is a sense amplifier.

The first memory cell 1 comprises a gate transistor 11 and a ferroelectric capacitor 12, and the second memory cell 2 comprises a gate transistor 13 and a ferroelectric capacitor 14. . First memory cell 1
One end of the ferroelectric capacitor 12 is connected to the first plate line 3.
5 and one end of the ferroelectric capacitor 14 of the second memory cell 2 is connected to the second plate line 36. The gate of the transistor 11 of the first memory cell 1 is connected to the first word line 30, and the gate of the transistor 13 of the second memory cell 2 is connected to the second word line 31. Also, the first and second bit lines 40, 41
Are connected to the sense amplifier 45.

In this embodiment, the following operation is performed.

Here, the case where the information stored in the first memory cell 1 is read will be described. At this time, the information stored in the second memory cell 2 is irrelevant. During the read operation,
The second word line 31 is at 0 V, the gate transistor 13 is cut off, and the second plate line 3 is turned off.
6 is open.

First, the first and second bit lines 40, 4
1 is precharged with the voltage Vb (Vc), and at this time, the second bit line 41 is used as an inverted bit line. Next, the power supply voltage Vcc is applied to the first plate line 35 as the control pulse 60, and the power supply voltage Vcc is applied to the first word line 30 as the read signal 61 with a slight delay. Here, until the read signal 61 is applied, the gate transistor 11 is cut off, and no potential difference is applied between the ferroelectric capacitors 12. Does not move. However,
When the read signal 61 is applied, the gate transistor 11 is turned on, so that a potential difference of (Vcc-Vc) is given to the ferroelectric capacitor 12. As described above, if the ferroelectric film thickness d of the ferroelectric capacitor 12 is set so that the precharge voltage Vb (Vc) becomes one-fourth of the power supply voltage Vcc, Vcc−Vc = 3
× Vc, and even if the charge in the initial state of the ferroelectric capacitor 12 is Q1, the charge is inverted in polarity and changes to the point A on the hysteresis curve shown in FIG. As a result, the potential of the first bit line 40 rises above the precharge voltage Vb (Vc) as shown by the curve 62 in FIG.

Next, when the potential of the control pulse 60 of the first plate line 35 returns to 0 V, a potential difference of (-Vc), that is, a coercive electric field Ec is applied to the ferroelectric capacitor 12, and the electric charge is almost completely reduced. It becomes 0. Therefore, when the charge in the initial state of the ferroelectric capacitor 12 is Q1 (information “1”), the charge moves by −Q1 (= Q0> 0), that is, the charge of Q0 enters. On the other hand, when the charge in the initial state of the ferroelectric capacitor 12 is Q0 (information “0”), it means that the charge has moved by −Q0 (<0), that is, the charge of Q0 has come out.

Therefore, as shown by the curve 64 in FIG. 4, when the charge in the initial state is Q1 (information “1”), the first charge
Of the bit line 40 is precharge voltage Vb (Vc).
As shown by the curve 65 in FIG. 4, when the charge in the initial state is Q0 (information “0”), the potential of the first bit line 40 falls below the precharge voltage Vb (Vc). I do.

At this time, the potential of the second bit line 41 serving as the inversion bit line remains at the precharge voltage Vb (Vc), so that the sense connected between the first and first bit lines 40 and 41 is not used. Using the amplifier 45, the second bit line 4
1 based on the precharge potential Vb (Vc)
Of the bit line 40 is set to V when the information is “1”.
If the information is increased to cc, and if the information is "0", it is decreased to 0V, the information can be detected as Vcc, 0V digital information.

Next, in rewriting information, the information "
In the case of rewriting "1", as shown by the curve 66 in FIG. 4, the potential of the first bit line 40 is raised to Vcc, and Vcc is applied to the ferroelectric capacitor 12 to rewrite the information "1". On the other hand, in the case of rewriting information “0”, the first bit line 4
The potential of 0 is lowered to 0 V. At this time, the potential difference is not applied to the ferroelectric capacitor 12 due to the cutoff of the gate transistor 11, so that the information "0" cannot be rewritten. Therefore, only in the case of rewriting information “0”, as shown in the rewriting pulse 75 in FIG.
If the potential of the first plate line 35 is temporarily increased to Vcc, the potential difference V
With the addition of cc, information "0" can be rewritten.

In this embodiment, the first memory cell 1
The above description has been made on the assumption that the second bit line 41 is used as an inverted bit line for reading information. However, in order to read information from the second memory cell 2, the first bit line 41 is used. 40 is used as an inversion bit line, the potential of the first word line 30 is set to 0 V, and the first plate line 35
And the gate transistor 11, ferroelectric capacitor 12, first word line 30, first plate line 35, and first bit line 40 described above are connected to the gate, respectively. -Read transistor 13, ferroelectric capacitor 14, second word line 31, second plate line 36, and second bit line 41,
This can be achieved by a similar operation.

Further, in this embodiment, the first and second
Bit lines 40 and 41 and first and second plate lines 3
5 and 36 are arranged in parallel, and the first and second word lines 30 and 31 are arranged so as to intersect with them.

By adopting such a configuration, the first and second
Plate lines 35 and 36 and first and second word lines 3
Since 0 and 31 are not arranged in parallel, when all the memory cells connected to the word line for writing and reading information are selected, the polarization state of the ferroelectric capacitors changes. Can be avoided.

FIG. 5 is a circuit diagram showing a second embodiment of the semiconductor memory of the present invention.

In the drawing, 3 is a third memory cell, 4 is a fourth memory cell, 15 and 17 are gate transistors, 16 and 18 are ferroelectric capacitors, and 32 is a third word line. In addition, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

The third memory cell 3 comprises a gate transistor 15 and a ferroelectric capacitor 16, and the fourth memory cell 4 comprises a gate transistor 16 and a ferroelectric capacitor 18. . One end of the ferroelectric capacitor 16 is connected to a first plate line 35, one end of the ferroelectric capacitor 18 is connected to a second plate line 36, and the gate of the transistor 15 is connected to the second word line. Line 31
The gate of the transistor 17 is connected to a third word line 32, the transistor 15 is connected to a first bit line 40, and the transistor 17 is connected to a second bit line 4
1 are connected to the memory cell pair 1,
Although two sets of 2, 3 and 4 are used, the word line 31 arranged at the boundary between them is shared by both.

In this embodiment, the following operation is performed.

Here, a case where the information of the second memory cell 2 is read will be described.

When information is read from the second memory cell 2, the potentials of the first and third word lines 30 and 32 are set to 0 V, and the first plate line 35 is opened.
When such settings are made, the first and third word lines 3
By the 0V potential of 0, 32, each transistor 11, 17
Is cut off, the information stored in the first and fourth memory cells 1 and 4 has no effect on the other, and is retained. Also, the second word line 31
Is turned on, the transistor 15 of the third memory cell 3 is turned on.
Since the first plate line 35 connected to the third memory cell 3 is in an open state, information of the ferroelectric capacitor 16 of the third memory cell 3 is stored in the first bit line 30 serving as an inverted bit line.
Never appear in

Therefore, the first bit line 40 is used as an inversion bit line, and the second word line 31, the second plate line 36, and the second bit line 41 are respectively connected to the first embodiment. The read signal 6 similar to that described in
1. If the control pulse 60, the rewrite pulse 75, and the preset voltage Vb (Vc) are supplied, the same read operation as that of the first embodiment can be achieved.

In this embodiment, the second memory cell 2
Has been described, the information can be read from the first, third, and fourth memory cells 1, 3, and 4 by the same operation.

FIG. 6 is a circuit diagram showing a third embodiment of the semiconductor memory of the present invention.

In the figure, reference numeral 33 denotes a fourth word line, and the same components as those shown in FIG. 5 are denoted by the same reference numerals.

Then, each of the ferroelectric capacitors 12, 1
One end of each of 4, 16 and 18 is a first plate line 35
The gate of the transistor 15 of the third memory cell 3 is connected to the third word line 32, and the gate of the transistor 17 of the fourth memory cell 4 is connected to the fourth word line 33. And two memory cell pairs 1, 2
The plate line 35 arranged at the central portion of each of the memory cells 1, 2, 3 and 4 is shared by both memory cells 1, 2, 3 and 4.

This embodiment performs the following operation.

Here, the case where the information of the first memory cell 1 is read will be described.

When information is read from the first memory cell 1, the second, third, and fourth word lines 31, 3
The potentials of 2, 33 are set to 0V. With such a setting, the transistors 13, 15, 17 are cut off by the 0V potential of the second to fourth word lines 31 to 33, so that the second to fourth memory cells 2 to 4 are cut off. The stored information has no other effect and remains retained. Then, if the second bit line 41 is used as an inversion bit line, the first bit line 41 can be used in the same manner as described in the first embodiment.
Of the memory cell 1 can be read.

In this embodiment, the reading of information from the first memory cell 1 has been described, but the second, third, and fourth data are read.
Reading information from memory cells 2, 3, and 4 of
This can be achieved by an operation similar to the operation described above.

FIG. 7 is a circuit diagram showing a fourth embodiment of the semiconductor memory according to the present invention.

In the figure, 5 is a fifth memory cell, 6 is a sixth memory cell, 7 is a seventh memory cell, 8 is an eighth memory cell, 19, 21, 23 and 25 are gates. Transistors, 20, 22, 24, and 26 are ferroelectric capacitors, 37 is a third plate line, and 42 is a third word line, and the same reference numerals are used for the same components as those shown in FIG. Is attached.

Then, each of the ferroelectric capacitors 20, 2
One end of each of 2, 24 and 26 is a second plate line 36.
The gate of the transistor 19 of the fifth memory cell 5 is connected to the first word line 30, and the gate of the transistor 21 of the sixth memory cell 6 is connected to the third word line 32. The gate of the transistor 23 of the seventh memory cell 7 is connected to the second word line 31 and the transistor 2 of the eighth memory cell 8 is connected.
The gate of No. 5 is connected to the fourth word line 33, and the first gate is disposed at the center of each of the two memory cell pairs 1, 2, 3 and 4. Line 35,
A second plate line 36 disposed at the central portion of each of the other two memory cell pairs 5, 7 and 6, 8 is connected to these memory cell pairs 1, 2, and 3, 4, and 5, It is configured to be shared between 7, 6, and 8.

In this embodiment, the following operation is performed.

However, the case where the information of the first memory cell 1 is read will be described.

When reading information from the first memory cell 1, the second plate line 36 is opened, and the potentials of the second, third and fourth word lines 31, 32 and 33 are set to 0V.
And When such a setting is made, the second plate line 3
6, the potential difference is not applied to the ferroelectric capacitors 20, 22, 24, 26 of the fifth to eighth memory cells 5 to 8, so that the fifth to eighth memory cells 5 to 8 are not subjected to the potential difference.
The information of the memory cells 5 to 8 is held as it is without affecting the other, and the second to fourth memory cells 2 are controlled by the 0V potential of the second to fourth word lines 31 to 33. Since the transistors 13, 15, and 17 are cut off, the information stored in the second to fourth memory cells 2 to 4 is retained without affecting other information. . Then, in this case, if the second bit line 41 is used as the inverted bit line, the information in the first memory cell 1 can be read in the same manner as described in the first embodiment.

In this embodiment, the reading of information from the first memory cell 1 has been described, but the second, third, and fourth data are read out.
Reading information from memory cells 2, 3, and 4 of
This can be achieved by an operation similar to the operation described above.

The fifth to eighth memory cells 5 to 8
For reading the information of the first to fourth memory cells 1 to 4, the first plate line 35 is opened and the second plate line 36 is activated. By performing the same operation as the reading of information, the reading of information can be similarly achieved.

In each of the above embodiments, each of the ferroelectric capacitors 12, 14, 16, 18, 20, 22, 24, 26
The, PbZrO ₃ -PbTiO ₃ as the ferroelectric film material
A system (hereinafter referred to as PZT) is used, and the composition ratio of Zr in this case is set to 0.5. The characteristics of the PZT at this time are as follows: the remanent polarization is 12 μC / cm ² and the coercive electric field Ec is 50 kC.
V / cm. Then, each ferroelectric capacitor 12, 1
When the electrodes having an electrode area of 1 μm ² and a ferroelectric film thickness d of 0.5 μm are used as 4, 16, 18, 20, 22, 24 and 26, the precharge voltage of each of the bit lines 40 to 42 is (Ec × d) becomes 1.25 V. If a power supply voltage Vcc of 5 V is used, just 1
/ 4.

The aforementioned ferroelectric capacitors 12, 14, 1
Memory cell 1 including 6, 18, 20, 22, 24, 26
When a semiconductor memory is configured by using the semiconductor memory device, the capacity of each bit line 40 to 42 in the semiconductor memory is about 1.
Since it is 5 pF, the potential of the bit lines 40 to 42 rises by about 70 mV from the precharge potential of the inversion bit line when the information is "1", and the information becomes "0".
In this case, the potential is about 70% higher than the precharge potential of the inverted bit line.
As a result, it has been confirmed by an experiment that if the sense amplifier 45 is used, the information can be sufficiently detected even when the information is “1” or “0”.

In this embodiment, PZT is used as the ferroelectric film material, but PbTiO ₃ doped with La (hereinafter referred to as PLT) may be used. This PLT
Since the remanent polarization is larger and the dielectric constant is smaller than that of PZT, it is possible to obtain a larger potential change of the bit lines 40 to 42.
There is an advantage that the volume of 4, 16, 18, 20, 22, 24, 26 can be reduced.

[0088]

As described above, according to the present invention,
Force reading to bit lines 40 to 42 prior to reading information
Coercive electric field of the ferroelectric material of
By applying the precharge potential Vb substantially equal to the product of the film thickness, the information from each of the memory cells 1 to 8 is read out without using the dummy memory cell 10, and the “1” or “0” of the information is read. You can make a decision.
Then, the dummy memory cell 10 is not necessary, that amount can be increased by the number of the memory cells 1 to 8, resulting in a high reliability, the effect that it is possible to obtain an inexpensive semiconductor memory There is.

According to the present invention, the sense amplifier 45
Of the first or second bit line 40, 4 immediately before the sensing operation of
1 is higher than the precharge voltage Vb,
Keep the potential of the first or second plate line 35, 36 at 0V.
If the voltage is lower than the precharge voltage Vb, the first
Alternatively, the potentials of the second plate lines 35 and 36 are set to the power supply voltage.
Information can be rewritten,
To obtain semiconductor memory that can be read out or rewritten
There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a semiconductor memory of the present invention.

FIG. 2 is a history diagram of a ferroelectric capacitor charge on a hysteresis curve.

FIG. 3 is another hysteresis diagram of a ferroelectric capacitor charge on a hysteresis curve.

FIG. 4 is an operation signal waveform diagram of each part in the first embodiment of the semiconductor memory of the present invention.

FIG. 5 is a circuit diagram showing a second embodiment of the semiconductor memory of the present invention.

FIG. 6 is a circuit diagram showing a third embodiment of the semiconductor memory of the present invention.

FIG. 7 is a circuit diagram showing a fourth embodiment of the semiconductor memory according to the present invention;

FIG. 8 is a circuit configuration diagram showing a conventional semiconductor memory.

FIG. 9 is a signal waveform diagram illustrating an operation of writing information to a memory cell.

FIG. 10 is another signal waveform diagram illustrating an operation of writing information to a memory cell.

FIG. 11 is a hysteresis curve of a ferroelectric capacitor charge.

FIG. 12 is an operation signal waveform diagram of each section in a conventional semiconductor memory.

FIG. 13 is another operation signal waveform diagram of each section in the conventional semiconductor memory.

FIG. 14 is a hysteresis diagram of ferroelectric capacitor charge in a conventional semiconductor memory.

FIG. 15 is another hysteresis diagram of ferroelectric capacitor charge in a conventional semiconductor memory.

FIG. 16 is an operation signal waveform diagram of each section in another conventional semiconductor memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 1st memory cell 2 2nd memory cell 3 3rd memory cell 4 4th memory cell 5 5th memory cell 6 6th memory cell 7 7th memory cell 8 8th memory cell 10 Dam , Memory cell 11, 13, 15, 17, 19, 21, 23, 25 gate transistor 12, 14, 16, 18, 20, 22, 24, 26 ferroelectric capacitor 30 first word Line 31 Second word line 32 Third word line 33 Fourth word line 35 First plate line 36 Second plate line 37 Third plate line 40 First bit line 41 Second bit line 42 Third bit line 43 Inverting bit line 45 Sense amplifier

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-110895 (JP, A) JP-A-2-301093 (JP, A) JP-A-4-78098 (JP, A) JP-A-3-110 16097 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 11/40-11/409 G11C 11/22

Claims (6)

(57) [Claims] A first memory cell comprising a ferroelectric capacitor and a transistor; a first plate line connected to the ferroelectric capacitor of the first memory cell; and a second memory cell. A second plate line connected to the ferroelectric capacitor of the cell; a first word line connected to the gate of the transistor of the first memory cell;
Of the second memory cell connected to the gate of the transistor
Word line, a first bit line connected to the transistor of the first memory cell, a second bit line connected to the transistor of the second memory cell, and the first and second bit lines. Semiconductor memo consisting of connected sense amplifier
A Li, prior to the reading of the information, first and second
Electric field of ferroelectric material of ferroelectric capacitor with bit line
And a precharge potential substantially equal to a product of the product and the thickness of the semiconductor memory. 2. The method according to claim 1, wherein the second or first bit line is an inverted bit line, and the potential of the first or second bit line is detected by a sense amplifier at the time of reading information with reference to the potential of the inverted bit line. 2. The semiconductor memory according to claim 1, wherein: 3. The transistor gate of a second memory cell.
The second word line connected to the
Other first memory adjacent to the second memory cell.
A first word line connected to the gate of the transistor of the recell
3. The semiconductor memory according to claim 1, wherein said semiconductor memory is used in combination with a gate line . 4. A ferroelectric capacitor for a first memory cell.
Is connected to the first plate line of the second memory cell.
Along with the second plate line connected to the ferroelectric capacitor
The semiconductor memory according to claim 1 or 2, wherein the obtained by use. 5. A first plate line connected to a ferroelectric capacitor of a first memory cell is used together with a second plate line connected to a ferroelectric capacitor of a second memory cell , and Connected to the transistor of the first memory cell
Of the first bit line and the second memory cell
The second bit line connected to the bit line in the bit line arrangement direction.
, The other adjacent to the first memory cell
Of the second memory cell connected to the transistor of the second memory cell
The bit line and the other adjacent to the second memory cell
Of the first memory cell connected to the transistor of the first memory cell
4. The method according to claim 1, wherein the bit line is used together with the bit line.
3. The semiconductor memory according to 2 . 6. A ferroelectric capacitor and a transistor, respectively.
First and second memory cells each including a first memory cell and a first memory cell.
The first capacitor connected to the ferroelectric capacitor of the memory cell
Heat line and the ferroelectric capacitor of the second memory cell.
Connected second plate line and the first memory cell
A first word line connected to the gate of the transistor;
Of the second memory cell connected to the gate of the transistor
Word line and the transistor of the first memory cell
The first bit line and the transistor of the second memory cell.
A second bit line connected to the first bit line and first and second bit lines.
And a sense amplifier connected to the first bit line and connecting the first and second bit lines to a ferroelectric
The product of the coercive electric field of the ferroelectric material of the capacitor and its film thickness is approximately
A semiconductor device that precharges to the same precharge potential
Memory and the second or first bit line is inverted bit
Line and release the second or first plate line
Alternatively, the potential of the second plate line is set to 0V, the power supply voltage, and 0V.
After the change, the potential of the second or first bit line is
Sense the potential of the first or second bit line as the potential
When detecting with an amplifier, just before the sense operation of the sense amplifier
Potential of the first or second bit line is
When the voltage is higher than the voltage of the first or second plate line,
Keep the potential at 0 V and lower than the precharge voltage.
In this case, the potential of the first or second plate line is set to the power supply voltage.
A semiconductor memory characterized in that rewriting is performed .