KR100412146B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100412146B1 KR100412146B1 KR10-1998-0025794A KR19980025794A KR100412146B1 KR 100412146 B1 KR100412146 B1 KR 100412146B1 KR 19980025794 A KR19980025794 A KR 19980025794A KR 100412146 B1 KR100412146 B1 KR 100412146B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 150000004767 nitrides Chemical class 0.000 claims abstract description 33
- 230000002093 peripheral effect Effects 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 12
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Chemical Kinetics & Catalysis (AREA)
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Abstract
본 발명은 CMP를 이용하는 것 없이 셀 영역과 주변 영역 사이의 단차를 효과적으로 제거하여 평탄화를 이룩할 수 있는 반도체 소자의 제조방법을 제공한다.The present invention provides a method of manufacturing a semiconductor device capable of achieving planarization by effectively removing a step between a cell region and a peripheral region without using CMP.
본 발명에 따른 반도체 소자는 다음과 같은 방법으로 평탄화한다. 먼저, 셀영역 및 주변영역이 정의되고, 그의 상부에 상기 셀영역 및 주변영역 사이의 단차로 인하여 그들의 경계부에서 경사를 가지는 BPSG막이 형성된 반도체 기판을 제공하고, 기판 상에 주변영역 상의 BPSG막이 노출되도록 제 1 질화막을 형성한다. 그런 다음, 기판 전면에 제 1 질화막에 대하여 식각 선택비가 우수한 산화막을 형성하고, 산화막 상에 셀영역 상의 산화막이 노출되도록 제 2 질화막을 형성한 후, 제 2 질화막 및 산화막을 셀 영역 상의 제 1 질화막이 노출되도록 전면식각하여 평탄화한다. 바람직하게, 전면식각은 9 : 1 BOE 용액을 이용하여 진행하고, 제 1 및 제 2 질화막은 Si3N4막이고, 산화막은 SiO2막이다.The semiconductor device according to the present invention is planarized in the following manner. First, a cell substrate and a peripheral region are defined, to provide a semiconductor substrate having a BPSG film having an inclination at their boundary due to the step between the cell region and the peripheral region on top thereof, and to expose the BPSG film on the peripheral region on the substrate. A first nitride film is formed. Then, an oxide film having an excellent etching selectivity with respect to the first nitride film is formed on the entire surface of the substrate, and a second nitride film is formed on the oxide film so that the oxide film on the cell region is exposed. The surface is etched to be exposed and planarized. Preferably, the front etching is performed using a 9: 1 BOE solution, the first and second nitride films are Si 3 N 4 films, and the oxide film is SiO 2 film.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 셀 영역과 주변영역 사이의 단차를 제거하여 기판 표면의 평탄화를 이룩할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of flattening a surface of a substrate by removing a step between a cell region and a peripheral region.
일반적으로, 캐패시터를 이용하여 정보를 저장하는 반도체 메모리 소자는 좁은 면적에 높은 캐패시턴스를 요구하는 고집적화가 요구된다. 따라서, 캐패시터의 용량을 극대화하기 위한 방법으로 전극간의 유전체를 높은 유전율을 갖는 절연체를이용하거나, 전극의 면적을 확대시키는 방법등이 제안되었다.In general, semiconductor memory devices that use capacitors to store information require high integration, which requires high capacitance in a small area. Therefore, as a method for maximizing the capacitance of the capacitor, a method of using an insulator having a high dielectric constant as the dielectric between electrodes or increasing the area of the electrode has been proposed.
반면, 캐패시터의 고용량화로 인하여 셀 영역과 주변영역에 최소 6,000Å 정도가 단차가 필연적으로 발생된다. 이에 대하여 종래에는 캐패시터의 형성 후 BPSG (Boro-Phospho Silicate Glass)막을 약 1,000Å 정도로 두껍게 증착하고 리플로우 (reflow)를 진행한 후, 화학기계연마(Chemical Mechanical Polishing; CMP)를 진행함으로써, 셀 영역과 주변 영역 사이의 단차를 제거하고 기판 표면의 평탄화를 이룩하였다.On the other hand, due to the high capacity of the capacitor, at least 6,000 steps are inevitably generated in the cell region and the peripheral region. In contrast, conventionally, after forming a capacitor, a BPSG (Boro-Phospho Silicate Glass) film is deposited to a thickness of about 1,000 GPa thick, reflowed, and then subjected to chemical mechanical polishing (CMP). And the step between the peripheral region was removed and the surface of the substrate was planarized.
그러나, 상기한 바와 같이 CMP를 이용하게 되면, 공정 시간이 길고 제조비용이 높다. 또한, 기계적 스트레스(mechanical stress)로 인하여 디바이스의 특성이 저하되는 문제가 발생한다.However, when CMP is used as described above, the process time is long and the manufacturing cost is high. In addition, there is a problem that the characteristics of the device is degraded due to mechanical stress (mechanical stress).
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, CMP를 이용하는 것 없이 셀 영역과 주변 영역 사이의 단차를 용이하게 제거하여 기판 표면의 평탄화를 이룩할 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned problems, to provide a method of manufacturing a semiconductor device that can achieve a flat surface of the substrate by easily removing the step between the cell region and the peripheral region without using the CMP. The purpose is.
도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
[도면의 주요 부분에 대한 부호의 설명][Description of Symbols for Main Parts of Drawing]
10 : 반도체 기판 11 : BPSG막10 semiconductor substrate 11 BPSG film
12, 14 : 질화막 13 : 산화막12, 14 nitride film 13: oxide film
A : 셀영역 B : 주변영역A: cell area B: peripheral area
C : 경계부C: boundary
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자는 다음과 같은 방법으로 평탄화한다. 먼저, 셀영역 및 주변영역이 정의되고, 그의 상부에 상기 셀영역 및 주변영역 사이의 단차로 인하여 그들의 경계부에서 경사를 가지는 BPSG막이 형성된 반도체 기판을 제공하고, 기판 상에 주변영역 상의 BPSG막이 노출되도록 제 1질화막을 형성한다. 그런 다음, 기판 전면에 제 1 질화막에 대하여 식각 선택비가 우수한 산화막을 형성하고, 산화막 상에 셀영역 상의 산화막이 노출되도록 제 2 질화막을 형성한 후, 제 2 질화막 및 산화막을 셀 영역 상의 제 1 질화막이 노출되도록 전면식각하여 평탄화한다.The semiconductor device according to the present invention for achieving the above object is planarized by the following method. First, a cell substrate and a peripheral region are defined, to provide a semiconductor substrate having a BPSG film having an inclination at their boundary due to the step between the cell region and the peripheral region on top thereof, and to expose the BPSG film on the peripheral region on the substrate. A first nitride film is formed. Then, an oxide film having an excellent etching selectivity with respect to the first nitride film is formed on the entire surface of the substrate, and a second nitride film is formed on the oxide film so that the oxide film on the cell region is exposed, and then the second nitride film and the oxide film are formed on the first nitride film on the cell region. The surface is etched to be exposed and planarized.
본 실시예에서, 전면식각은 9 : 1 BOE 용액을 이용하여 진행하고, 제 1 및 제 2 질화막은 Si3N4막이고, 산화막은 SiO2막이다.In this embodiment, the front side etching is performed using a 9: 1 BOE solution, the first and second nitride films are Si 3 N 4 films, and the oxide film is SiO 2 film.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 1a를 참조하면, 셀영역(A) 및 주변영역(B)이 정의되고, 셀 영역(A)에 캐패시터(미도시)가 형성된 반도체 기판(10) 상에 BPSG막(11)을 증착한 후 리플로우한다. 이때, 리플로우된 BPSG막(11)은 셀영역(A)과 주변 영역(B) 사이의 단차로 인하여 그들의 경계부(C)에서 경사를 갖는다. BPSG막(11) 상에 제 1 질화막(12)을 증착하고, 주변영역(B) 상의 BPSG막(11)이 노출되도록 패터닝하고, 그 상부에 제 1 질화막(12)에 대하여 식각 선택비가 우수한 산화막(13)을 증착한다. 산화막(13) 상에 제 2 질화막(14)을 증착하고 셀영역(A) 상의 산화막(13)이 노출되도록 패터닝한다. 여기서, 제 1 및 제 2 질화막(12, 14)은 산화막(13)에 대한 식각 저지층으로서 작용하고, 바람직하게 제 1 및 제 2 질화막(12, 14)은 Si3N4막으로 각각 증착하고, 산화막(13)은 SiO2막으로 증착한다. 또한, 제 1 및 제 2 질화막(12, 14)과 산화막(13)은 단차에 따라 두께를 조절하여 증착한다. 예컨대, 단차가 약 6,000Å 정도인 경우, 제 1 및 제 2 질화막은 약 80Å 정도의 두께로 증착하고, 산화막은 단차보다 두꺼운 약 1㎛ 정도의 두께로 증착한다.Referring to FIG. 1A, after the cell region A and the peripheral region B are defined and a capacitor (not shown) is formed in the cell region A, the BPSG film 11 is deposited on the semiconductor substrate 10. Reflow. At this time, the reflowed BPSG film 11 has an inclination at the boundary portion C due to the step between the cell region A and the peripheral region B. FIG. The first nitride film 12 is deposited on the BPSG film 11, is patterned to expose the BPSG film 11 on the peripheral region B, and an oxide film having an excellent etching selectivity with respect to the first nitride film 12 thereon. (13) is deposited. A second nitride film 14 is deposited on the oxide film 13 and patterned so that the oxide film 13 on the cell region A is exposed. Here, the first and second nitride films 12 and 14 serve as an etch stop layer for the oxide film 13, and preferably the first and second nitride films 12 and 14 are deposited as Si 3 N 4 films, respectively. The oxide film 13 is deposited by a SiO 2 film. In addition, the first and second nitride films 12 and 14 and the oxide film 13 are deposited by adjusting the thickness according to the step difference. For example, when the step is about 6,000 mW, the first and second nitride films are deposited to a thickness of about 80 mW, and the oxide film is deposited to a thickness of about 1 μm thicker than the step.
그런 다음, 9 : 1 BOE(Buffered Oxide Etchant) 용액을 이용하여, 제 2 질화막(14) 및 산화막(13)을 셀영역(A) 상의 제 1 질화막(12)이 노출되도록 블랭킷 식각하여 도 1f에 도시된 바와 같이, 셀영역(A)과 주변영역(B) 사이의 단차를 제거하여 기판 표면의 평탄화를 이룩한다. 이때, 질화막(12, 14)에 대한 산화막(13)의 식각 선택비는 9 : 1 BOE 용액에서 약 67 정도로서, 산화막(13)의 식각율은 약 33.6Å/sec 이고, 질화막(12, 14)의 식각율은 약 0.5Å/sec 이다. 이에 따라, 먼저 도 1b에 도시된 바와 같이, 9 : 1 BOE 용액에 의해 노출된 산화막(13) 및 제 2 질화막 (14)이 소정 두께만큼 제거되고, 도 1c에 도시된 바와 같이, 노출된 산화막(13)이 소정 두께만큼 제거됨과 더불어 제 2 질화막(14)이 완전히 제거되어 산화막(13)이 완전히 노출된다. 그런 다음, 도 1d 및 도 1f에 도시된 바와 같이, 제 1 질화막 (12)을 식각 저지층으로하여 산화막(13)이 블랭킷 식각된다.Then, using a 9: 1 BOE (Buffered Oxide Etchant) solution, the second nitride film 14 and the oxide film 13 are blanket-etched to expose the first nitride film 12 on the cell region A. As shown, the level between the cell region A and the peripheral region B is eliminated to planarize the substrate surface. At this time, the etching selectivity of the oxide film 13 with respect to the nitride films 12 and 14 is about 67 in a 9: 1 BOE solution, the etching rate of the oxide film 13 is about 33.6 kV / sec, and the nitride films 12 and 14 The etching rate of is about 0.5Å / sec. Accordingly, first, as shown in FIG. 1B, the oxide film 13 and the second nitride film 14 exposed by the 9: 1 BOE solution are removed by a predetermined thickness, and as shown in FIG. 1C, the exposed oxide film is shown. While the 13 is removed by a predetermined thickness, the second nitride film 14 is completely removed to expose the oxide film 13 completely. Then, as shown in FIGS. 1D and 1F, the oxide film 13 is blanket etched using the first nitride film 12 as an etch stop layer.
상기한 본 발명에 의하면, CMP를 이용하는 것 없이, 높은 식각선택비를 가지는 산화막 및 질화막을 9 : 1 BOE 용액을 이용하여 블랭킷 식각함으로써, 셀영역과 주변영역 사이의 단차를 용이하게 제거하여 기판 표면의 평탄화를 이룩할 수 있게 된다. 이에 따라, 평탄화 공정시간이 감소될 뿐만 아니라 제조비용이 감소된다. 또한, CMP로 인한 기계적 스트레스가 방지되어 결국 소자의 특성이 향상된다.According to the present invention described above, the oxide film and the nitride film having a high etching selectivity are blanket-etched using a 9: 1 BOE solution without using CMP, thereby easily removing the step between the cell region and the peripheral region, thereby providing a substrate surface. The planarization of can be achieved. This not only reduces the planarization process time but also reduces the manufacturing cost. In addition, mechanical stress due to CMP is prevented, and thus device characteristics are improved.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
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| JPH0493071A (en) * | 1990-08-09 | 1992-03-25 | Nec Corp | Manufacture of semiconductor memory circuit |
| JPH05121688A (en) * | 1991-10-29 | 1993-05-18 | Sony Corp | Semiconductor storage device |
| JPH05326885A (en) * | 1992-05-15 | 1993-12-10 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH0697159A (en) * | 1992-09-14 | 1994-04-08 | Sanyo Electric Co Ltd | Fabrication of semiconductor device |
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| JPH0482263A (en) * | 1990-07-25 | 1992-03-16 | Sharp Corp | Semiconductor storage device |
| JPH0493071A (en) * | 1990-08-09 | 1992-03-25 | Nec Corp | Manufacture of semiconductor memory circuit |
| JPH05121688A (en) * | 1991-10-29 | 1993-05-18 | Sony Corp | Semiconductor storage device |
| JPH05326885A (en) * | 1992-05-15 | 1993-12-10 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH0697159A (en) * | 1992-09-14 | 1994-04-08 | Sanyo Electric Co Ltd | Fabrication of semiconductor device |
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