KR100399771B1 - Circuit for Malfunction Induction of fail Goods in Semiconductor Memory Device - Google Patents

Abstract

The present invention relates to an induction circuit for malfunctioning a defective product of a semiconductor memory device. The present invention relates to a fuse connected to a power source and not cut when the semiconductor memory device is normal, but cut when the semiconductor memory device is normal, and responding to a signal of the first node when power is applied. The first means for generating an initialization signal for controlling the operation of the semiconductor memory device, and the state of the signal of the second node is changed in response to the signal of the first node when the fuse is not cut. The state of the signal of the first node changes as the state of the signal of the second node changes, and when the fuse is cut, the state of the signal of the second node is fixed in response to the signal of the first node. Inoperable inducing means having second means for fixing the state of the signal of the first node as the state of the signal of the node is fixed, and input from the outside even when the fuse is cut Is configured, in response to the signal, the operation switching control means for changing the state of the second node. According to the present invention, the semiconductor memory device, which has been found to be defective and has been converted into an inoperable state through a fuse cutting, can be restored to a circuit-operable state. It is a useful invention with the advantage of being able to.

Description

Circuit for Malfunction Induction of fail Goods in Semiconductor Memory Device

In the semiconductor memory device, a semiconductor memory device which turns out to be inoperable after a fuse cutting has been found to be defective so that the semiconductor memory device can be converted back into an operational state so that the semiconductor memory device can be tested again. The inferior product of inoperable relates to the induction circuit.

The defective product inoperable device of the semiconductor memory device performs the function of the semiconductor memory device in which the fuse is cut after the fuse cutting is performed to physically cut the fuse of the product determined to be a defective product among the manufactured semiconductor memory devices. It is a device that prevents the use of the device by paralyzing. It prevents the leakage of the semiconductor memory device that is found to be defective and prevents the product from failing when the product is tested at the wafer and package level of the semiconductor memory device. A device is provided inside a semiconductor memory device for the purpose of screening on.

In general, as shown in FIG. 1, when an inductive device is installed in a semiconductor memory device and power is supplied from an external power supply device to the semiconductor memory device, the semiconductor memory device may be initialized normally when the semiconductor memory device is a normal product. It outputs a value to supply to each circuit in the semiconductor memory device, and if the fuse 20 that is found to be defective is cut, the function of the product is prevented from being used through the inoperable induction circuit 10. A value to be made is output to each circuit of the semiconductor memory device to render the semiconductor memory device inoperable.

Such inoperable induction circuit 10 can be designed in a number of ways, one example of which illustrates a conventional problem.

FIG. 2 is a circuit diagram for describing an inoperable induction circuit of a conventional semiconductor memory device. The inoperable induction circuit 10 includes PMOS capacitors C2 and C3, PMOS transistors MP3 and MP4, and NMOS transistors (FIG. First means 10-1 composed of MN2, MN3, and inverter INV1, and second means 10- composed of PMOSs MP1, MP2, NMOS transistor MN1, and NMOS capacitor C1. 2). The functions of each of the blocks shown in FIG. 2 will be described below.

The first means 10-1 generates a low level initialization signal VCCHB when the internal power supply IVC is at a low level, and generates a high level initialization signal VCCHB when the internal power supply IVC is at a high level. . In the second means 10-2, when the voltage level of the node 'B' becomes high when the fuse 20 is not cut, the node 'A' becomes a low level. Accordingly, the PMOS transistor MP1 is turned on. Node A goes high and node B goes low. When the fuse 20 is cut, when the voltage level of the node 'B' becomes high, the node 'A' is fixed to the low level, and accordingly, the voltage level of the node 'B' is fixed to the high level. That is, if the voltage level of the node 'B' becomes high when the fuse is not cut, the second means 10-2 makes the voltage level of the node 'B' low and makes the low level initialization signal VCCHB. When the fuse is cut, when the voltage level of the node 'B' becomes a high level, the voltage level of the node 'B' is fixed to a high level, thereby fixing the initialization signal VCCHB to a "high" level.

The operation of the circuit shown in FIG. 2 will be described as follows. First, the initialization signal VCCHB is a signal that performs a function of bringing circuits inside the semiconductor memory device to an initialization level, and is a semiconductor memory device powered by an external voltage source. In other words, when the VCC applied when the semiconductor memory device is turned on and the internal power supply IVC is applied to the input terminal, the initialization signal VCCHB outputs a low level through the circuit of FIG. 2. Supplying and initializing circuits of the semiconductor memory device, and outputting a high level paralyzes the function of the semiconductor memory device to switch to an inoperable state. The capacitors C1, C2, C3 operate as switching capacitors holding data.

When the fuse 20 is not cut because the semiconductor memory device is determined to be normal, when the low level internal power supply IVC is applied, the low level signal is transmitted to the node 'B' through the PMOS transistor MP3. Then, the PMOS transistor MP4 is turned on to generate a high level signal, and the inverter INV1 inverts the high level signal to generate a low level initialization signal VCCHB. When (IVC) is applied, a high level signal is transmitted to the node 'B' through the PMOS transistor MP3. Then, the NMOS transistor MN3 is turned on to generate a low level signal, and the inverter INV1 inverts the low level signal to generate a high level initialization signal VCCHB. The PMOS transistor MP1 is turned on because the initial level of the node 'A' is a low level, and the node 'A' becomes a high level. Thus, when the NMOS transistor MN1 is turned on and the node 'B' goes from the high level to the low level, the PMOS transistor MP4 is turned on and its output is at the high level, which is passed through the inverter INV1 to the initial value. Will be maintained. Accordingly, the low level initialization signal VCCHB is generated. That is, when the high level internal power supply IVC is applied, the initialization signal VCCHB transitions to a high level and then transitions to a low level. When the semiconductor memory device is determined to be defective, the fuse 20 is cut. When the low level internal power supply IVC is applied, the low level initialization signal VCCHB is generated.

On the other hand, when the internal power supply IVC of the "high" level is applied, the node 'B' becomes high level and generates the high level initialization signal VCCHB. At this time, the node 'A' is always low level and the PMOS Since the transistor MP1 is turned on but the fuse is cut, the voltage level of the node 'A' is fixed at a low level, which causes the PMOS transistor MP2 to be turned on so that the voltage level of the node 'B' is also fixed at a high level. The high level initialization signal VCCHB is generated. That is, when the high level internal power supply IVC is applied, the initialization signal VCCHB is fixed to the high level. Therefore, after the fuse 20 is found to be defective and the fuse 20 is cut, the product becomes inoperable and the semiconductor memory device becomes impossible to use.

FIG. 3 is a timing diagram for explaining, through a signal, a process in which a semiconductor memory device determined to be defective through an operation of the apparatus of FIG. 2 becomes inoperable.

Since power is not yet supplied until t0, the external power supply VCC of the semiconductor device, the internal power supply IVC and the initialization signal VCCHB transmitted from the VCC are both low.

When power is applied from t0 onwards, there is a slight delay from t1 to the low level between t2 and t3 after the high level period from t1 to t2. This signal level indicates that the interval is fully initialized. It is a step to detect and operate internally that the chip is initialized normally. After t3, the level is high, which means that the fuse 20 is cut, and thus the initialization signal VCCHB of FIG. 2 becomes high level, which means that the chip has entered an inoperable state. In other words, when the initialization signal VCCHB reaches a high level, the chip becomes inoperable inoperable state. Therefore, the semiconductor memory device, which has been found to be defective and has undergone a fuse cutting, remains in an inoperable state. do.

However, if the defective semiconductor memory device is made inoperable in this way, the internal circuit is configured in an inoperable state even when the cause of product inferiority is analyzed, but the product cannot operate at all. It becomes impossible to analyze the cause of the failure.

That is, since the fuse of the defective product inoperable induction circuit of the semiconductor memory device is cut, the initialization signal VCCHB is fixed at a high level so that the semiconductor memory device itself does not operate even if the cause of the failure is determined, so that the cause of the failure cannot be analyzed. Problem occurs.

SUMMARY OF THE INVENTION The present invention has been made to achieve the above object, and in the inoperable induction circuit of a defective product detected through a semiconductor memory device test, the semiconductor memory device is switched to an inoperable state through fuse cutting or the like. It is an object of the present invention to provide a circuit incapable of malfunctioning a defective product of a semiconductor memory device that can be restored to an operational state, so that it can be retested when analyzing a failure cause.

1 is a block diagram illustrating a conventional general inoperable induction circuit.

FIG. 2 is a circuit diagram illustrating a device for inducing a failure of a defective product of a conventional semiconductor memory device.

FIG. 3 is a timing diagram for explaining a process in which a semiconductor memory device which is found to be defective through an operation of the circuit of FIG.

4 is a circuit diagram illustrating a configuration of a defective product inoperable circuit of a semiconductor memory device according to an exemplary embodiment of the present invention.

5 is a circuit diagram for explaining another preferred embodiment of the present invention.

FIG. 6 is a timing diagram illustrating levels of main signals of a circuit configured as shown in FIG. 4 or 5 according to a preferred embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

20: fuse

10: inoperable induction circuit

20a, 20b: operation switching circuit

In order to achieve the above object, a defective product inoperable induction circuit of the semiconductor memory device of the present invention is connected to a power supply and is a fuse which is not cut when the semiconductor memory device is normal but is cut when it is defective, and the first node when the power is applied. First means for generating an initialization signal for controlling an operation of the semiconductor memory device in response to a signal of the second memory device; and a second device connected to the fuse and in response to a signal of the first node when the fuse is not cut. The state of the signal of the node is changed, the state of the signal of the first node is changed as the state of the signal of the second node is changed, and in response to the signal of the first node when the fuse is cut. A second means for fixing the state of the signal of the first node as the state of the signal of the second node is fixed and the state of the signal of the second node is fixed; Compared is characterized by having a properly operating the induction means, and an operation switching control means for changing the state of the second node to the fuse in response to a signal inputted from the outside, even if the cutting.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In addition, it should be noted that the same reference numerals are given to the same components, although belonging to different drawings for convenience of understanding.

FIG. 4 is a circuit diagram illustrating a configuration of a defective product inoperable induction circuit of a semiconductor memory device according to a preferred embodiment of the present invention, and an operation switching circuit 20a is added to the inoperable induction circuit 10 shown in FIG. 2. It is composed. As shown in Fig. 2, the inoperable induction circuit 10 is composed of first means 10-1 and second means 10-2.

As shown in FIG. 4, the inoperable induction circuit 10 configured in the semiconductor memory device has a low level initialization signal such that each circuit in the semiconductor memory device is normally initialized when it is determined that the semiconductor memory device is normal. The VCCHB is supplied to the circuits of the semiconductor memory device, and when the semiconductor memory device is determined to be defective, the fuse 20 is cut to provide a high level initialization signal VCCHB so that operation of each circuit of the semiconductor memory device is impossible. Supply to each circuit of the semiconductor memory device. In addition, when the initialization signal VCCHB is at a high level, the operation switching circuit 20a sets the high level initialization signal VCCHB output from the inoperation induction circuit 10 to a low level in response to a signal applied from the outside. By switching, the semiconductor memory device in the inoperative state is switched to the inoperable state.

At this time, when the semiconductor memory device is found to be defective and the fuse 20 is cut, the pad (PAD: Signal Pin) for receiving an external voltage level used for testing the semiconductor memory device is connected to the node 'A'. By artificially maintaining the voltage level of the initialization signal VCCHB in the low state through the operation switching circuit 20a, the semiconductor memory device can be maintained in a normal operating state so as to analyze the cause of the failure during the wafer level test. .

Preferably, the pad used at this time is composed of only pads of a semiconductor memory device that are commonly used in wafer level testing, so that no additional pad is required.

Referring to FIG. 4, when the fuse 20 is cut at the node 'A' to cause the semiconductor memory device to be inoperable, the external input unit 20a is connected through a pad that can be connected to the outside of the semiconductor memory device. When any one or more inputs of the input signals of the NOR gate NOR1 are at a high level, the output of the NOR gate NOR1 is at a low level and is supplied to the input of the inverter INV2. When the input of the (INV2) becomes a low level, the input level of the NAND gate (NAND1) is a high state, wherein the initialization signal (VCCHB) signal used for the inoperable state inside the semiconductor device is already at a high level Therefore, the output of the NAND gate NAND1 is at a low level, and the PMOS transistor MP5 is turned on.

When the PMOS transistor MP5 is turned on, the level of the internal power supply IVC of the semiconductor memory device is supplied to the node 'A', so that the level of the node 'A' becomes high. As described above, the node 'A' Since NMOS transistors MN1 and MN3 are turned on at the high level, the initialization signal VCCHB goes back to the low level.

That is, when the initialization signal VCCHB is output at the low level, the inoperable state of the semiconductor memory is released and operates normally. Therefore, the cause of the failure may be analyzed by performing a circuit operation during the wafer level test.

However, in the case of the circuit configured as shown in FIG. 4, the assembling of the semiconductor memory device is completed, and the operation of releasing the operation using the internal pad of the semiconductor memory device is impossible.

In this case, the semiconductor memory device may be configured as shown in FIG. 5, which shows another exemplary embodiment of the present invention by using one or more pins (PINs) that are external to the semiconductor memory device.

In a semiconductor memory device which has already been processed in an inoperative state, the level of the initialization signal VCCHB is set to a high state by its inoperable induction circuit 10.

Therefore, the NMOS transistor MN5 is turned on and the PMOS transistor MP6 is turned on by the inverter INV5. At this time, when the high level is supplied to the inoperable induction circuit 20b through an external pin, the NMOS transistor MN5 and the PMOS transistor MP6 are turned on as described above, and thus, the PMOS transistors may be passed through the inverters INV3 and INV4. The gate level of MP5) becomes the low level and the level of node 'A' becomes high.

As a result, when the level of the node 'A' becomes high, as described above, the NMOS transistors MN1 and MN3 are turned on, and the initialization signal VCCHB is switched to the low level to release the inoperable state.

6 is a timing diagram for indicating the level of the main signal of a circuit configured as shown in FIG. 4 or 5 according to a preferred embodiment of the present invention. There is a slight delay from t1 to t1 when power is applied from t0 and t2 to t2. After the high level interval, the low level is between t2 and t3, which is a signal level indicating that the initialization is complete, and through this level, the chip internally detects that the chip is normally initialized and operates. Will be. After t3, the level is high, which means that the fuse 20 is cut, and thus the initialization signal VCCHB of FIG. 2 becomes high level, which means that the chip has entered an inoperable state. At t4, since the external pin or pad signal supplies the high level signal, the initialization signal VCCHB transitions from the high level to the low level, thereby switching the chip to an operational state.

Therefore, even if the semiconductor memory device is inoperable by fuse cutting during various semiconductor tests such as wafer level test, the chip is converted into an operable state by applying a high level signal to the pins or pads, and the failure cause analysis for the defective chip is performed. Can be performed.

As described above, according to the present invention, the semiconductor memory device, which has been found to be defective and has been converted into an inoperable state through a fuse cutting, can be restored to an operational state by a circuit. It is a useful invention that has the advantage of being able to run and test normally.

Claims (5)

A fuse connected to a power source and not cut when the semiconductor memory device is normal but cut when the semiconductor memory device is bad; First means for generating an initialization signal for controlling an operation of the semiconductor memory device in response to a signal of a first node when the power is applied; The first node is connected to the fuse, and the state of the signal of the second node is changed in response to the signal of the first node when the fuse is not cut, and the state of the signal of the second node is changed. The state of the signal of the second node is fixed in response to the signal of the first node and the state of the signal of the second node is fixed in response to the signal of the first node when the fuse is cut. Inoperable inducing means having second means for fixing a state of a signal of one node; And And operation switching control means for changing a state of the second node in response to a signal input from the outside even when the fuse is cut. The method of claim 1, wherein the first means A first PMOS transistor having a source connected to the power source, a gate to which a ground voltage is applied, and a drain connected to the first node; An NMOS transistor having a gate and a drain connected to the first node and a source connected to a ground voltage; A first PMOS capacitor having a gate connected to the first node and a drain and a source connected to the power source; A first inverter for inverting the signal of the first node; A second PMOS capacitor having a gate connected to an output terminal of the first inverter and a drain and a source connected to the power source; And And a second inverter for inverting the output signal of the first inverter. The method of claim 1, wherein the second means A third PMOS transistor having a source connected to the fuse, a gate and a drain connected to the first node; An NMOS capacitor having a gate connected to the first node and a drain and a source connected to a ground voltage; And And a third inverter for inverting the signal of the first node and outputting the inverted signal to the second node. The method of claim 1, wherein the operation switching means A logic circuit for generating an operation switching control signal by combining the initialization signal and the signal input from the outside; And And a fourth PMOS transistor for transmitting a high level to the second node in response to an operation switching control signal generated from the logic circuit. According to claim 1, wherein the signal input from the outside is When the semiconductor memory device is in a wafer state, it is applied from a pad, And the semiconductor memory device is applied from an external pin when assembly is completed.