KR0145218B1 - Clock control circuit - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Semiconductor memory device

2. The technical problem to be solved by the invention

The semiconductor memory device measures the operation speed of the circuit and generates a clock at an optimal timing.

3. Summary of the Solution of the Invention

In the semiconductor memory device comprising a first function performing means activated by the first clock to perform the first function, and a second function performing means activated by the second clock to perform the second function. A pad for inputting the first clock and a means for delaying the first clock, inputting two clocks outputted to the pad and the delaying means, and a means for issuing a second clock when the two clocks are activated. Variable to measure the first function execution means and the operation time, and activate the second clock at an optimum timing according to the measurement result.

4. Important uses of the invention

Description

Clock control circuit of semiconductor memory device

1 is a clock generation circuit diagram of a conventional semiconductor memory device.

2 is a configuration diagram of a circuit for generating an internal clock in FIG.

3 is a waveform diagram showing the operating characteristics of each part of FIG.

4 is a circuit diagram for controlling clock generation in a semiconductor memory device according to the present invention.

5 is a configuration diagram of a circuit for generating an internal clock in FIG.

6 is a waveform diagram showing the operating characteristics of each part of FIG.

7 is another configuration diagram of a circuit for generating an internal clock in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit of a semiconductor memory device, and more particularly, to a circuit capable of designing an optimum clock generation circuit by measuring an operation time when a variation of an operation performance prediction time of an internal circuit is severe.

In general, a peripheral circuit of a semiconductor memory device is a complex of unit blocks that perform various functions, and blocks constituting the peripheral circuit may be classified into two functionally. One of them is a function block that actually performs a function of a semiconductor memory device by inputting an address or data, processing the same, or outputting stored data. The other one is blocks that generate control clocks that perform a series of operations by sequentially activating / deactivating the above functional blocks. FIG. 1 is a diagram illustrating an operating state between the functional blocks and the clock generation blocks in the semiconductor memory device. The first function execution circuit 12 performs a function of inputting an external input signal EXD, which is an address or data, to perform a first function, and then output a first internal signal ITD1. The second function execution circuit 14 is a circuit for inputting the first internal signal ITD1 generated by performing the first function to perform a second function and then output a second internal signal ITD2. The first clock generation circuit 11 inputs an external control signal ECC to generate the first clock PITC1 so that the first function execution circuit 12 can perform the first function at a predetermined timing. Here, when the semiconductor memory device is a dynamic random access memory device, the external control signal ECC sms low address strobe signal is generated. The second clock generation circuit 13 receives the first clock PITC1 to generate a second clock PITC2 for controlling the operation of the second function execution circuit 14. In the configuration of FIG. 1, 12 and 14 are blocks corresponding to the former case of performing functions in the semiconductor memory device, and 11 and 13 correspond to the latter case controlling the operation of the functional blocks such as 12 and 14. Block. In FIG. 1, only a configuration for performing the first and second functions is illustrated, but circuits for performing more functions by being connected in a series configuration or in a parallel configuration may be further connected. FIG. 2 is a configuration diagram of a second clock generation circuit 13 that generates a second clock PITC2 by inputting the first clock PITC1 in FIG. 1 and may include a plurality of inverters connected in series.

FIG. 3 is a waveform diagram showing the operation characteristics of each part in the conventional configuration having the same configuration as that of FIG. 1, and the operation of FIG. 1 will be described with reference to FIG. First, the first clock generation circuit 11 inputs an external control signal ECC such as 301 to generate a first clock PITC1 such as 303 of FIG. 3 to activate the first function execution circuit 12 at a specific timing. Then, the first function execution circuit 12 inputs an external input signal EXD such as 302 of FIG. 3 and is activated when the first clock PITC1 such as 303 is generated to perform the corresponding function, and then the first internal signal as 304 of FIG. Occurs with ITD1. In this case, as shown in FIG. 3, the first function execution circuit 12 requires a function execution time called TD1 until the first internal signal ITD1 is generated after the first clock PITC1 is generated. When the first clock PITC1 is activated, the second clock generation circuit 13 should generate the second clock PITC2 delaying the first clock PITC1 to activate the second function execution circuit 14. At this time, the second clock PITC2 is generated before the first internal signal ITD1 is output, and the second function execution circuit 14 performs a malfunction. Therefore, the second clock PITC2 must be delayed than the first internal signal ITD1 and a sufficient timing margin TD2 must be secured. Therefore, the second clock generation circuit 13 inputs the first clock PITC1, and then adds TD1, which is an operation time of the first function execution circuit 12, and TD2, which is a timing margin of the first internal signal ITD1 and the second clock PITC2. It should be designed to generate the second clock PITC2 after delaying by TD3. Therefore, in the second clock generation circuit 13 having the configuration as shown in FIG. 2, if the delay time of the inverter is τ and the number of inverter stages is n stage, the delay time between the first clock PITC1 and the second clock PITC2 is Td3 =. nτ is obtained.

Therefore, to design the second clock generation circuit 13, it is necessary to accurately predict the Td3, which means that the operating time of the front end function execution circuit must accurately predict the Td1. Therefore, if the Td1 is designed to be shorter than the actual operation time, the timing margin between the first internal signal ITD1 and the second clock PITC2 is eroded or reversed, causing a problem of malfunction. In addition, if the TD1 is designed to be longer than the actual operation time, the Td3 becomes unnecessarily large, which causes a problem that the operation speed becomes slow. Modern semiconductor memory devices have increased integration, which makes the manufacturing process more complicated and requires advanced technology. Therefore, it becomes more difficult to control various parameters in the process, resulting in a relatively wide spread of process parameters. . In fact, when designing a semiconductor memory device, the operation execution time of the function execution circuits 11 and 14 is predicted through a circuit simulation based on the elements constituting the function execution circuit. In this case, when designing the function execution circuit based on the predicted operation execution time, the operation execution time may deviate from the predicted value according to the process variation in the manufacturing process of the actual semiconductor memory device. In particular, in the case of functional execution circuits that are sensitive to process changes of the device, the operation execution time may cause a large difference from the predicted period, which may cause the operation speed to be lowered or malfunctioned.

Therefore, when fixing the components generating the internal control signals in the conventional semiconductor memory device, a problem may occur in which the semiconductor memory device may malfunction. That is, when the operation time of the function execution circuit is not accurately predicted or when the function execution circuit has a lot of error with the operation execution time predicted by the process change, the generation time of the internal control signals is fixed. There is a problem that the operation of the semiconductor memory device can not be performed. In addition, in order to control such a malfunction in an optimal state, many trials and errors are required, which requires a lot of time and effort in designing a semiconductor memory device.

Accordingly, an object of the present invention is to provide a clock generation circuit capable of measuring the operation time of a corresponding internal circuit when the operation time of the internal circuit is not predicted in the design of a semiconductor memory device.

Another object of the present invention is to provide a circuit capable of measuring an operating time of an internal circuit in a semiconductor memory device and generating an optimal clock according to the measured result.

In order to achieve the above object of the present invention, the clock generation circuit of the present invention includes a first function performing means activated by a first clock to perform a first function, and a second function activated by a second clock to perform a second function. A pad for inputting an adjustable external clock in a semiconductor memory device having two function execution means, a means for inputting and delaying the first clock, and two clocks outputted to the pad and delay means are input. Means for generating the second clock when being activated to vary the external clock to measure the operation time of the first function performing means, and to activate the second clock PITC2 at the optimum time according to the measurement result Can be characterized.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As used herein, the term external control signal ECC denotes a signal inputted to activate an operation of the semiconductor memory device outside the semiconductor memory device. The external control signal ECC becomes a row address straw signal / RAS in the case of a dynamic random access memory device. The term "external clock PECC1" is a control signal capable of externally adjusting timing, and when designing a semiconductor memory device, the timing is variably adjusted according to the operation time of the front end function performing means. Indicates a signal. The term "external clock mode signal PECC2" is a signal input from the outside to inform the use of the external clock PECC1. When the external clock mode signal PECC2 is in an inactive state, the input path of the external clock PECC1 is blocked and the external clock is blocked. When the mode signal PECC2 is activated, a clock is generated according to the variable value of the external clock PECC1. The first clock PITC1 denotes an internal clock that is activated by a predetermined delay of the external control signal ECC. The term "second clock PITC2" denotes an internal clock set by the first clock PITC1 delayed by a predetermined delay or an external clock PECC1 capable of timing adjustment. The term first internal signal IDT1 denotes output data of an internal circuit activated by the first clock PITC1 to process and output the external input signal EXD. The term second internal signal ITD2 denotes output data of an internal circuit activated by the second clock PITC2 to process and output the first internal signal ITD1.

4 is a diagram showing the configuration of a circuit for generating an internal clock in a semiconductor memory device according to the present invention. The first clock generation circuit 41 generates the first clock PITC1 by a predetermined delay of the external control signal ECC. The first function execution circuit 42 inputs an external input signal EXD, which is activated by the first clock PITC1 to process the external input signal EXD and output a first internal signal ITD1. The second clock generation circuit 43 has a pad for inputting an external clock PECC1 and means for delaying the first clock PITC1, and generates the delayed first clock PITC1 as a second clock PITC2 when the external clock PECC1 is not input. When the external clock PECC1 is input, the second clock PITC2 is generated as the external clock PECC1. The second function execution circuit 44 is activated by the second clock PITC2 and processes the first internal signal ITD1 output from the first function execution means to output the second internal signal ITD2.

5 is a diagram showing the configuration of the second clock generation circuit 43 in FIG. 4, in which the pad 57 inputs an external clock PECC1 that is input from the outside and is adjustable. The ENMO transistor 51 is connected between the pad 57 and the ground voltage, and the gate electrode is connected to the power supply voltage. The ENMO transistor 51 functions to maintain the pad 57 at a ground voltage potential when the external clock PECC1 is not input to the pad 57. The inverter 52 is connected to the pad 57 to invert the external clock PECC1 input to the pad 57. Inverters 55-56 are multi-stage inverters connected in series, and are means for delaying the first clock PITC1. The NAND gate 53 inputs the outputs of the inverter 52 and the inverter 56, and outputs the negative inputs of the two inputs. The inverter 54 inverts the output of the NAND gate 53 to generate the second clock PITC2.

The present invention enables the external input of a clock for controlling unit blocks which perform various functions in a memory device on a peninsula. At this time, since the clock can be directly input from outside, it is possible to easily measure the proper timing which does not cause malfunction even in the case of severe process change. Can be designed. To this end, the second clock generation circuit 43 directly inputs the external clock PECC1. At this time, since the external clock PECC1 is a control signal necessary only for analysis and design, it does not need a separate pin for the package, and if there is only a pad 47 for inputting the external clock PECC1 when analyzing in a wafer state, do.

First, when the external clock PECC1 is not input, the potential of the pad 57 becomes the ground voltage since the enMOS transistor 51 is turned on. Then, the inverter 52 is inverted into a high logic signal and applied to one side input of the NAND gate 53. In this case, the NAND gate 53 receives the second clock moment when the first clock PITC1 delayed by the inverters 55-56 is activated. Occurs with clock PITC2. Also, when the external clock PECC1 input to the pad 57 is input as a low logic signal, the same form as described above is used. However, when the external clock PECC1 input to the pad 57 is in a high logic state, the NAND gate 53 inputs a low logic signal. In this case, the NAND gate 53 does not activate the second clock PITC2 regardless of the logic of the delayed first clock PITC1.

FIG. 6 is a waveform diagram showing the operating characteristics of each of FIGS. 4 and 5, and looks at the operation of generating the second clock PITC2 in the present invention. In this case, it is assumed that the first function execution circuit 42 is composed of elements sensitive to process changes, and thus the actual operating time Td1 is in a state of Td1Td3 which is much larger than the expected time. In this case, when the second clock generation circuit 43 generates the second clock PITC2 by using the delayed first clock PITC1, the second function execution circuit 44 is normal data in the first function execution circuit 42. It is activated before outputting and causes malfunction.

In this case, in order to measure the actual operating time Td1 of the first function execution circuit 42, an external clock PECC1 that transitions from high logic to low logic is applied to the pad 57 as shown in 605 of FIG. At this time, the NAND gate 53 is driven only when the external clock PECC1 transitions to a low logic state as shown in FIG. Therefore, if the time Td6 at which the external clock PECC1 transitions from the high logic state to the low logic state is increased, the time period Td3 at which the second clock PITC2 is activated to the high logic as shown in 606 of FIG. 6 is increased, thus increasing the time of Td1Td3. If the condition is satisfied, the second function execution circuit 44 normally generates the second internal signal ITD2 as shown in FIG. 607 of FIG. 6 so that a malfunction does not occur. Accordingly, the time when Td1 = Td3 can be found by measuring the time when the second function path 44 changes from a malfunction to a normal operation while varying the time period Td6 at which the external clock PECC1 transitions to a low logic state. At this point, the time period Td6 for activating the external clock PECC1 in a low logic state may be measured. In addition, the time point Td4 of generating the first clock PITC1, which is an operation clock of the first functional execution circuit 42 as shown in 603 of FIG. 6, may be measured by simulation of the circuit. Using Td6 and Td4, Td5 can be obtained from the relationship of Td5 = Td6-Td4. Here, the Td5 time refers to a delay period in which the external clock PECC1 is activated in a low logic state as in 605 after the first clock PITC1 is activated as in 603 of FIG. 6. Therefore, if the propagation delays of the inverter 56 and the inverter 52 are the same in FIG. 5, the delay unit of the inverter 55-56, which is a means for delaying the first click PITC1, is larger than the Td5. Just adjust the number of inverters at -56. That is, by adjusting the inverters 55-56 to compensate for the Td5 time, it is not necessary to use the external clock PECC1. In fact, if the delay means matches the time obtained by adding a slight timing margin to the Td5 value calculated under the condition of Td1 = Td3 in the semiconductor memory device, the loss is minimized in terms of operating speed. The circuit can be implemented with a stable operation while reducing the voltage.

Although the second clock generation circuit 43 shown in FIG. 5 is capable of delaying the second clock PITC2 using the external clock PECC1, it is impossible to advance the time point at which the second clock PITC2 is activated. Accordingly, a configuration of the second clock generation circuit 43 capable of simultaneously delaying or forwarding the activation time of the second clock PITC2 is illustrated in FIG. 7. Referring to the configuration of FIG. 7, the multi-stage inverters 77-78 connected in series are connected between the first clock PITC1 and the node N1 and serve as a means for delaying the first clock PITC1. The first pad 79 inputs all external clock signals PECC2. The second pad 80 inputs an external clock PECC1 whose timing can be adjusted. The ENMO transistor 71 is connected between the first pad 79 and a ground voltage, and a gate electrode is connected to a power supply voltage. The inverter 72 is connected between the first pad 79 and the node N2 and inverts the external clock mode signal PECC2 input to the first pad 79. The NAND gate 73 inputs the outputs of the node N1 and the node N2, performs negative logic multiplication, and outputs the result to the node N3. The NAND gate 73 inputs the output of the first pad 79 delay means, activates the second clock PITC2 when the delayed first clock PITC1 is input while the external clock mode signal PECC2 is released, and the external clock mode. The first means for deactivating the input of the delayed first clock PITC1 when the signal PECC2 is activated. The NAND gate 74 inputs the outputs of the first pad 79 and the second pad 80 to be negative and then outputs to the node N4. The NAND gate 74 inputs the outputs of the first pad 79 and the second pad 80, blocks the passage of the external clock PECC1 when the external clock mode signal PECC2 is released, and activates the external clock PECC1 when the external clock mode signal PECC2 is activated. Is the second means for generating the second clock PITC2. The NAND gate 75 inputs the outputs of the node N3 and the node N4 to output negative logic, and the inverter 76 inverts the output of the NAND gate 75 to generate the second clock PITC2. The NAND gate 75 and the inverter 76 may be means for generating the second clock PITC2 by inputting the outputs of the first and second means.

In the second clock generation circuit 43 as shown in FIG. 7, the second clock PITC2 may delay or advance the timing. That is, the timing of the second clock PITC2 can be freely adjusted by varying the external click PECC1. For this purpose, when the second clock generation circuit 43 as shown in FIG. 7 is used, two pads for inputting the external clock mode signal PECC2 and the external clock PECC1 are required. Since the external clock mode signal PECC2 and the external clock PECC1 are signals necessary only for analysis and design and are not required in actual products, the first pad 79 and the second pad 80 do not need separate package pins.

When the external clock mode signal PECC2 is not input to the first pad 79 or a low logic signal is input, the potential of the first pad 79 becomes a ground voltage, and thus, the nodes N2 and N4 are in a high logic state. In this case, the second clock PITC2 is determined according to the logic state of the node N1 regardless of the external clock PECC1 input to the second pad 80. The node N1 shows the first clock PITC1 delayed by the inverter 77-inverter 78. Therefore, the delayed first clock PITC1 is generated as the final second clock PITC2.

However, when the external clock mode signal PECC2 having the high logic is input to the first pad 79, the node N2 is in a low logic state, and the NAND gate 73 outputs a high logic signal to the node N3. Therefore, since the NAND gate 73 outputs a high logic signal regardless of the state of the node N1, it can be seen that the path of the delayed first clock PITC1 is blocked. In addition, since the NAND gate 74 has a high logic state, the output of the node N4 is determined by the external clock PECC1 input to the second pad 80. That is, the signal of the node N4 is determined by the logic of the external clock PECC1. Then, the NAND gate 75 and the inverter 76 which input the outputs of the node N3 and the node N4 are in accordance with the external clock PECC1 generated in the delayed first clock PITC1 or the node N4 generated by the node N3 according to the presence or absence of the external clock mode signal PECC2. Activate and output the second clock PITC2. At this time, the external clock PECC1 input to the second pad 80 while the external clock mode signal PECC2 is activated is a control signal capable of timing adjustment as described above. In this case, if the transition time of the external clock PECC1 is changed, the activation time of the second clock PITC2 may be delayed or advanced. At this time, when the activation time of the second clock PITC2 is advanced, if there is no problem in device operation, the operation time of the device may be increased by reducing the delay time from the first clock PITC1 to the second clock PITC2.

As described above, the clock generation circuit of the semiconductor memory device according to the present invention can easily measure the operation speed change of the unit block sensitive to the process from the outside, thereby monitoring the process. Second, when a malfunction occurs due to a change in the operation speed of a unit block due to a process change, a normal analysis can be induced by inputting an external clock, thereby facilitating design analysis. Third, the operating time of the unit block can be measured, so that the clock generation circuit can be designed without trial and error at the optimum timing. In addition, the clock generation circuit can be implemented by simply adding pads and a simple circuit.

Claims (9)

A semiconductor memory device comprising: a first function execution means activated by a first clock to perform a first function and a second function execution means activated by a second clock to perform a second function, the adjustable external clock A pad for inputting a signal, a means for inputting and delaying the first clock, and two clocks outputted to the pad and the delaying means, and means for generating the second clock when the two clocks are activated. And varying the external clock to measure an operation time of the first function performing means, and activating the second clock at an optimum timing according to a measurement result. The method of claim 1, further comprising a switching means connected between the pad and the second voltage and a control terminal connected to the first voltage to maintain the pad potential at the second voltage level when the external clock is not applied. And a means for deactivating the external clock. 3. The clock generation circuit of a semiconductor memory device according to claim 2, wherein said switching means is an MOS transistor, wherein said first voltage is a power supply voltage and said second voltage is a ground voltage. 12. A semiconductor memory device comprising: a first function execution means activated by a first clock to perform a first function and a second function execution means activated by a second clock to perform a second function Means for delaying by inputting a clock; a first pad for inputting an external clock mode signal; a second pad for inputting an external clock capable of timing adjustment; and an output of the first pad and the delay means; First means for activating the second clock when the delayed first clock is input while the clock mode signal is released, and deactivating the input of the delay means when the external clock mode signal is activated; A second means for inputting an output of the pad, for blocking a passage of the external clock when the external clock mode signal is released, and generating the external clock as a second clock when the external clock mode signal is activated; Means for inputting the output of the first means and the second means to generate the second clock, wherein the delayed first clock is generated as the second clock in the normal operation mode, and the external clock is generated in the external clock mode. And a second clock at the optimum timing according to the measurement result, wherein the operation time of the first function performing means is measured. 5. The method of claim 4, further comprising a switching means connected between the pad and the second voltage and a control terminal connected to the first voltage to maintain the pad potential at the second voltage level when the external clock is not applied. And a means for deactivating the external clock. 6. The clock generation circuit of a semiconductor memory device according to claim 5, wherein said switching means is an MOS transistor, wherein said first voltage is a power supply voltage and said second voltage is a ground voltage. A semiconductor memory device operated by an external control signal, comprising: first clock generating means for generating a first clock by delaying the external control signal a predetermined time, an external input signal being input, and activated by the first clock A first function performing means for processing an input signal, a pad for inputting an external clock, and means for delaying the first clock, wherein the delayed first clock is generated as a second clock when the external clock is not input. And a second clock generating means for generating the second clock as the external clock when the external clock is input, and a second function performing activated by the second clock to process the output of the first function performing means. Means for measuring the operation time of the first function performing means by varying the external clock, and activating the second clock at an optimum timing according to the measurement result The clock generation circuit of the semiconductor memory device according to claim. 8. The apparatus of claim 7, wherein the second clock generating means is a pad for inputting an adjustable external clock, a means for inputting and delaying the first clock, and inputs two clocks outputted to the pad and the delay means. And a means for generating the second clock when the two clocks are activated. 8. The apparatus of claim 7, wherein the second clock generating means comprises: a first pad for inputting and delaying the first clock, a second pad for inputting an external clock mode signal and a second pad for inputting a timing external clock; A pad and an output of the delay means are input, the second clock is activated when the delayed first clock is input while the external clock mode signal is released, and the input of the delay means is deactivated when the external clock mode signal is activated. A first means for inputting the output of the first pad and the second pad, blocking the passage of the external clock when the external clock mode signal is released, and transferring the external clock to the second clock when the external clock mode signal is activated. And a second means for generating and means for inputting the output of said first means and said second means to generate said second clock.