KR100231898B1 - Test circuit of semiconductor memory device and method thereof - Google Patents

Abstract

The present invention discloses a test method and circuit for a semiconductor memory device. The method includes classifying a plurality of data input / output pins into a predetermined number of groups, inputting test data through one data input / output pin for each group, writing and reading the same data in the corresponding memory cells of the group If the comparison data of the group are all the same, the fail signal is outputted through the pin which is not connected to the inside of the external pin when the pass signal is not the same. Since the device is implemented in accordance with the present method and therefore is not a method of checking the high impedance of the pin and is a method of checking the "high" level or "low" level of the pin, it can be effectively applied to semiconductor memory devices operating at high frequencies have.

Description

Method and circuit for testing semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method and circuit for a semiconductor memory device, and more particularly to a test method and circuit for testing a semiconductor memory device on a package.

As the number of data output pins of the semiconductor memory device increases, the testable pin count of the test device becomes limited, and the number of testable semiconductor memory devices decreases. This resulted in an increase in test time. In order to overcome this problem, a plurality of data input / output pins are classified into a predetermined number of groups, and one data input / output pin per group is used to write the same data to the remaining data input pins. If all the data are the same, the data is output. If a FAIL occurs, the data output buffer is disabled so that the value output through the data input / output pin is in the high impedance state.

FIG. 1 illustrates a semiconductor package having 32 data input / output pins for explaining a method of testing a semiconductor memory device on a conventional package. The apparatus includes external pins 100, internal pads 102, data input buffers DIBO-DIB31 104, data output buffers DOBO-DOB31 106, write circuits W0- W31, the read circuits R0-R31 110, and the comparators 112. [

The test operation of the above-described conventional configuration will be described below.

And classifies the 32 data input / output pins into a predetermined number of groups. In FIG. 1, four pins are grouped into eight groups into one group, and data is input / output only through one of the four pins forming one group. That is, data input / output pins 0 to 3 form a group and input test data through pin 1 of them. This data is input to the data input buffer (DIB0) through pad No. 0. The buffered data is input to the data input buffers (DIB1, DIB2, DIB3) through the data input buffer (DIB0). The data input buffers DIB0 to DIB3 output the buffered data to the corresponding write circuits W0 to W3. The write circuits W0 to W3 write the input data to the corresponding memory cell of the memory cell array 120. [ That is, the same data is written to all the cells. When the next read operation is performed, data output from the corresponding memory cell of the memory cell array 120 is input to the read circuits R0 to R3, respectively. The read circuits R0 to R3 output the read data to the data output buffers DOB0 to DOB3 and output the same to the comparator 012. The comparator 0 (112) enables the data output buffer (DOB0) to output data of "high" or "low" level to the 0th pin through the 0th pad if these output data are all the same If they are not all the same, the data output buffer DOB0 is disabled and the output of the 0th pin is set to high impedance. The operation described above is also performed for the other group of data input / output pins.

The conventional semiconductor memory device testing method on the package has a problem that it is not suitable for a semiconductor memory device operating at a high frequency by checking the high impedance of the output. That is, since the data output can not be sent in a sufficiently high impedance state within a short cycle time, the memory device can not detect a failure when it occurs.

It is an object of the present invention to provide a method of testing a semiconductor memory device on a package that is capable of accurately detecting failures during testing of a memory device operating at high frequencies.

It is another object of the present invention to provide a test circuit of a semiconductor memory device on a package that can accurately detect failures during testing of a memory device operating at high frequencies.

According to an aspect of the present invention, there is provided a method of testing a semiconductor memory device, Pads connected to the external pins; A plurality of data input buffers for buffering data input from the pads; A plurality of write means for writing the buffered data from the plurality of data input buffers to a corresponding memory cell of the memory cell array; A plurality of read means for reading the data written in the memory cell of the memory cell array, respectively; And a plurality of data output buffers for buffering data from the plurality of read means, the test method comprising: a plurality of data input / output pins among the outer pins; a plurality of data input / The data input / output pads, the plurality of data input buffers, the plurality of write means, the plurality of read means, and the data output buffers into a predetermined number of groups, A data input step of inputting test data through only one pin and buffering the test data through the corresponding data input buffer; A write step of outputting the buffered data to the other data input buffers in the group and writing an output signal of the data input buffers to the write unit in a corresponding memory cell of the memory cell array; A read step of reading the data written in the memory cell through the read means for each group; And comparing the data read by the read means with each other in a group, and when the comparison data of the group is combined, if a pass signal is not identical, a fail signal is transmitted through a pin which is not connected to an internal pad of the external pins And a comparing and verifying step of outputting the comparison result.

According to another aspect of the present invention, there is provided a test circuit of a semiconductor memory device including external pins; Pads connected to the external pins; A plurality of data input buffers for classifying data input / output pins of the external pins into a predetermined number of groups, inputting one data for each group and outputting the buffered data to another data input buffer in the group, field; A plurality of write means for writing the data buffered by the data input buffers into the corresponding memory cells of the memory cell array for each group; A plurality of read means for reading the data written to the memory cells of the memory cell array for each group; A predetermined number of comparison means for comparing data output from the read means for each group; And verification means for comparing the output signals of the predetermined number of comparison means and outputting a fail signal through a pin among the external pins which is not connected to the pad if the pass signals are not identical.

1 is for explaining a test circuit of a semiconductor memory device on a conventional package.

2 is intended to explain a test circuit of a semiconductor memory device on a package of the present invention.

3 is a circuit diagram of an embodiment of the check circuit shown in Fig.

Hereinafter, a method and a circuit for testing a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

FIG. 2 illustrates a semiconductor package having 32 data input / output pins for explaining a method of testing a semiconductor memory device on a package of the present invention. The apparatus includes external pins 100, internal pads 102, data input buffers DIBO-DIB31 104, data output buffers DOBO-DOB31 106, write circuits W0- W31, the read circuits R0 to R31 110, the comparators 112 and 114, and the check circuit 116. [

The test operation of the configuration of the present invention described above is as follows.

And classifies the 32 data input / output pins into a predetermined number of groups. In FIG. 2, four pins are grouped into eight groups into one group, and data is input / output only through one of the four pins forming one group. That is, data input / output pins 0 to 3 form a group and input test data through pin 1 of them. This data is input to the data input buffer (DIB0) through pad No. 0. The buffered data is input to the data input buffers (DIB1, DIB2, DIB3) through the data input buffer (DIB0). The data input buffers DIB0 to DIB3 output the buffered data to the corresponding write circuits W0 to W3. The write circuits W0 to W3 write the input data to the corresponding memory cell of the memory cell array 120. [ That is, the same data is written to all the cells. When the next read operation is performed, data output from the corresponding memory cell of the memory cell array 120 is input to the read circuits R0 to R3, respectively. The read circuits R0 to R3 output the read data to the data output buffers DOB0 to DOB3 and output the same to the comparator 012. The comparator 0 (112) generates the comparison signal COM0 of the "high " level when these output data are all the same. The above operation is performed through the data input / output pins of the other groups, and if the data output by these groups are all the same, the comparison signals COM1 to COM7 of the "high " level are generated. The comparator 114 generates a signal COM of the "high" level when the output signals of the comparators 112 are all "high" The check circuit 116 outputs a signal of a "low" level when there is no fail, and a signal of "high"

FIG. 3 shows a circuit of the embodiment of the check circuit shown in FIG. 2, which includes a PMOS transistor P1 having a gate electrode to which a precharge signal PRCHG is applied and a source electrode to which a power supply voltage is applied, An NMOS transistor N1 having a gate electrode to which an output signal of the inverter 200 is applied, a source electrode to which a ground voltage is applied, and a drain electrode connected to a drain electrode of the PMOS transistor P1; Inverters 210 and 220 for latching a signal from the common point of the transistor P1 and the NMOS transistor N1 and an inverter 210 for inputting an output signal of the inverter 210 and outputting the output signal to an external pin NC. And a fuse 230 as shown in FIG.

The check circuit 116 outputs a signal of "low" level inverted through the inverter 210 through the fuse 230 when the PMOS transistor P1 is turned on in response to the precharge signal PRCHG. That is, if the signal output to the external pin NC is at the "LOW" level, it can be recognized that there is no fail. Latches 210 and 220 cause the output signal to remain at a "low" level. However, when a fail occurs during the test read operation, the output signal COM of the comparator 116 becomes a "low" level, so that the NMOS transistor N1 is turned on and inverted through the inverter 210 And outputs a signal through the fuse 230. That is, if the signal output to the external pin NC is at the "high" level, it is recognized that there is a fail. In this way, the test equipment is recognized as a defective memory device if the output signal is at a "high" level to an external pin (NC) that is not connected to the internal pad.

After the above-described test is completed, the fuse present in the check circuit 116 may be disconnected.

As described above, since the test method and circuit of the semiconductor memory device on the package of the present invention is not a method of checking the high impedance of the pin but a method of checking the "high" level or the "low" level of the pin, It can be effectively applied to a semiconductor memory device.

Claims (4)

External pins; Pads connected to the external pins; A plurality of data input buffers for buffering data input from the pads; A plurality of write means for writing the buffered data from the plurality of data input buffers to a corresponding memory cell of the memory cell array; A plurality of read means for reading the data written in the memory cell of the memory cell array, respectively; And a plurality of data output buffers for buffering data from the plurality of read means, the method comprising the steps of: A plurality of data input / output pads among the external pins, a plurality of data input / output pads among the pads, the plurality of data input buffers, the plurality of write means, the plurality of read means, A data input step of classifying the buffers into a predetermined number of groups, inputting test data only through one of the data input / output pins for each group, and buffering the test data through the corresponding data input buffer; A write step of outputting the buffered data to the other data input buffers in the group and writing an output signal of the data input buffers to the write unit in a corresponding memory cell of the memory cell array; A read step of reading the data written in the memory cell through the read means for each group; The data read by the read means is compared in groups, and when the comparison data of the groups are combined, if the pass signals are not identical, a fail signal is output through a pin which is not connected to the pad of the external pins And a comparing and verifying step of comparing and verifying the semiconductor memory device. CLAIMS 1. A test circuit for a semiconductor memory device that enables testing in a package state, comprising: External pins; Pads connected to the external pins; A plurality of data input buffers for classifying data input / output pins of the external pins into a predetermined number of groups, inputting one data for each group and outputting the buffered data to another data input buffer in the group, field; A plurality of write means for writing the data buffered by the data input buffers into the corresponding memory cells of the memory cell array for each group; A plurality of read means for reading the data written to the memory cells of the memory cell array for each group; A predetermined number of comparison means for comparing data output from the read means for each group; And And verifying means for comparing the output signals of the predetermined number of comparison means and outputting a fail signal through a pin among the external pins which is not connected to the pad if the pass signals are not identical, The test circuit of the device. 3. The apparatus of claim 2, wherein the verification means comprises: a pull-up transistor that is turned on in response to a precharge signal; A pull-down transistor that is turned on in response to a signal generated when the output signal of the comparator is not the same; A latch for latching a signal from a common point of the pull-up and pull-down transistors; And a fuse for receiving a signal latched by the latch and outputting the signal through a pin among the external pins which is not connected to the pad. 4. The test circuit of claim 3, wherein the fuse is blown after the test.