KR100296124B1 - Semiconductor device capable of full-repair characteristic test - Google Patents

Abstract

The present invention is to provide a semiconductor device that can perform a characteristic test faster by performing a characteristic test of the memory chip for the remaining portions except the failed memory cells before the repair operation on the failed memory cell. The present invention is a semiconductor device including a plurality of memory cells and a plurality of address pads to receive an address applied from the outside, and is connected to the address pad in a semiconductor device for performing a characteristic test on the remaining cells except a failed memory cell. Address storage means for receiving and storing the failed address in response to a first external control signal enabled to receive a failed address from a test equipment during the characteristic test; An address coupled to the address pad and the address storage means and comparing an address currently input through the address pad with a failed address output from the address storage means in response to a second external control signal enabling a comparison operation; Comparison means; Internal control signal generation means for outputting a plurality of internal control signals in response to a write enable signal enabled during a write operation of the chip and a comparison result signal output from the address comparison means; And data path blocking means for blocking a normal operation path for the failed memory cell in response to an internal control signal output from the internal control signal generating means.

Description

Semiconductor device capable of full-repair characteristic test

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of performing a characteristic test of a memory chip except for failed memory cells before repairing a failed memory cell in a repair device. It is about.

In general, when testing a memory chip, an address of a failed memory cell is found by a test device, and a memory cell corresponding to the failed address is repaired by the repair device. After repairing, check the test equipment again, and then check the A.C characteristics of the memory chip.

In the memory chip test performed as described above, the A.C characteristic test cannot be immediately performed when a failure occurs even in one memory cell for processing reasons. Therefore, there is a problem in that a lot of time is unnecessary for the characteristic test of the chip by repairing the repair device for the characteristic test of the memory chip and performing the characteristic test again in the test device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and can perform a characteristic test more quickly by performing a characteristic test of a memory chip for the remaining portions except the failed memory cells before a repair operation on the failed memory cell. The purpose is to provide a semiconductor device.

1 is an address latch circuit diagram according to the present invention for receiving and storing a corresponding address of a failed memory cell.

2A is an address comparison circuit diagram in accordance with the present invention.

FIG. 2B is a circuit diagram for outputting a final comparison signal FA from a comparison result signal output from the address comparison circuit of FIG. 2A.

3 is a block diagram illustrating a data path including a control circuit according to the present invention.

FIG. 4 is a circuit diagram of an exemplary embodiment of a control signal generator for generating control signals WEF and READF used in the controller of FIG. 3.

* Description of the main parts of the drawing

100: address pad 110: address buffer

130, 322: latch portion 300: data input / output pad

310: data input buffer 320: control unit

330: data output buffer 340: sense amplifier

321, 324, 323: pass gate

In accordance with an aspect of the present invention, there is provided a semiconductor device including a plurality of memory cells and a plurality of address pads receiving an address applied from the outside, and performing a characteristic test on a cell other than a failed memory cell. Address storage means connected to the address pad and configured to receive and store the failed address in response to a first external control signal enabled to receive a failed address from a test equipment during the characteristic test; An address coupled to the address pad and the address storage means and comparing an address currently input through the address pad with a failed address output from the address storage means in response to a second external control signal enabling a comparison operation; Comparison means; Internal control signal generation means for outputting a plurality of internal control signals in response to a write enable signal enabled during a write operation of the chip and a comparison result signal output from the address comparison means; And data path blocking means for blocking a normal operation path for the failed memory cell in response to an internal control signal output from the internal control signal generating means.

The present invention receives and stores the address of a failed memory cell found by a test device during a test of a memory chip, compares an address input through an address input pad for the characteristic test with the failed address, and performs normal operation in the same case. By configuring not to perform, and configured to perform a normal operation if not the same, it is possible to perform the characteristic test of the chip without first repairing the memory cell corresponding to the failed address.

1 is an address latch circuit diagram according to the present invention for receiving and storing a corresponding address of a failed memory cell, and is connected to each address pad. The address latch circuit includes an address pad 100 for receiving an address applied from the outside of the chip, an address buffer 110 for receiving an address from the address pad 100 and performing a buffering operation, and failing from the test equipment during the characteristic test. Stores a pass gate 120 for transferring an address output from the address buffer 110 in response to a control signal TE1 for receiving and storing an address, and a failed address output from the pass gate 120. And a inverter unit IV3 for inverting and outputting a failing address output from the latch unit 130, wherein the latch unit 130 includes two configured inputs and outputs to be engaged with each other. It consists of inverters IV1 and IV2. In addition, the control signal TE1 is a special signal that is not used when the memory chip operates normally. The control signal TE1 is a signal applied from the outside through the pad added by the present invention. Activated with a "high" signal to receive input.

A chip test on the test rig will determine the address of the failed memory cell, if any. Then, a high signal is applied to the control signal TE1 and the failed address is applied to each address pad. Accordingly, the failed address is latched to the latch unit 130 through the address buffer 110 and the pass gate 120.

Next, a low signal is applied to the control signal TE1 to turn off the pass transistor 120 so as to store only the address AFi that is failed in the latch unit 130.

2A illustrates an address according to the present invention for comparing an address Ai input through an address input pad 100 and an address buffer 110 and a failed address AFi stored in an address latch circuit for a characteristic test. A comparison circuit diagram is connected to each address pad. The address comparison circuit includes a negative logic gate 200 that receives an address Ai and a failed address AFi and performs a negative logic multiplication, and a negative logic gate that receives an address Ai and a failed address AFi and performs a negative logic sum. And a parallel connection between the PMOS transistor PM1, which is connected to the power supply voltage and receives the control signal / TE2 to the gate, the drain of the PMOS transistor PM1 and the output terminal FAi, and is negative to each gate. Negative logical gates connected in series between the PMOS transistors PM2 and PM3 receiving the output from the AND gate 200 and the output from the negative logic gate 210, the output terminal FAi, and the ground power supply. The NMOS transistors NM1 and NM2 that receive the outputs from the output and the negative logic gate 210 and the output terminal 200 are connected between the output terminal FAi and the ground power source and receive the control signal / TE2 through the gate. NM transistor (NM3) The control signal (/ TE2) is a special signal that is not used when the memory chip is operating normally. The control signal (/ TE2) is a signal applied from the outside through the pad added by the present invention, and is a failing address during the characteristic test. Is activated with a "low" signal when comparing the address input via the current address pad.

The "high" signal is output as the comparison result signal FAi only when the failed address AFi and the input address Ai are signals of the same level. For example, when the control signal / TE2 is input as a "low" signal, and the failed address AFi and the input address Ai are "high", the PMOS transistors PM1 and PM2 and the enMOS transistors. The NM2 is turned on, the NMOS transistors NM1 and NM3 and the PMOS transistor PM3 are turned off, and a "high" signal is output as the comparison result signal FAi so that the failed address AFi and the input address ( Ai) is the same. Then, when the control signal / TE2 is input as a "low" signal, the failing address AFi is "high", and the input address Ai is "low", the PMOS transistor PM1 and the enMOS transistor. The NM1 and NM2 are turned on, the NMOS3 and the PMOS transistors PM2 and PM3 are turned off, and a "low" signal is output as the comparison result signal FAi so that the failing address AFi and the input are output. Inform that the address Ai is not the same.

FIG. 2B is a circuit diagram for outputting the final comparison signal FA from the comparison result signal FAi output from the address comparator of FIG. 2A corresponding to each address pad, and the three comparison results output from each address comparator. A plurality of negative logical gates 220 that receive a signal as an input and a negative logic multiplication, and a negative logic gate 230 that receives all the signals output from the negative logical gate 220 and performs a negative logic sum.

When each comparison result signal FAi is "high", the final comparison signal FA is output "high" to indicate that the failed address and the currently input address are the same address.

3 is a block diagram illustrating a data path including a control circuit according to the present invention, in which a data input / output pad 300 for inputting / outputting data and data for receiving data from the data pad 300 and performing a buffering operation. Data input and output by performing an input buffer 310, a sense amplifier 340 for sensing and amplifying data read from a memory cell (not shown), and data output from the sense amplifier 340 and performing a buffering operation. The data output buffer 330 outputs to the pad 300, the data output from the data input buffer 310 for the write operation in response to a plurality of control signals, and the path of the data output through the sense amplifier 340. It consists of a control unit 320 for controlling.

The controller 320 outputs data from the data input buffer 310 during normal operation (ie, when the address currently input to the address pad is not a failed address) and during the data read operation in response to the control signal WEF. And a pass gate 321 and a pass gate 321 for transferring data output from the data input buffer 310 during a control operation (that is, when the address currently input to the address pad is a failed address). One end is connected to a latch unit 322 for storing data output from the inverter, an inverter IV4 for inverting data output from the latch unit 322, and a sense amplifier 340, and responds to a control signal READF. In the normal operation, the data output from the sense amplifier 340 is transferred to the data output buffer 330, and in the read operation during the control operation, the data is output from the sense amplifier 340. The pass gate 323 which blocks the data to be transmitted to the data output buffer 330 and the inverter IV4 and the other side of the pass gate 323 are connected to the other side of the inverter in the normal operation in response to the control signal READF. The pass-gate 324 which cuts out the data output from (IV4) and transfers the data output from the inverter IV4 to the data output buffer 330 at the time of a read operation at the time of a control operation.

FIG. 4 is a circuit diagram of an embodiment of the present invention for a control signal generator for generating control signals WEF and READF used in the controller of FIG. 3, wherein a write enable signal (/ Inverter IV5 that receives WE and inverts, and negative logic gate 400 that receives the output signal from inverter IV5 and the final comparison signal FA and performs a negative logic multiplication to output it as a control signal / WEF. And a negative logic gate 410 that receives the write enable signal / WE and the final comparison signal FA and performs a negative logic multiplication to output the control signal / READF, and the control signals / WEF and / READF. Are each composed of inverters IV6 and IV7 which invert.

3 and 4, an embodiment of the present invention will be described in detail.

First, the control signals WEF and READF during normal operation and control operation are divided according to the read operation and the write operation and are shown in Table 2 below (hereinafter, the high signal is "H" and the low signal is "L"). box)

First, when the failing address AFi and the currently input address Ai are the same through FIGS. 2A and 2B, that is, the final comparison signal FA is "H" in the control operation, and in the write operation (/ WE =). When the control signal / WEF is "L" and the control signal / READF is "H", the pass gate 321 is turned on in the data path of FIG. 3 through the data input buffer 310. The input write data is stored in the latch unit 322, and the pass gate 324 is turned off to block the data path so that data is no longer transferred while the data is stored in the latch unit 322.

At the next read operation (/ WE = "H"), the final comparison signal FA is "H", the control signal / WEF is "H", and the control signal / READF is "L". The gate 323 is turned on to block data output from the sense amplifier 340, and the pass gate 324 is turned on to store data stored in the latch unit 322 to the data output buffer 330. Is output.

Next, when the failed address AFi and the currently input address Ai are not the same, that is, in the normal operation, the final comparison signal FA is "L", and in the write operation (/ WE = "L"). When the control signal / WEF is " H " and the control signal / READF is " H ", the pass gate 321 is turned off, so that the write data passing through the data input buffer 310 is stored in the control unit of FIG. Data is input via the normal write data path (not shown) rather than by 320.

When the failed address AFi and the currently input address Ai are not the same, that is, in the normal operation, the final comparison signal FA is "L", and in the read operation (/ WE = "H"). When the control signal / WEF is " H " and the control signal / READF is " H, " the pass gate 323 is turned on to output the sensed amplified data output from the sense amplifier 340. Lead 330.

Accordingly, when a fail address corresponding to a failed memory cell is input, the A.C characteristic may be measured by performing a characteristic test on the remaining cells except the failed memory cell by operating the memory cell so as not to directly access the corresponding memory cell.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention as described above, the failed memory cell is not operated in response to a combination of two newly applied control signals from the outside, and the chip is subjected to a preferential characteristic test only on the remaining memory cells except the failed memory cell. In developing the chip, chip characteristics can be analyzed early. In addition, it is possible to reduce the overall memory chip development time by performing the repair operation on the failed memory cell after the characteristics are identified in advance.

Claims (10)

A semiconductor device including a plurality of memory cells and a plurality of address pads receiving an address applied from the outside, wherein the semiconductor device performs a characteristic test on the remaining cells except the failed memory cell. Address storage means connected to the address pad and configured to receive and store the failed address in response to a first external control signal enabled to receive a failed address from a test equipment during the characteristic test; An address coupled to the address pad and the address storage means and comparing an address currently input through the address pad with a failed address output from the address storage means in response to a second external control signal enabling a comparison operation; Comparison means; Internal control signal generation means for outputting a plurality of internal control signals in response to a write enable signal enabled during a write operation of the chip and a comparison result signal output from the address comparison means; And Data path blocking means for blocking a normal operation path to the failed memory cell in response to an internal control signal output from the internal control signal generating means A semiconductor device capable of performing all-repair characteristics testing comprising a. The method of claim 1, The address storing means, Transfer means for transferring the failed address input from the address pad in response to the first external control signal; And Latch means for storing the failed address output from the transfer means A semiconductor device capable of performing all-repair characteristics testing comprising a. The method of claim 2, The latch means, And a reversal means configured to engage an input and an output with each other. The method of claim 1, The address comparison means, First negative logic means for negatively multiplying an address currently input through the address pad and the failed address output from the address storage means; Negative logic sum means for receiving an illegal logic sum on an address currently input through the address pad and the failed address output from the address storage means; Second negative logic means for receiving a signal output from the negative logic means and a signal output from the negative logic means and performing a negative logic sum to output the comparison result signal; Bias means connected to a power supply voltage and biasing said second negative logical means in response to said second external control signal; And A pull-down means connected between an output terminal of the second negative logical means and a ground power supply, and pull-down driving the comparison result signal in response to the second external control signal; A semiconductor device capable of performing all-repair characteristics testing comprising a. The method of claim 4, wherein The second negative logical means, First and second PMOS transistors connected in parallel between the biasing means and the output stage and receiving an output from the first negative logic means and an output from the negative logic means to each gate; And First and second NMOS transistors connected in series between the output terminal and a ground power source and receiving an output from the first negative logic means and an output from the negative logic means to each gate; A semiconductor device capable of performing all-repair characteristics testing comprising a. The method of claim 4, wherein The pull-down means, An NMOS transistor receiving the second external control signal through a gate A semiconductor device capable of performing all-repair characteristics testing comprising a. The method of claim 1, The data path blocking means, First transfer means for transferring data output from a data input buffer in response to a first internal control signal output from said internal control signal generating means; Latch means for storing data output from said first transfer means; Second transfer means connected to one side of a sense amplifier and transferring data output from the sense amplifier to a data output buffer in response to a second internal control signal output from the internal control signal generating means; And Third transfer means connected to the other side of the latch means and the second transfer means to transfer data output from the latch means to the data output buffer in response to the second internal control signal; A semiconductor device capable of performing all-repair characteristics testing comprising a. The method of claim 7, wherein The first internal control signal is, The first block to be activated to block data output from the data input buffer when the address currently input through the address pad and the failed address are not identical to each other and when the write enable signal is disabled. And controlling the first transfer means to be active when the address currently input through the address pad and the failed address are the same and to transfer data output from the data input buffer. Semiconductor device capable of all-repair characteristic tests. The method of claim 7, wherein The second internal control signal is, Control the second transfer means to be activated when the address input through the current address pad and the failed address are not equal to each other and transfer data output from the sense amplifier to the data output buffer, The address inputted through the address pad and the failed address are the same, and when the write enable signal is disabled, the input is activated to block the data output from the sense amplifier from being transferred to the data output buffer. 2. A semiconductor device capable of a full-repair characteristic test, wherein the transfer means is controlled. The method of claim 7, wherein The second internal control signal is, The third transfer means is controlled to block data output from the latch means by being activated when the address currently input through the address pad and the failed address are not equal to each other. And the third transfer means is controlled to transfer data output from the latch means to the data output buffer when the write input signal is the same as the failed address and the write enable signal is disabled. A semiconductor device capable of all-repair characteristic tests.