iu 4646 五、發明說明（ 發明領t 本發明揭示一種具有預檢修測試模式之半導體記憶裝置 ，更明確地’一種用於半導體裝置之預檢修測試模式電路 ’其可以有效方式提供不良記憶格在檢修前之交流測試。 術說明 半導體裝置’即記憶晶片’大致包括複數個記憶格。記 憶晶片使用習用測試裝置來測試，以便檢測不良記憶格。 本情形中，不良記憶格之位址以測試裝置來識別。 另一方面，交流（AC )測試使用來測試記憶晶片之諸如資 料儲存性能的AC參數。AC測試對於記憶晶片尤其重要， 其主要功能在儲存資料。AC測試量以各種時間 '電壓位準 及型式來寫入資料到所要測試之記憶晶片，而檢查所寫入 資料是否可以照樣地恢復。 在上述習用方法中’當一個記憶格發生不良時’測試裝 置不能在不良記憶格檢修之前測試記憶晶片之AC參數。因 而’問題在於爲實施AC測試，記憶晶片中所包含不良記億 格必需檢修，所以需要很多時間來測試記憶晶片之AC參數 發明槪沭 因此，本發明之目的在於提供—種具有預檢修測試模式 之半導體記憶裝置，其能在不良記憶晶片檢修之前測試記 憶晶片之交流（AC)參數。 本發明之另一目的在於提供一種具有預.檢修測試模式之 本紙張尺度適用中國國家標準（CNSM4規格（210 X 297公釐） I^---------訂---------線 I (請先閱讀背面之注意事項再填寫本頁)iu 4646 5. Description of the invention (Invention t) The present invention discloses a semiconductor memory device with a pre-overhaul test mode, and more specifically, 'a pre-overhaul test mode circuit for semiconductor devices', which can effectively provide bad memory cells during overhaul The previous AC test. Technical description The semiconductor device 'ie memory chip' roughly includes a plurality of memory cells. The memory chip is tested using a conventional test device in order to detect bad memory cells. In this case, the address of the bad memory cell is determined by the test device. Identification. On the other hand, alternating current (AC) tests are used to test AC parameters such as data storage performance of memory chips. AC tests are particularly important for memory chips, whose main function is to store data. AC test quantities are at various time 'voltage levels And type to write data to the memory chip to be tested, and check whether the written data can be recovered in the same way. In the above-mentioned conventional method, when a memory cell is defective, the test device cannot test the memory before the defective memory cell is repaired. AC parameters of the chip. So 'the problem is to implement A C test, the memory chip contained in the memory chip must be repaired, so it takes a lot of time to test the AC parameters of the memory chip. Therefore, the object of the present invention is to provide a semiconductor memory device with a pre-overhaul test mode. The AC parameters of the memory chip can be tested before the defective memory chip is overhauled. Another object of the present invention is to provide a paper size with a pre-overhaul test mode applicable to the Chinese national standard (CNSM4 specification (210 X 297 mm)) I ^ --------- Order --------- Line I (Please read the notes on the back before filling this page)
經濟部智慧財產局員工消費合作社印K A7 Τ^υι&ι 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 半導體sS憶裝置，其可降低測試記憶晶片之交流（A C )參數 所需要的額外時間。 根據本發明，提供一種具有預檢測測試模式之半導體記 憶裝置，包含：記憶格陣列，包括具有至少一個不良記憶 格之複數個記憶格；位址路徑，用於提供一表示將從外部 電路存取之記憶格的輸入位址到記憶格陣列；不良檢測電 路’響應預檢修測試模式信號，同於從該輸入位址檢測指 示不良記憶格之不良位址而產生不良位址檢測信號；以及 控制電路’包括儲存格’用於響應不良位址檢測信號及寫 入控制信號以儲存來自外部電路；3資料於儲存格中，用於 響應不良ill址檢勸ig號及讀取控彰信號以檢索在儲存格中 之資料做爲輸出資料’用於響應寫入控制信號而儲存來自 外部電路之資料在輸入位址所指定記憶格中，及用於響應 讀取控制信號以檢索記憶格中所儲存之資料做爲輸出資料。 圖式之簡單說明 本發明之上述及其他目的及特徵將由下文較佳實施例連 同附圖之說明變得顯而易見，其α : 第1圖是根據本發明之具有預檢修測試模式的半導體裝 匱槪示圖； 第2圖是說明第1圖所示不良檢測電路之閂鎖電路（1 ac h circuit)槪示圖： 第3A圖是說明第1圖所示不良檢測電路之比較電路的電 路圖： 本纸張尺度適用中國國家標準（CNS)A4規格（210 >： 297公釐） ----------I I I 1--.1 I Γ ^ --------I ,1 (請先閱讀背面之注意事項再填寫本頁) /16 4 8 6 9 B7 、年月，日」 補充 五、發明說明（ 定 決 址 位 良 不 之 路 電 測 檢 良 不 示 1 所 第 圖 明 1及說 第以是 昍一;圖 I?圖 B 是路4 圖電及 B A 3 的 4 第路第 電 圖 路 電 之 路 電 制 控 示 所 圖 發明之詳細說明 參照第1圖，表示根據本發明之具有預檢修測試模式的半 導體記憶裝置，其包括記憶格陣列1 02、不良檢測電路1 04 '位址路徑（address path)l〇6、資料板（test pad)108' 經濟部智慧財產局員工消費合作社印鼓 資料緩衝器（date buifer)U〇及控制電路（control circuit)112 = 記憶格陣列1 0 2包括含有至少一個不良記憶格之多數記 憶格，其中π良記錄格可在記憶格陣列製備期間發生。位 址路徑1 06提供表示外部電路（未圖示）所要存取之記憶格 的輸入位址到記憶格陣列1 0 2。 不良檢測電路1 0 4響應預檢修測試模式信號*而檢測表 示來自輸入位址之不良記憶格的不良位址，而產生不良位 址檢測信號FA。然後，不良位址檢測信號FA耦接到控制 電路112。預檢修測試模式信號（在第2圖所示）由外部電 路提供1且由使用者在預檢修測試模式中所產生。在下文 當寫入致能信號/ WE在邏輯"低·•電位時，稱爲寫入控制 信號/ WE。而且，當寫入致能信號/ WE在邏輯“高”電位時 ’稱爲讀取控制信號（read c〇ntr〇i Slgnal)/We = 控制電路112包括儲存格，且響應不良位址檢測信號FA 及外部電路所輸入寫入控制信號/WE ，而儲存來自外部電 (諳先閱讀背面之注意事項再填寫本頁) 裝-------—訂---------線 本纸張尺度適用中國國家標準（CNS)AOM各（210 X 297公釐） 4 6 4 8 6 9 五、發明説明（） 路之資料在儲存格內。然後，控制電路1 1 2響應不良位址 檢測信號及讀取控制信號/ WE而恢復在儲存格內之資料做 爲輸出資料。進一步響應寫入控制信號/ W E，控制電路Π 2 儲存來自外部電路之資料在輸入位址所指定之記憶格內。 然後1響應讀取控制信號/ W E，控制電路1 1 2恢復在記憶格 內所儲存資料做爲輸出資料。 資料緩衝器110經資料板來緩衝來自外部電路之資 料’且傳送所緩衝資料到控制電路1 1 2 «進一步，資料緩 衝器110緩衝來自外部電路112之緩衝資料，且經資料板 108來傳送所緩衝資料到外部電路112。 參照第2 ' 3Λ及3β圖，表示第1圖所示不良檢測電路， 其包括多數閂鎖電路、多數比較電路及不良位址決定電路 參照第2圖，圖示第1圖不良檢測電路所包含閂電路1 其包括位址板200、位址緩衝器2 10 '通閘（p a s s ga t e ) 220 及不良位址閂2 3 0。 閂鎖電路響應預檢修測試模式信號TE 1或/ TE 1而閂鎖不 良位址之位元’其中不良位址表示不良記憶格，而且具有 多數位址位元。位址緩衝器210緩衝不良位址位元AFi 。 通閘2 2 0響應預檢修測試模式信號T E 1或/ T E 1來傳送不良 位址位元AFi。不良位址問230包括反相益（inver〖ei.)lVl ’ 1 V 2及I V 3 ’且閂鎮自通閘2 2 0所傳送之不良位址位元 AF i 。在不良位址位元AF ί閂後，表示用於ac測試.所要測 本紙张尺度適用中國威家榇準（CNS ) ΑΊ规格（21〇><297公茇） (請先閱讀背面之注意事項再填寫本页) •裝 T '-p. 經濟部智慧財產局8工消費合作社印製 五、發明説明（ 8 6 9 年9會;〇#司 5? TO· 試記憶格之新輸入位址的對應輸入位址位元經第I圖所 示位址板1 0 6及位址板2 0 0來閂入位址緩衝器2 1 0內《 (請先閱讀背面之注意事項再填寫本頁) 參照.第3 Λ圖，第I圖所示不良檢測電路之各比較電路包 括位址接收器3 〇 0及位址比較器3 4 0。比較電路比較來自 第2圖所示不良位址閂2 3 0不良位址位元A F !及來自第2園 所示位址緩衝器2 1 0之對應輸入位址位元A F ί ，而產生位 址比較信號F A i =即，位址接收器3 0 0接收來自不良位址 閂230之不良位址位元AFi及來自位址緩衝器210之對應® 入位址位元Ai。位址比較器340比較不良位址位元及對應 輸入位址位元而產生位址比較信號FAi 。如果不良位址位 元和對應位址位元完全相同，位址比較信號F A i變成邏辑 "高”信號。否則，位址比較信號F A i變成邏輯•‘低”信 號。 位址接收器300包括反及閘（NAND) 310，反或閘（N0R)320 及反栢器3 3 0。NAND閘3 1 0用於使得不良位址位元及對應 輸入位址位元反及。NOR閘320用於使得不良位址位元及 對應輸入位址位元反或。反相器330耦接到NOR閘320使得 經濟部智慧財產局員工消費合作社印奴 反或信號反相。 位址比較器3彳0包括一*組pm〇S(P通道全氧半導體）電晶 體及一組NMOS ( N通道全氧半導體）電晶體。pM〇s電晶體組 包括PM0S電晶體PM1、PM2及PM3。PM0S電晶體PM1響應 P Μ 0 S電晶體Ρ Μ 1之閘極所耦接預檢修測試模式信號/ τ E 2， 傳送來自電源之邏_ “高’’信號。pM〇S電晶體PM2響應來 本紙張尺度適用中國_國家捸準（CNS ) A4規格（210+X297公| ) I 6 五、發明説明（） 補充 經濟部智蚝_財產局S工消費合作社印製 自PN10S電晶體PM2之閘極所耦接反及（NAND)閘3 1 0之反及 信號的邏輯“低"信號，輸出邏輯“高”信號做爲位址比 較信號FAie PM0S電晶體PM3響應來自PM0S電晶體pM3閘 極所耦接反相器3 3 0之反相反或信號，輸出邏輯“高，.信 號做爲位址比較信號FA i。 NM0S電晶體組包括NMOS電晶體NM1、NM2'及NM0S 電晶體NM1響應NM0S電晶體NM1閘極所耦接反及信號之邏 輯"高"信號，傳送邏輯“高”信號到NM0S電晶體NM2。 NM0S電晶體NM 1閘極所耦接NM0S電晶體_2響應NM0S電晶 體NM2閘極耦接之反相反及信號，旁通邏輯••高"信號到 地（g f 〇 u n d )，因而_出邏輯“低”信號做爲比較信號F A i 參照第3 B圖1不良檢測電路之不良位址決定電袼包括多 數NAND閘3 50及NOR閘360。不良位址決定電路以位址比 較信號FA1至FAi來實施邏輯運算（logic operation) 1而 當輸入位址A丨和所閂入不良位址AFi完全相同時’產生不 良位址檢測信號FA。在NAND閘3 50處，使得來自比較電路 之位址比較信號FA 1至FAi反及。在NOR閛360，变得來自 NAND閘3 50之反及位址比較信號反或，而當輸入位址A !和 所閂入不良位址A F i完全相同時，產生不良位址喷測信號 Fa ° 參照第4A及4B圖，說明第1圖所示控制電路，其包括閘 控制信號產生器、通閘4 2 1 ' 4 2 3及4 2 4 '及儲存格4 2 2。 本紙悵尺度適用中國®家標準（CNS ) A4規格（210 X 297公釐）- ----Ί-------t------ΐτ------Μ (請先閱讀背面之注意事項再疔1¾本頁) 4 6 4 ί: 經濟部智葸財產局員工消費合作社印製 五、發明説明（）I 補充 如第4 A圖所示，閘控制信號產生器包括反相器I V 5 ' 1 V 6 及1 V7，及NAND閘4 00及4 10。閘控制信號產生器響應不 良位址檢測信號FA及寫入控制信號/ WE ’產生閘控制信號 WEF及/WEF來控制寫入運算（write operation)。進一步’ 閘控制信號產生器響應不良位址檢測信號F A及讀取控制 信號/ WE，產生閘控制信號READF及/READF來控制讀取運 算（read operation)。反相器]V5使得寫入控制信號/ WE 反相來產生反相寫入控制信號。在NAND閘4 00處’反相寫 入控制信號及不良位址檢測信號FA反及來產生閘控制信 / W EF。反相器I V 6使得來自NA ND閘4 0 0之反及信號反相而 產生閘控制信號WEF 6在NAMD閘4 1 0處，諳取控制信號/ WE 及不良位址檢測信號FA反及而產生閘控制信號/ READF =反 相器1 V 7用於使得來自N A N D閘4 1 0反及信號反相而產生閘 控制信號READF 。 參照第4B圖，通閘42 1響應閘控制信號WEF及/WEF，而 傳送來自外部電路之資料到儲存格4 2 2 =儲存格4 2 2包括 及相器IV8、IV9及iV10，且儲存來自通閘421之資料。 通閘4 24響應閘控制信號/ READF及READF來傳送儲存格422 內所儲存之資料。通閘4 2 3響應閘控制信號/ READF及READF ，而傳送來自外p電路之資料到蝓入位址所指定之記憶格 。通閘4 2 3響應閘控制信號/ R E A D F及R E A D F，而傳送輸入 位址所指定之記憶格內所儲存的資料。 第1表 -Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs K A7 Τ ^ υι & ι Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs According to the present invention, a semiconductor memory device having a pre-detection test mode is provided, comprising: a memory cell array including a plurality of memory cells having at least one bad memory cell; an address path for providing a The input address of the memory cell accessed by the external circuit to the memory cell array; the bad detection circuit responds to the pre-repair test mode signal, and generates a bad address detection signal from the input address detection indicating the bad address of the bad memory cell ; And the control circuit 'including the cell' is used to respond to the bad address detection signal and write the control signal to store from the external circuit; 3 data in the cell, used to respond to the bad ill address inspection to advise the ig number and read the control mark The signal is to retrieve the data in the cell as the output data 'for storing in response to the write control signal The data from the external circuit is in the memory cell designated by the input address, and is used to respond to the read control signal to retrieve the data stored in the memory cell as the output data. A brief description of the above and other objects of the present invention and The features will become apparent from the following description of the preferred embodiment together with the accompanying drawings, in which α: FIG. 1 is a diagram of a semiconductor device having a pre-overhaul test mode according to the present invention; FIG. 2 is a view illustrating FIG. 1 1 ac h circuit diagram of the defective detection circuit: Figure 3A is a circuit diagram illustrating the comparison circuit of the defective detection circuit shown in Figure 1: This paper is scaled to the Chinese National Standard (CNS) A4 ( 210 >: 297 mm) ---------- III 1-. 1 I Γ ^ -------- I, 1 (Please read the precautions on the back before filling this page ) / 16 4 8 6 9 B7, year, month, and day "Supplement V. Description of the invention Figure B is the circuit control diagram of Road No. 4 and BA 3 of No. 4 No. Detailed description of the Ming refers to FIG. 1, which shows a semiconductor memory device with a pre-repair test mode according to the present invention, which includes a memory cell array 102, a defect detection circuit 10 04 'address path 106, and a data board. (Test pad) 108 'Date consumer buffer U oo and control circuit 112 of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs = control circuit 112 = memory cell array 1 0 2 includes most memories containing at least one bad memory cell Grids, where the π good record grid can occur during memory grid array preparation. The address path 106 provides an input address indicating a memory cell to be accessed by an external circuit (not shown) to the memory cell array 102. The defective detection circuit 104 responds to the pre-overhaul test mode signal * and detects a defective address indicating a defective memory cell from the input address, and generates a defective address detection signal FA. Then, the bad address detection signal FA is coupled to the control circuit 112. The pre-overhaul test mode signal (shown in Figure 2) is provided by an external circuit and is generated by the user in the pre-overhaul test mode. In the following, when the write enable signal / WE is at the logic " low · • potential, it is referred to as the write control signal / WE. Moreover, when the write enable signal / WE is at a logic "high" potential, it is called a read control signal (read c〇ntr〇i Slgnal) / We = the control circuit 112 includes a cell and responds to a bad address detection signal FA and external circuit input write control signal / WE, and stored from external power (谙 Please read the precautions on the back before filling this page) Installation ------------ Order --------- The paper size of the paper is applicable to the Chinese National Standard (CNS) AOM (210 X 297 mm) 4 6 4 8 6 9 V. Description of the invention () The data of the road is in the cell. Then, the control circuit 1 12 responds to the bad address detection signal and reads the control signal / WE to recover the data in the cell as the output data. In response to the write control signal / WE, the control circuit Π 2 stores the data from the external circuit in the memory cell designated by the input address. Then 1 responds to the read control signal / WE, and the control circuit 1 1 2 restores the data stored in the memory cell as output data. The data buffer 110 buffers the data from the external circuit via the data board 'and transmits the buffered data to the control circuit 1 1 2 «Further, the data buffer 110 buffers the buffered data from the external circuit 112 and transmits the data via the data board 108 Buffer data to external circuit 112. Referring to FIGS. 2 ′ 3Λ and 3β, the defective detection circuit shown in FIG. 1 is shown, which includes a plurality of latch circuits, a plurality of comparison circuits, and a defective address determination circuit. Referring to FIG. 2, the defective detection circuit shown in FIG. 1 is included. The latch circuit 1 includes an address plate 200, an address buffer 2 10'pass gate (pass ga) 220, and a defective address latch 2 3 0. The latch circuit responds to the pre-examination test mode signal TE 1 or / TE 1 and latches the bits of the bad address', wherein the bad address indicates a bad memory cell and has most of the address bits. The address buffer 210 buffers bad address bits AFi. The open gate 2 2 0 responds to the pre-overhaul test mode signal T E 1 or / T E 1 to transmit the defective address bit AFi. The bad address question 230 includes the inverse benefits (inver [ei.) LVl ′ 1 V 2 and I V 3 ′ and the bad address bits AF i transmitted by the latch from the open gate 2 2 0. After the bad address bit AF, it indicates that it is used for the ac test. The paper size to be measured is applicable to China Weijia Standard (CNS) ΑΊ specifications (21〇 > < 297 Gong) (Please read the back Please fill in this page again) • Install T '-p. Printed by the 8th Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (9th meeting in 1989; 〇 # 司 5? The corresponding input address bits of the address are latched into the address buffer 2 1 0 through the address board 1 06 and the address board 2 0 shown in Figure I. (Please read the precautions on the back before filling (This page) Refer to Fig. 3 and Fig. 1. Each comparison circuit of the defect detection circuit shown in Fig. 1 includes an address receiver 3 00 and an address comparator 3 4 0. The comparison circuit compares the bad bits shown in Fig. 2 The address latch 2 3 0 bad address bit AF! And the corresponding input address bit AF from the address buffer 2 1 0 shown in the second circle, and an address comparison signal FA i = that is, address reception The device 3 0 0 receives the bad address bit AFi from the bad address latch 230 and the corresponding address bit Ai from the address buffer 210. The address comparator 340 does not compare The address bit and the corresponding input address bit generate an address comparison signal FAi. If the bad address bit and the corresponding address bit are exactly the same, the address comparison signal FA i becomes a logic " high " signal. Otherwise The address comparison signal FA i becomes a logic “low” signal. The address receiver 300 includes a reverse AND gate (NAND) 310, a reverse OR gate (N0R) 320, and an inverter 3 3 0. The NAND gate 3 1 0 Therefore, the bad address bit and the corresponding input address bit are inverted. The NOR gate 320 is used to reverse the OR of the bad address bit and the corresponding input address bit. The inverter 330 is coupled to the NOR gate 320 to make economy Ministry of Intellectual Property Bureau staff consumer cooperatives Indo-Slaves or signal inversion. The address comparator 3 彳 0 includes a * group of pMOS (P-channel all-oxygen semiconductor) transistors and a group of NMOS (N-channel all-oxygen semiconductor) transistors Crystal. The pM0s transistor group includes PM0S transistor PM1, PM2, and PM3. The PM0S transistor PM1 responds to the pre-overhaul test mode signal / τ E 2 coupled to the gate of P M 0 S transistor P M 1 and transmits Power logic_ "high" signal. PM〇S transistor PM2 response to the paper size applicable Country_National Standard (CNS) A4 specification (210 + X297 male |) I 6 V. Description of the invention () Complementary to the Ministry of Economy ’s Smart Oyster_ Property Bureau S Industrial Consumer Cooperative Co., Ltd. Printed from the gate of PN10S transistor PM2 coupled Inverting (NAND) gate 3 1 0 Inverting the logic "low" signal and outputting the logic "high" signal as the address comparison signal FAie PM0S transistor PM3 responds from the PM0S transistor pM3 gate is coupled to the reverse The phase inverter 3 3 0 reverses the OR signal, and outputs a logic “high”. The signal is used as the address comparison signal FA i. The NM0S transistor group includes the NMOS transistor NM1, NM2 'and NM0S transistor NM1 in response to the logic " high " signal coupled to the NM0S transistor NM1 gate and signal, transmitting a logic "high" signal to the NMOS transistor NM2 . NM0S transistor NM 1 gate is coupled to NM0S transistor _2 Responds to NM0S transistor NM2 gate is coupled to the opposite and signal, bypass logic • • high " signal to ground (gf 〇und), so _out The logic “low” signal is used as a comparison signal FA i. Referring to FIG. 3B, the defective address of the defective detection circuit is determined by a plurality of NAND gates 3 50 and NOR gates 360. The bad address determining circuit performs logic operation 1 using the address comparison signals FA1 to FAi, and generates a bad address detection signal FA when the input address A 丨 and the latched bad address AFi are identical. At the NAND gate 3 50, the address comparison signals FA 1 to FAi from the comparison circuit are inverted. In NOR 閛 360, the reverse of the NAND gate 3 50 and the address comparison signal become OR, and when the input address A! And the latched bad address AF i are exactly the same, a bad address spray signal Fa is generated. ° Referring to Figs. 4A and 4B, the control circuit shown in Fig. 1 is described, which includes a gate control signal generator, an open gate 4 2 1 '4 2 3 and 4 2 4', and a cell 4 2 2. The paper size of this paper applies to China® Home Standard (CNS) A4 specification (210 X 297 mm)----- Ί ------- t ------ ΐτ ------ Μ (Please Please read the precautions on the back before going to this page (1¾ this page) 4 6 4 ί: Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention () I Supplement As shown in Figure 4A, the brake control signal generator includes Inverters IV 5 '1 V 6 and 1 V7, and NAND gates 4 00 and 4 10. The gate control signal generator generates the gate control signals WEF and / WEF in response to the defective address detection signal FA and the write control signal / WE 'to control the write operation. Further, the gate control signal generator responds to the bad address detection signal F A and the read control signal / WE to generate the gate control signals READF and / READF to control the read operation. Inverter] V5 inverts the write control signal / WE to generate an inverted write control signal. At the NAND gate 400, the control signal and the bad address detection signal FA are inverted to generate the gate control signal / WEF. Inverter IV 6 reverses the signal from NA ND gate 4 0 0 and generates a gate control signal WEF 6 At NAMD gate 4 1 0, the control signal / WE and the bad address detection signal FA are reversed. Generate the gate control signal / READF = inverter 1 V 7 is used to invert the signal from the NAND gate 4 1 0 and generate the gate control signal READF. Referring to FIG. 4B, the gate 42 1 responds to the gate control signals WEF and / WEF, and transmits data from the external circuit to the cell 4 2 2 = cell 4 2 2 includes the phase generators IV8, IV9, and iV10, and the storage is from Information on opening gate 421. Gate 4 24 responds to the gate control signals / READF and READF to transmit the data stored in cell 422. The open gate 4 2 3 responds to the gate control signals / READF and READF, and transmits the data from the external p circuit to the memory cell designated by the entry address. The open gate 4 2 3 responds to the gate control signals / R A A D F and R E A D F, and transmits the data stored in the memory cell designated by the input address. Table 1-
本紙乐尺度適用中國ϋ家標準（CNS ) A4規格（2丨〇〆297公楚） (#先閱讀背面之注意事項再填寫本頁) .裝. 、11 線 6 4 48 1 五、發明説明（）This paper scale is applicable to the Chinese Family Standard (CNS) A4 specification (2 丨 〇〆297 公 楚) (#Read the precautions on the back before filling out this page). Packing, 11 line 6 4 48 1 V. Description of the invention ( )
狀態 /TE2 /\VE= “ 低” /WE= “高” /WEF /READF /WEF /KEADF 控制運算 (fa='‘高） 低 低 高 低 正常運算 (FA二.‘低，’） 冋 1% ί% 參照第4 A及4 B圖及第1表，控制電路響應不良位址檢測 信號（FA= “高”）及寫入控制信號（/ WE= “低”，儲存來自 外部電路之資料在儲存格4 2 2中。 控制電路響應不良位址檢測信號（FA= __高”）及寫入控制 信號（/ W E= “高：’），而恢復在儲存格4 2 2內之資料做爲輸 出資料。 進一步，控制電路響應不良位址檢測信號（FA= “低”） 及冩入控制信號（/ WE= “低’’），而儲存來自外部電路之資 料到_入位址所指定記憶格。 控制電路響應不良位址檢測信號（FA二“低”）及寫入控制 信號（/ WE= “高”），而恢復在記憶格內所儲存之資料做爲 輸出資料。 經濟部智慧財產局R工消費合作社印製 由上可見，當然根據本發明之不良位址檢測電路及控制 電路可提供獨特運算，來實施包含在記憶格陣列中之不良 記憶格檢修前的A C測試。即，在A C測試期間，不良記憶 格內所儲存資料可儲存在控制電路之儲存格內，而儲存格 內所儲存資料可直接恢復。其他記憶格直接測試以便記憶 格陣列之A C測試可在檢修作業之前有效地實施。 雖然本B明較佳實施例發表用於說明巨的，但擅於本技 本仏張尺度適用中國園。:：讳準（CNS ) A4規；( 2】0X: 7公釐）Status / TE2 / \ VE = "Low" / WE = "High" / WEF / READF / WEF / KEADF Control operation (fa = '' High) Low Low High Normal operation (FA II. 'Low,') 冋 1% ί% With reference to Figures 4A and 4B and Table 1, the control circuit responds to a bad address detection signal (FA = "High") and writes a control signal (/ WE = "Low". The data from the external circuit is stored in In cell 4 2 2. The control circuit responds to the bad address detection signal (FA = __high) and the write control signal (/ WE = "high: '), and restores the data in cell 4 2 2 to do To output data. Further, the control circuit responds to the bad address detection signal (FA = "Low") and the input control signal (/ WE = "Low"), and stores the data from the external circuit to the _in address specified Memory cell. The control circuit responds to the bad address detection signal (FA 2 "low") and the write control signal (/ WE = "high"), and restores the data stored in the memory cell as output data. Wisdom of the Ministry of Economic Affairs Printed by the Property Bureau R Industrial Consumer Cooperative, which can be seen from the above, of course, the bad address according to the present invention The detection circuit and the control circuit can provide unique calculations to perform the AC test before repairing the defective memory cells included in the memory cell array. That is, during the AC test, the data stored in the defective memory cells can be stored in the memory cells of the control circuit. The data stored in the cell can be directly restored. Other memory cells can be directly tested so that the AC test of the memory cell array can be effectively implemented before the maintenance operation. Although the preferred embodiment of this B Ming is published to explain the huge, Good at the technical scale of this book is applicable to the Chinese garden. :: CNS A4 regulation; (2) 0X: 7 mm)
經濟部智慧財產局員工涓費合作社印製 4 6 --- 五、發明説明（） 術者理解各種修正、附加及替代可能，而沒有脫離本發明 申請專利範圍之範圍及精神。 主要元件 之對照表 102 記憶格陣列 1 04 不良檢測電路 106 位址路徑 108 資料板 110 資料緩衝器 112 控制電路 200 位址板 2 10 位址緩衝器 421/220 通閘 230 不良位址閂 330/IV] 反相器 300 位址接收器 340 位址比較器 AF i 不良位址位元 350/310 反及閘 360/320 反或閘 ---..------装------1T------10 (请先閱讀背面之注意事項再填寫本頁) 本紙張尺度逞用中國Ej:標準（CNS )六心兄格（210X 297公釐）Printed by the staff of the Intellectual Property Bureau of the Ministry of Economy 4 6 --- V. Description of the invention () The operator understands the various amendments, additions and alternatives without departing from the scope and spirit of the patent application scope of the present invention. Comparison table of main components 102 Memory cell array 1 04 Defect detection circuit 106 Address path 108 Data board 110 Data buffer 112 Control circuit 200 Address board 2 10 Address buffer 421-220 Open gate 230 Defective address latch 330 / IV] Inverter 300 address receiver 340 address comparator AF i Bad address bit 350/310 reverse gate 360/320 reverse OR gate ---..------ install ---- --1T ------ 10 (Please read the notes on the back before filling out this page) This paper uses Chinese Ej: Standard (CNS) Six-Heart Brother (210X 297 mm)