JP2000090698A - Semiconductor device having pre-repair test mode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a time required for the AC parameter test of a memory chip by generating an error-address detecting signal in response to a pre-repair test-mode test control signal, storing data from the outside in a memory cell in response to the error-address detecting signal and a read control signal and retrieving data stored in the memory cell. SOLUTION: An error memory cell can be generated during the preparation of a memory cell array, and an address path 106 transmits an input address designating a memory cell accessed from the outside to a memory cell 102. An error detector 104 detects an error address specifying the error memory cell from the input address for generating an error-address detecting signal FA in response to a pre-repair test-mode test control signal, and couples the error address with a control circuit 112. The control circuit 112 retrieves data stored in the memory cell in response to a read control signal/WE.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pre-repair test mode.
In a particularly effective manner, a semiconductor device having AC (alternating current) before repairing an error memory cell
The present invention relates to a pre-repair test mode for use in a semiconductor device capable of providing an attenuating current test.

[0002]

2. Description of the Related Art Semiconductor devices, especially memory chips, generally include a large number of memory cells. The memory chip is tested by using a known test device to detect a failed memory cell. In such a case, the address of the error memory is identified by the test device.

On the other hand, AC (alternating c)
The current test is an alternating current (AC) such as a data store performance of a memory chip.
nt) Used to test parameters. AC
Testing is especially important for memory chips that perform the primary function of storing data. The AC test records data in a memory to be tested at various timings, voltage levels, and patterns, and checks whether the recorded data is accurately retrieved.

In the conventional method as described above, when an error occurs in a memory cell, the test apparatus cannot test the AC parameters of the memory chip before the error memory cell is repaired. Therefore, conventionally, there is a problem that much time is required since an error memory cell included in a memory chip must be repaired in order to test an AC parameter of the memory chip.

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is directed to an AC (alternating) circuit for a memory chip before an error memory cell is repaired.
It is an object of the present invention to provide a semiconductor device having a pre-repair test mode in which a g current parameter can be tested.

Further, the present invention devised to solve the above-mentioned problem is based on an AC (alternate) of a memory chip.
It is an object of the present invention to provide a semiconductor device having a pre-repair test mode that can reduce the time required to test an ing current parameter.

[0007]

According to the present invention, there is provided a memory cell array having a large number of memory cells including at least one error memory cell, and an input address designating a memory cell to be accessed from the outside. Is provided to the memory cell.
s path), an error detection circuit for detecting an error address designating the error memory cell from the input address to generate an error address detection signal in response to the pre-repair test mode test control signal, and Therefore, the external data is stored in the storage cell in response to the error address detection signal and the recording control signal, and the data of the storage cell is searched in response to the error address detection signal and the read control signal. Then, the external data is stored in the memory cell specified by the input address in response to the recording control signal, and the data stored in the memory cell is searched in response to the read control signal. And a control circuit.

[0008]

FIG. 1 shows a pre-repair test mode (pre-repair test mode) according to the present invention.
FIG. 3 is a schematic diagram of a semiconductor device having de).

Referring to FIG. 1, a semiconductor device includes a memory cell array 102, an error detection circuit 104, an address path 106, and a data pad 1.
08, a data buffer 110 and a control circuit 112.

[0010] The memory cell array 102 has a number of memory cells including at least one error memory cell, where the error memory cells can be generated during the preparation of the memory cell array. The address path 106 provides the memory cell 102 with an input address designating a memory cell to be accessed from outside. Below, the recording enable signal / WE
Is at the "low" level, it is referred to as the recording control signal / WE. When the write enable signal / WE is at a "high" level, it is referred to as a read control signal / WE.

An error detection circuit 104 detects an error address designating an error memory cell from an input address in order to generate an error address detection signal FA in response to a pre-repair test mode test control signal. The signal FA is coupled to the control circuit 112. The pre-repair test mode signal is provided externally and is generated by a user in the pre-repair test mode.

The control circuit 112 stores a storage cell (storage).
e cell) and stores external data in the memory cell in response to the error address detection signal FA and the externally supplied recording control signal / WE. The control circuit 112 searches the data of the storage cell in response to the error address detection signal FA and the read control signal / WE.
The control circuit 112 stores external data in a memory cell specified by the input address in response to the recording control signal / WE. The control circuit 112 responds to the read control signal / WE by using a memory cell (memory cell).
The data of the memory cell stored in l) is searched.

The data buffer 110 includes a data pad 10
The buffered data is transmitted to the control circuit 112 through the buffer 8.
The data buffer 110 buffers data from the control circuit 112 and transmits the buffered data to the outside through the data pad 108.

Referring to FIGS. 2, 3 and 4, the error detection circuit of FIG. 1 includes a plurality of latch circuits, a plurality of comparison circuits, and an error address determination circuit.

FIG. 2 is a schematic diagram of a latch circuit of the error detection circuit of FIG.

Referring to FIG. 2, each latch circuit of the error detection circuit includes an address pad 200 and an address buffer 2.
10, a pass gate 220 and an error address latch 230.

Each latch circuit latches an error address bit in response to a pre-repair test mode test control signal TE1 or / TE1, where the error address indicates an error memory cell and has a number of address bits.

The address buffer 210 buffers error address bits AFi and input address bits Ai from the address pad 200. Pass gate 22
0 transmits the error address bit AFi in response to the pre-repair test mode test control signal TE1 or / TE1. Error address latch 230 is connected to inverter I
Latch the error address bits AFi transmitted from the pass gate 220, including V1, IV2 and IV3. After the error address bit AFi is latched,
The input address bit of the new input address indicating the memory cell to be tested for the AC test is the address path 1
06 and the address buffer 210 via the address pad 200.

FIG. 3 is a circuit diagram of a comparison circuit of the error detection circuit of FIG.

Referring to FIG. 3, each comparison circuit of the error detection circuit shown in FIG. 1 includes an address receiver 300 and an address comparator 340. Each comparison circuit generates an error address bit AF from the error address latch 230 shown in FIG. 2 to generate an address comparison signal FAi.
i and an input address bit Ai from the address buffer 210 shown in FIG. 2 are compared bit by bit. The address receiver 300 receives one bit of the error address bit AFi from the error address latch 230 and the input address bit Ai from the corresponding address buffer 210.
Is received. The address comparator 340 compares one bit of the error address bit AFfi and one bit of the corresponding input address bit Ai to generate the address comparison signal FAi. If the error address bit is the same as the corresponding address bit, the address comparison signal FAi becomes a logic high signal. Otherwise, the address comparison signal FAi becomes a logical low signal.

The address receiver 300 performs a NAND operation (N
AND) gate 310, NOR gate (NOR) 3
20 and an inverter 330. NAND gate 31
0 performs a NAND operation on one bit of the error address from the error address latch 230 and one bit of the input address from the address buffer 210. The NOR gate 320 performs a NOR operation on one bit of the error address from the error address latch 230 and one bit of the input address from the address buffer 210. Inverter 3
30 is coupled to a NOR gate 320,
Invert the NOR operation signal.

The address comparator 340 includes a group of PMOS transistors and a group of NMOS transistors. The group of PMOS transistors includes PMOS transistors PM1, PM2 and PM3. The PMOS transistor PM1 transmits a logic high signal from the power supply in response to the pre-repair test mode test control signal / TE2 through the gate terminal. PMOS
The transistor PM2 responds to the logical low signal of the NAND operation signal from the NAND gate 310 coupled to the gate terminal, and the address comparison signal FAi.
And outputs a logic high signal. PMOS
The transistor PM3 responds to the inverted signal from the inverter 330 in the address receiver 300 coupled to the gate terminal, so that the address comparison signal F is output.
A logical high signal is output as Ai.

The group of NMOS transistors is NMO
Includes S transistors NM1, NM2 and NM3. NM
The OS transistor NM1 transmits a logic high signal in response to a NAND operation signal from the NAND gate 310 coupled to the gate terminal. NMO
The S transistor NM2 is coupled to the NMOS transistor NM1 and bypasses a logic high signal to ground in response to an inverted signal from the inverter 330 coupled to the gate terminal to bypass the logic high signal as the comparison signal FAi. Output a logic low signal. The NMOS transistor NM3 is coupled to the PMOS transistors PM2 and PM3,
In response to the pre-repair test mode test control signal / TE2 coupled to the gate terminal, a logic low signal is output as a comparison signal FAi by bypassing a logic high signal to ground.

FIG. 4 is a circuit diagram of the error address determination circuit of the error detection circuit of FIG.

Referring to FIG. 4, the error address determination circuit of the error detection circuit includes a plurality of NAND gates 350 and a NOR gate 360. When the input address Ai is the same as the latched error address AFi, the error address determination circuit performs a logical operation on the address comparison signals FA1 to FAi to generate an error address detection signal FA. The plurality of NAND gates 350 perform a NAND operation on the address comparison signals FA1 to FAi from the plurality of comparison circuits. When the input address Ai is the same as the latched error address AFi, the NOR gate 360 performs a NOR operation on the NAND operation signals from the multiple NAND gates 350 to generate the error address detection signal FA. Perform

Referring to FIGS. 5 and 6, the control circuit of FIG. 1 includes a gate control signal generator and a pass gate.
a) 421, 423 and 424 and storage cell 422
including.

Referring to FIG. 5, the gate control signal generator includes inverters IV5, IV6 and IV7 and NAND gates 400 and 410. The gate control signal generator controls the write operation in response to the error address detection signal FA and the write control signal / WE to control the gate control signal WE.
Generate F and / WEF. Further, the gate control signal generator generates gate control signals READF and / READF in order to control the read operation in response to the error address detection signal FA and the read control signal / WE. The inverter IV5 inverts the recording control signal / WE to generate an inverted recording control signal. NAND gate 400 has a gate control signal / WEF
In this case, a NAND operation is performed on the inverted recording control signal and the error address detection signal FA. Inverter IV6 is connected to NAND gate 40 to generate gate control signal WEF.
Invert the NAND operation signal from 0.
NAND gate 410 performs a NAND operation on read control signal / WE and error address detection signal FA to generate gate control signal / READF. Inverter IV7 has gate control signal REA
Invert the NAND operation signal from NAND gate 410 to generate DF.

Referring to FIG. 6, a pass gate (pass gate) is shown.
gate) 421 is a gate control signal WEF and / WE
In response to F, external data is transmitted. Storage cell 4
22 stores the data from pass gate 421 including inverters IV8, IV9 and IV10. The pass gate 424 controls the gate control signals READF and / READF.
To transmit the data stored in storage cell 422. Pass gate 423 transmits external data to a memory cell specified by an input address in response to gate control signals READF and / READF. Further, the pass gate 423 outputs the gate control signals READF and / RE.
The data stored in the memory cell is transmitted to the outside in response to the ADF.

[0029]

[Table 1]

Referring to FIGS. 5 and 6, and Table 1, the control circuit responds to the error address detection signal (FA = “High”) and the recording control signal (/ WE = “Low”) to store the data in the storage cell 422. Store external data.

The control circuit supplies an error address detection signal (FA
= “High”) and (read control signal / WE) =
The data of the storage cell 422 is searched in response to “High”.

Further, the control circuit supplies an error address detection signal (FA = “Low”) and a recording control signal (/ WE = “L”).
ow ”), external data is stored in the memory cell specified by the input address.

The control circuit supplies an error address detection signal (FA
= “Low”) and a read control signal (/ WE = “Hi”)
gh ”), the data stored in the memory cell is searched.

As described above, the error detection circuit and the control circuit according to the present invention can provide a specific operation for performing an AC test before repairing an error memory cell included in a memory cell array. That is, AC
The data stored in the error memory cell during the test can be stored in the storage cell of the control circuit, and the data stored in the storage cell can be directly searched. Another memory cell array is directly tested so that an AC test for the memory cell array can be effectively performed before the repair operation.

Although the technical concept of the present invention has been specifically described by the above-described preferred embodiments, it should be noted that the above-described embodiment is for the explanation and not for the limitation. is there. Also, those skilled in the art of the present invention can understand that various embodiments are possible within the scope of the technical idea of the present invention.

[0036]

As described above, the present invention has a pre-repair test mode, so that the AC (alternate) of the memory chip can be changed before the error memory cell is repaired.
An advantage of the present invention is that it is possible to test the parameters of the current chip, thereby reducing the time required to test the AC parameters of the memory chip.

[Brief description of the drawings]

FIG. 1 shows a pre-repair test mode (pr) according to the present invention.
FIG. 3 is a schematic diagram of a semiconductor device having an e-repair test mode.

FIG. 2 is a schematic diagram of a latch circuit of the error detection circuit of FIG.

FIG. 3 is a circuit diagram of a comparison circuit of the error detection circuit of FIG. 1;

FIG. 4 is a circuit diagram of an error address determination circuit of the error detection circuit of FIG. 1;

FIG. 5 is a circuit diagram of the control circuit of FIG. 1;

FIG. 6 is a circuit diagram of the control circuit of FIG. 1;

[Explanation of symbols]

 102 memory cell array 104 error detection circuit 106 address path 108 data pad 110 data buffer 112 control circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kim Seung-min Republic of Korea 467-860 Nuncun Bubarium Amiri Sun 136-1 Hyundai Electronics Industries Kampanee Limited

Claims (14)

[Claims] 1. A memory cell array having a large number of memory cells including at least one error memory cell, an address path for providing an input address designating a memory cell to be accessed from outside to the memory cell, a pre-repair test An error detection circuit for detecting an error address designating the error memory cell from the input address in order to generate an error address detection signal in response to a mode signal; The data from the outside is stored in the storage cell in response to a signal, the data in the storage cell is searched in response to the error address detection signal and the read control signal, and the data is stored in response to the recording control signal. Stores the external data in the memory cell specified by the input address A control circuit for retrieving data stored in the memory cell in response to the read control signal. 2. The error detection circuit according to claim 1, further comprising: latch means for latching the error address in response to a first pre / repair test mode signal; and when the input address is the same as the latched error address. And a comparing means for comparing the input address and the latched error address in response to a second pre-repair test mode signal to generate the error address detection signal. 2. A semiconductor device having the pre-repair test mode according to 1. 3. The latch means includes a plurality of latch circuits, wherein each of the latch circuits includes an address buffer for buffering the error address and the input address from an address pad; 3. The pre-charge circuit according to claim 2, further comprising: a pass gate for transmitting said error address in response to a repair test mode signal; and an error address latch for latching said error address transmitted from said pass gate. A semiconductor device having a repair test mode; 4. A comparison circuit comprising: a plurality of comparison circuits for comparing an error address from the error address latch with the input address from the address buffer for each bit unit to generate an address comparison signal; An error address determination circuit for performing a logical operation on an address comparison signal to generate the error address detection signal when the input address is the same as the latched error address. Item 4. A semiconductor device having a pre-repair test mode according to item 3. 5. An address receiver for receiving one bit of the error address from the error address latch and one bit of the input address from the corresponding address buffer. 5. The address comparison signal 5. The semiconductor device having a pre-repair test mode according to claim 4, further comprising an address comparator for comparing one bit of said error address and one bit of said input address corresponding to said error address. . 6. An address receiver, comprising: a NAND gate for performing a NAND operation on one bit from the address buffer corresponding to one bit from the error address latch; A NOR gate for performing a NOR operation on one bit from the address buffer corresponding to one bit from the latch; and a NOR gate coupled to the NOR gate. 6. The pre-processor according to claim 5, further comprising an inverter for inverting the operation signal.
A semiconductor device having a repair test mode. 7. The semiconductor device having a pre-repair test mode according to claim 5, wherein said address comparator includes a group of PMOS transistors and a group of NMOS transistors. 8. The group of PMOS transistors includes: a first PMOS transistor for transmitting a logic high signal from a power supply in response to the second pre-repair test mode signal through a gate terminal; A second PMOS transistor for outputting the logical high signal as the address comparison signal in response to the NAND operation signal passed through the inverter; and an inverted signal from the inverter of the address receiver through a gate terminal. 8. A semiconductor device having a pre-repair test mode according to claim 7, further comprising: a third PMOS transistor for outputting said logic high signal as said address comparison signal in response to the first PMOS transistor. 9. The NMOS transistor group is coupled to a first NMOS transistor for transmitting the logic high signal in response to the NAND operation signal through a gate terminal, and the first NMOS transistor. A second NMOS transistor for outputting a logic low signal by bypassing a logic high signal to ground in response to an inverted signal from the inverter of the address receiver through a gate terminal; A third N coupled to a third PMOS transistor for outputting the logic low signal by bypassing the logic high signal to ground in response to the second pre-repair test mode signal through the gate terminal.
9. The semiconductor device according to claim 8, further comprising a MOS transistor.
A semiconductor device having the pre-repair test mode described. 10. The error address determination circuit, comprising: a plurality of NAND gates for performing a NAND operation on the address comparison signals from the plurality of comparison circuits; A logical AND for performing a logical NOR (NOR) operation on the logical AND operation signals from the multiple logical AND gates to generate the error address detection signal when the same error address is obtained. 10. The semiconductor device having a pre-repair test mode according to claim 9, further comprising a sum gate. 11. The control circuit generates first and second gate control signals for controlling a recording operation in response to the error address detection signal and the recording control signal. A gate control signal generator for generating third and fourth gate control signals for controlling a read operation in response to the read control signal; and the external control in response to the first and second gate control signals. A first pass gate for transmitting data from the first pass gate; a memory cell for storing data from the first pass gate; and a memory cell stored in the memory cell in response to the third and fourth gate control signals. A second pass gate for transmitting data, wherein the external data is specified by the input address in response to the third and fourth gate control signals. And a third pass gate for transmitting data stored in the memory cell specified by the input address in response to the third and fourth gate control signals in response to the third and fourth gate control signals. 11. A semiconductor device having a pre-repair test mode according to claim 10. 12. The gate control signal generator includes: a first gate control signal generator for generating the first and second gate control signals for controlling the recording operation; and controlling the read operation. 12. The semiconductor device having a pre-repair test mode according to claim 11, further comprising a second gate control signal generator for generating the third and fourth gate control signals. 13. The first gate control signal generator, a first inverter for inverting the recording control signal to generate an inverted recording control signal, and generating the first gate control signal. And a NAND gate for performing a NAND operation on the inverted recording control signal and the error address detection signal, and the NOT logic for generating the second gate control signal. 13. The semiconductor device having a pre-repair test mode according to claim 12, further comprising a second inverter for inverting the NAND operation signal from a product gate. 14. The second gate control signal generator, wherein a NOT for performing a NAND operation on the read control signal and the error address detection signal to generate the third gate control signal. 14. The pre-charge circuit according to claim 13, further comprising: an AND gate; and an inverter for inverting the NAND operation signal from the NAND gate to generate the fourth gate control signal. A semiconductor device having a repair test mode;