KR100475738B1 - Semiconductor device with function of malfunction cancellation - Google Patents

Abstract

A semiconductor device having a chip inoperable release function is disclosed. A semiconductor device having a memory cell array and a plurality of internal functional circuits for storing data in the memory cell array or for outputting data from the memory cell array includes a chip inoperable signal when the semiconductor device is determined to be defective. A chip inoperable setting unit for outputting a; A chip inoperation canceling unit for outputting a chip inoperation canceling signal for causing the chip inoperational signal to be converted into a chip inoperable signal in response to an externally applied signal; Generating a chip driving signal for releasing the chip inoperable signal in response to the chip inoperable release signal, and having a function selector for providing the at least one internal function circuit to set the chip set in the malfunction state; Restore to the previous state.

Description

Semiconductor device with function of malfunction cancellation

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of restoring a chip set to an inoperable state to a state before the inoperable setting.

In general, a malfunction setting technique is known in the art that allows the operation of a chip to be permanently inhibited with respect to a defective chip screened during the testing of a semiconductor device such as a semiconductor memory device. Such an inoperable setting technique is disclosed in Korean Patent Application No. 1999-23426 filed in the Republic of Korea on June 22, 1999 by the applicant.

The inoperative setting technique described above is derived from the intention that no defective chips screened in the test procedure are classified as good chips and manufactured or shipped as good chips. This is because a manufacturer can receive demeasurement in terms of cost and image of the maker. Therefore, the chip inoperability control circuit 10 as shown in FIG. 1 has permanently disabled the defective chip even in a later process or after shipment.

1 is a block diagram of a semiconductor device having a chip inoperable setting function according to the above-described prior art. Referring to the drawings, the identification signal PMF provided from the chip inoperable control circuit 10 includes the input buffer 11, the output buffer 12, the chip internal circuit 13, and the chip internal DC voltage generator 14. The connection structure configured to be applied to is shown. In FIG. 2, a circuit showing an example of the chip inoperation control circuit 10 of FIG. 1 is illustrated. When the fuse F10 is disconnected between the anode of the diode D1 and the power supply voltage when it is determined to be a bad chip, the node N21 located between one end of the resistor R1 and the cathode of the diode D1 is disconnected. An identification signal PMF for setting the inoperability is output through the waveform shaping buffer 10-1 as a logic level high. When the identification signal PMF is applied as a control signal to at least one of the input buffer 11, the output buffer 12, the chip internal circuit part 13, or the chip internal DC voltage generation part 14. Operation of the chip is inherently prohibited.

The above prior art is useful as a technique that completely excludes the possibility that a bad chip can operate again. However, in some cases, a bad chip needs to be restored to a state prior to chip inoperation setting, that is, before cutting the fuse. For example, a good chip has been identified as a bad chip due to a test error, the fuse has been incorrectly cut due to an operation error in the fuse cutting, a search for the cause of the bad to analyze the bad chip, or repairable at the wafer level is possible. Cases in which a chip is incorrectly determined as a bad chip may occur. When one or more of the above recovery requests occur, a recovery technique capable of recovering a chip set to chip inoperation to its original state is desired.

Accordingly, an object of the present invention is to provide a semiconductor device having a function of restoring a chip set in an inoperative state to a state before being set.

Another object of the present invention is to provide a semiconductor device capable of releasing a chip on which a malfunction function is set.

Another object of the present invention is to find a good chip as a bad chip due to a test error, the fuse is incorrectly cut due to an operation error of the fuse cutting, or to search for the cause of the failure to analyze the bad chip, When the repairable chip at the wafer level is incorrectly determined to be a bad chip, there is provided a method for releasing a malfunction that can reduce a chip set to an inoperative state to an unset state.

It is still another object of the present invention to provide a chip inoperation releasing method and a semiconductor device, which can selectively release a chip set in an inoperation state to a state before the inoperation.

It is still another object of the present invention to provide a method for restoring a chip set to an inoperable state to a state before the inoperation only for a desired time and permanently resetting the inoperable state after a desired time elapses, and thus a semiconductor device. In providing.

In order to achieve the above and other objects, a semiconductor device according to an aspect of the present invention includes a first integrated circuit unit for storing data; A second integrated circuit unit including a plurality of functional groups for reading data stored in the first integrated circuit unit; A first set programming circuit element for setting a first state when the apparatus is determined to be defective; A second set programming circuitry for setting a second state to cause the first state to be bypassed; An output circuit element coupled to the first and second set programming circuit elements, for providing an output signal to at least one of the functional groups in accordance with the first and second states, wherein the output signal The first level of is generated to prohibit the operation of the semiconductor device and the second level of the output signal is generated to restore the disabled operation to the enabled state.

According to still another aspect of the present invention, a semiconductor device includes: a first integrated circuit unit configured to store data; A second integrated circuit unit including a plurality of functional groups for reading data stored in the first integrated circuit unit; A chip inoperation setting section for setting a first state when the device is determined to be defective; A chip inoperation canceling unit for setting a second state in response to an external control signal to cause the first state to be bypassed; A function selection unit connected to the chip disable setting unit and the chip disable release unit, and configured to provide an output signal to at least one of the function groups according to the first and second states, wherein the output The first level of the signal is generated to prohibit normal operation of the semiconductor device and the second level of the output signal is generated to restore the disabled operation to the enabled state.

According to still another aspect of the present invention, a semiconductor device includes: a first integrated circuit unit configured to store data; A second integrated circuit unit including a plurality of functional groups for reading data stored in the first integrated circuit unit; A chip inoperation setting section for setting a first state when the device is determined to be defective; A chip inoperation release portion for setting a second state only during the desired time in response to a pad application signal applied through a pad of the device to ensure that the first state is bypassed only during a desired time; Connected to the chip disable setting unit and the chip disable release unit, providing an output signal to at least one of the functional groups according to the first and second states and after the desired time has elapsed. And a function selector for permanently inhibiting operation, wherein the first level of the output signal is generated to prohibit normal operation of the semiconductor device and the second level of the output signal indicates the prohibited operation of the semiconductor device. It is generated to recover to the enabled state only for a desired time. The desired time period may be set as an application time of the pad application signal.

According to still another aspect of the present invention, a malfunction release method for releasing a semiconductor device set in a malfunction state from a malfunction state includes: generating a malfunction release signal using an internal or external signal; Restoring a malfunction setting signal to a malfunction enable signal in response to the malfunction release signal; And applying the malfunction enable signal to an internal functional circuit of the semiconductor device.

According to the semiconductor device and method described above, by restoring a chip that has become inoperable to an operation enable state, a good chip is found to be a bad chip, or the fuse is incorrectly cut due to an operation error of the fuse cutting, or is defective. When the cause of the defect is to be searched for analyzing the chip, or when the repairable chip at the wafer level is incorrectly determined as the defective chip, there is an advantage that an appropriate operation corresponding thereto is performed.

The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention described below with reference to the accompanying drawings. It should be noted that in the drawings, the same or similar parts to each other are described with the same or similar reference numerals for convenience of description and understanding.

3 is a block diagram of a semiconductor device having a chip inoperable release function according to an embodiment of the present invention. Compared to the configuration of FIG. 1, the semiconductor device of FIG. 3 further includes a chip inoperable release unit 20 and a function selector 30. The function selector 30 ignores the malfunction setting signal PMF indicating the chip disable setting in response to the state of the mal function release signal PMFR generated from the chip disable release unit 20. Or outputs a function control signal (PMF_CON) that allows the function setting to be performed as it is. The chip disable setting unit 10 of FIG. 3 corresponds to the first set of programming circuitry, the chip disable release unit 20 corresponds to the second set programming circuitry, The function selector 30 corresponds to the output circuitry. In addition, the second integrated circuit unit includes an input buffer 11, an output buffer 12, an internal chip unit 13, and an internal DC voltage generator 14 of the chip of FIG. 3. Although not shown in the drawings, a memory cell array of a semiconductor device is included. Here, the malfunction control signal PMF_CON is selectively applied to only one of the input buffer 11, the output buffer 12, the chip internal circuit part 13, or the chip internal DC voltage generation part 14, or as a whole. Can be applied.

As shown in FIG. 4 to FIG. 6, the chip inoperation release unit 20 may generate a malfunction release signal PMFR by fuse cutting or externally execute a mode register set (MRS) command. It can be generated by applying or by applying a voltage to the pad (pad).

4 is a detailed circuit diagram illustrating an example of an implementation of a chip inoperation canceling unit and a function selection unit in FIG. 3. The chip inoperable release part 21 shown in FIG. 4 is an example in which a laser or a current cut fuse F10 is basically used.

It is shown that one end of the fuse F10 is connected to the power supply voltage VCC and the other end thereof is connected to the source of the PMOSFET Q21 in the chip inoperation release unit 21. The drain of the transistor Q21 is connected to the source of another channeled transistor Q22, and the drain of the transistor Q22 is connected in common with the gates of the transistors Q21 and Q22. Therefore, since the transistors Q21 and Q22 function as diodes, the transistors Q21 and Q22 may equivalently correspond to the diode D1 of FIG. 2. A resistor R1 is connected between the drain terminal of the transistor Q22 and the ground voltage VSS. The malfunction release signal PMFR is obtained substantially at the node N21 which is the drain terminal of the transistor Q22. It is shown that a buffer consisting of inverters Q23 to Q25 is connected to the node N21 in order to waveform-shape the malfunction release signal PMFR obtained at the node N21. It can only be replaced by an inverter.

When the malfunction setting signal PMF is generated at a high level, the operation of the semiconductor device is essentially prohibited. According to the object of the present invention, the fuse F10 in the chip inoperation release portion 21 is cut in order to restore such an inoperation state back to the original state. Accordingly, even when the power supply voltage VCC is applied, the two transistors Q21 and Q22 functioning as diodes are turned off to generate a low level voltage at the node N21. The low level voltage is inverted by the buffer and output as a waveform shaped high level. The high level becomes a malfunction release signal PMFR for returning a chip set to an inoperative state to a state prior to being set.

On the other hand, the fuse F10 is not cut when it is not necessary to release the malfunction, so the two transistors Q21 and Q22 are turned on and a high level voltage appears at the node N21. The high level voltage is output as the low level by the buffer. The low level allows the function setting signal PMF to function as a function without substantially canceling the function.

In FIG. 4, the function selector 30 receives the inverter IN1 for inverting the malfunction setting signal PMF and the output of the inverter IN1 as one input and receives the malfunction release signal PMFR. A NOR gate NOR1 for receiving a second input to generate a noah response, and an inverter IN2 for inverting the output of the noah gate NOR1 to generate a malfunction control signal PMF_CON. Therefore, even when the chip function is inhibited by the mal function setting signal PMF applied as the high level by cutting the fuse F10 of FIG. 2, the mal function release signal ( When the PMFR is applied as the high level, the logic level of the malfunction control signal PMF_CON becomes a high level and the chip which is inoperable is returned to its previous state, that is, the operation enable state. If it is not desired to release the malfunction setting, the fuse F10 is not cut. Accordingly, the function selector 30 receives the malfunction setting signal PMF as the high level and the malfunction release signal PMFR as the low level. Accordingly, the inputs of the NOR gate NOR1 are all low level and the output thereof is high, and the logic level of the malfunction control signal PMF_CON output through the inverter IN2 is low to provide the malfunction function. The inoperable state is continuously maintained.

On the other hand, in the case of a normal chip that has not been malfunctioned, the fuse F10 need not be cut. Therefore, since the function selection unit 30 receives both the malfunction release signal PMFR and the malfunction setting signal PMF as a low level, the logic level of the malfunction control signal PMF_CON is output as a high level. do. Thus, in this case the chip is in an enabled state.

In addition, in the case of a normal chip that has not been made a function, even if the fuse F10 is cut, the function selector 30 receives the function release signal PMFR as a high level and sets the function. Since the signal PMF is all received as a low level, the logic level of the function control signal PMF_CON is output as a high level. Again, in this case, the chip is in an enabled state.

The malfunction control signal PMF_CON is a control circuit among chip internal function circuits such as the input buffer 11, the output buffer 12, the chip internal circuit 13, and the chip internal DC voltage generator 14. It is provided to at least one control stage. The circuits of the chip inoperable setting unit 10, the chip inoperable release unit 20, and the function selector 30 may be made on a semiconductor substrate by using a known CMOS manufacturing process, and fabrication of a semiconductor memory. It is advantageous in terms of cost to manufacture together.

Meanwhile, as used herein, the term “bad chip” refers to a soft fail in which some of the memory cells in the memory cell array have a hard fail or satisfies the AC and DC specifications according to a test condition. Chips or memory cells that have a meaning include both normal and false test cases. The hard fail is easily generated when a short occurs between adjacent lines due to particles generated during the process, or a contact hole is blocked.

FIG. 5 is a detailed circuit diagram illustrating another implementation example of the chip inoperable releasing unit and the function selecting unit in FIG. 3. In the case of FIG. 5, the chip inoperation canceling unit 22 generates a function release signal PMFR by receiving a mode register set (MRS) command applied from the outside. Referring to the drawings, the chip inoperation canceling unit 22 may include a transfer gate PG1 that receives the mode register set MRS command, and the malfunction setting signal PMF to switch the transfer gate PG1. Inverter IN10 for inverting the inverter, inverter IN11 for inverting the output of the inverter IN10, inverter IN12 for inverting the output of the transfer gate PG1, and output of the inverter IN12. Inverter IN13 that inverts, the NAND gate ND1 that receives the output of the inverter IN11 and the output of the inverter IN13, and generates a NAND response, and inverts the output of the NAND gate ND1. And an inverter IN14 for generating a function release signal PMFR.

The mode register set (MRS) instruction is externally applied to the high level to bring the semiconductor device set to the malfunction state to the malfunction release state. Accordingly, both inputs of the NAND gate ND1 become high level, and the output of the NAND gate ND1 becomes low level. The low level malfunction release signal PMFR is generated by the inverter IN14.

Therefore, since the function selection unit 30 receives both the malfunction release signal PMFR and the malfunction setting signal PMF as a high level, the logic level of the malfunction control signal PMF_CON is output as a high level. do. Therefore, the chip that was in an inoperable state returns to a previous state, that is, an operation enable state.

The mode register set (MRS) instruction is externally applied as a low level if it is not desired to release the malfunction setting or if it is set back to the malfunction state after the release. Accordingly, the function selector 30 receives the malfunction setting signal PMF as the high level and the malfunction release signal PMFR as the low level. Accordingly, the inputs of the NOR gate NOR1 are all low level, and the output thereof is high, and the logic level of the malfunction control signal PMF_CON output through the inverter IN2 is low, which is caused by the malfunction function. An inoperable state continues or is returned to an inoperable state after an interruption.

FIG. 6 is a detailed circuit diagram illustrating still another example of implementation of a chip inoperation canceling unit and a function selection unit in FIG. 3. In the case of FIG. 6, the chip inoperable release unit 23 receives the pad control signal applied through the pad PAD of the chip to generate the malfunction release signal PMFR. Referring to the drawing, the chip inoperable release unit 23 has a drain connected to an inverter IN20 and an N-type transistor NM1 connected to the pad PAD, and a source of the N-type transistor NM1, The N-type transistor NM2 connected to the ground and the inverter IN21 which inverts the output of the inverter IN20 to generate the malfunction release signal PMFR.

 A high level voltage signal is applied to the pad PAD in order to put the semiconductor device set in the malfunction state into the malfunction release state. As a result, the inverter IN21 generates the high level malfunction release signal PMFR as an output.

Therefore, since the function selection unit 30 receives both the malfunction release signal PMFR and the malfunction setting signal PMF as a high level, the logic level of the malfunction control signal PMF_CON is output as a high level. do. Therefore, the chip that was in an inoperable state returns to a previous state, that is, an operation enable state.

If it is not desired to release the malfunction setting or to set the malfunction again after the release, the pad PAD is applied with a ground signal, for example, a voltage of 0 volts. Accordingly, the function selector 30 receives the malfunction setting signal PMF as the high level and the malfunction release signal PMFR as the low level. Accordingly, the inputs of the NOR gate NOR1 are all low level, and the output thereof is high, and the logic level of the malfunction control signal PMF_CON output through the inverter IN2 is low, which is caused by the malfunction function. The inoperable state continues or is returned from the released state to the inoperable state. Eventually, the operator can release the chip inoperable state only while applying the high level through the pad, perform the desired failure analysis, and then return the bad chip to the function function by not applying voltage through the pad. will be.

Hereinafter, how the malfunction control signal PMF_CON drives the operation of the input buffer 11, the output buffer 12, the chip internal circuit part 13, or the chip internal DC voltage generation part 14. Or control to disable (disable) will be described.

7 to 10 are detailed circuit diagrams of respective circuit blocks for receiving malfunction control signals generated by the function selection unit in FIG. 3.

First, referring to FIG. 7, an example of the configuration of the input buffer 11 in FIG. 3 is shown. In the drawing, an externally applied input signal is commonly applied to the gates of the transistors Q32 and Q33 constituting the clocked inverter through the input pin 11-1 of the semiconductor device, thereby inverting the clocked inverter. After phase inversion by the operation, it is output from the output inverter Q38 via the buffering inverter Q37. Here, when the input signal is a chip select signal for selecting a chip, the input pin 11-1 becomes a chip select / CS pin, and the output signal Pin obtained from the inverter Q38 is a chip select in the chip. It is applied to the control signal generating circuit for controlling the. The clocked inverter further includes transistors Q31 and Q34 and an inverter Q36 for inverting the control signal, and the N-channel MOS transistor Q35 discharges the potential of the output terminal to the ground level when the gate application signal is high level. It plays a role. When the malfunction control signal PMF_CON is applied as the low level to the normal input buffer 11 having the above-described configuration, the operation of the input buffer 11 is caused by the turn-off operation of the transistors Q31 and Q34. It becomes disabled. As a result, the transistors Q32 and Q33 cannot permanently perform the inverting function and thus do not serve as an input buffer. After all, the chip is in a malfunction setting.

On the contrary, when the malfunction control signal PMF_CON is applied to the input buffer 11 as the high level, the input buffer 11 is restored to the enabled state by the turn-on operation of the transistors Q31 and Q34. In this way, the chip set to be inoperable by chip generation by generating the malfunction release signal PMFR as the high level and providing the malfunction control signal PMF_CON of the high level is restored to its original state. Therefore, a good chip is found to be a bad chip, the fuse is incorrectly cut due to an operation error of the fuse cutting, a search for a cause of the failure to analyze the bad chip, or a chip that can be repaired at the wafer level is a bad chip. When misjudged cases occur, the operator releases the set function and performs the required work.

Although only one malfunction control signal PMF_CON is applied to the control terminal of the input buffer 11 in the drawing, the input buffer is actually merged with a control signal for enabling and disabling the input buffer. Can be applied.

Although the internal circuit configuration is different from that of the input buffer 11, the technical control principle may be similarly applied to the output buffer 12.

8, the output driver transistors Q41 and Q42, the transistors Q43a, Q44a, Q45a, Q46c and Q47a constituting the clocked inverter for the output control signal A and the output control signal B The transistors Q43b, Q44b, Q45b, Q46b, and Q47b constituting the clocked inverter and the discharge transistors Q48a and Q48b are included in the configuration of the output buffer 12. An output pin 12-1 is connected to the common drain of the output driver transistors Q41 and Q42 so that high or low level data is provided to the outside during normal operation. When the malfunction control signal PMF_CON is applied as the low level to the normal output buffer 12 having the above-described configuration, the operation of the output buffer 12 is in a disabled state. That is, since the transistors Q43a, Q46a, Q43b, and Q46b are always kept turned off, two clocked inverters cannot permanently perform the inverting function.

When the malfunction control signal PMF_CON is provided as a high level, the transistors Q43a, Q46a, Q43b, and Q46b are turned on to perform an inverting operation on the input signals A and B. As a result, the output buffer is restored to the operation enable state.

Similarly, the malfunction control signal PMF_CON may also be applied to the chip internal circuitry 13 to set a malfunction function or to release the set malfunction function.

Referring to FIG. 9, the NAND gate Q51 and the inverters Q52 and Q53 to Q56 which are sequentially connected to each other constitute a conventional chip internal circuit 13 located in a peripheral circuit of a semiconductor memory device. do. Here, the second clock signal P2 for controlling the internal operation of the chip is normally generated only when the first clock signal P1 is properly transmitted. When the malfunction control signal PMF_CON is applied as a low level to the normal chip internal circuitry 13 having the above-described configuration, the operation of the chip internal circuitry 13 is disabled.

When the malfunction control signal PMF_CON is applied as the high level, the output of the NAND gate Q51 becomes logic inverting the logic level of the first clock signal P1. That is, in this case, the NAND gate Q51 is operated as an inverter. Therefore, the first clock signal P1 to be applied is properly transferred and processed to fulfill the function as the chip internal circuitry 13. As a result, the chip set to Malfunction is restored to the released state.

Although the circuit configuration is different, the technical control principle similarly, the malfunction control signal PMF_CON may be applied to the internal DC (direct current) voltage generator 14. When the malfunction control signal PMF_CON is at the low level, the internal DC voltage generator 14 is in an inoperable state. Examples of the internal DC voltage generator 14 include an internal power supply voltage generator for generating an internal power supply voltage IVCC, a boosted voltage generator for generating a boosted voltage VPP, a negative voltage generator for generating a negative voltage VBB, and a half. ) Half power voltage generator to generate power supply voltage (1 / 2VCC) VBL. In the present exemplary embodiment, only the internal power supply voltage generator 14 'that generates the internal power supply voltage IVCC is shown in FIG. 10 and the control thereof will be described.

Referring to FIG. 10, the operation of the current-mirror circuit is enabled in response to the states of the transistors Q61, Q62, Q63, and Q64 and a control signal applied to constitute a current-mirror circuit. Alternatively, the control transistor Q65 for disabling and the driving transistors Q66 and Q67 having drains connected to the output node N61 and the internal power supply voltage stage IVCC, respectively, constitute a conventional internal power supply voltage generator 14 '. . When the malfunction control signal PMF_CON is applied at the low level to the internal power supply voltage generator 14 ′, the chip is in an inoperable state.

When the malfunction control signal PMF_CON is applied as the high level, the transistor Q65 goes into the turn-on state to form a current path so that the current mirror operation is performed. In this case, the transistor Q66 is turned off. This allows the generator to generate an internal power supply voltage that follows the reference voltage Vref, thus fulfilling its function as the internal power supply voltage generator 14 '. As a result, the chip set to Malfunction is restored to the released state.

As described above, the present invention has been described by way of example only with reference to the drawings, but is not limited thereto and various changes and modifications by those skilled in the art to which the present invention pertains without departing from the technical spirit of the invention. Of course this is possible. For example, it is a matter of course that the internal configuration of the circuit block can be different according to the matter.

As described above, according to the present invention, there is an effect of restoring a chip set to an inoperable state to a state before the inoperable setting.

1 is a block diagram of a semiconductor device having a chip inoperable setting function according to the prior art;

FIG. 2 is an example of a chip inoperable control circuit of FIG. 1.

3 is a block diagram of a semiconductor device having a chip inoperable release function according to an embodiment of the present invention.

4 is a detailed circuit diagram illustrating an example of implementation of a chip inoperation canceling unit and a function selection unit in FIG. 3;

FIG. 5 is a detailed circuit diagram illustrating another example of implementation of a chip inoperation canceling unit and a function selection unit in FIG. 3; FIG.

FIG. 6 is a detailed circuit diagram illustrating still another example of implementation of a chip inoperation canceling unit and a function selection unit in FIG. 3; FIG.

7 to 10 are detailed circuit diagrams of respective circuit blocks for receiving malfunction control signals generated by the function selection unit in FIG.

Claims (11)

(delete) (delete) In a semiconductor device: A first integrated circuit unit for storing data; A second integrated circuit unit including a plurality of functional groups for reading data stored in the first integrated circuit unit; A chip inoperation setting unit for setting a first state when the semiconductor device is determined to be defective; A chip inoperation canceling unit for setting a second state in response to an external control signal provided as a mode register set command or a pad applying signal to cause the first state to be bypassed; A function selection coupled to the chip disable setting unit and the chip disable release unit, for providing an output signal of a first level or a second level to at least one of the functional groups according to the first and second states; Wherein the first level of the output signal is generated to prohibit normal operation of the semiconductor device and the second level of the output signal is generated to restore the prohibited semiconductor device to an enabled state. A semiconductor device, characterized in that. (delete) In a semiconductor device: A first integrated circuit unit for storing data; A second integrated circuit unit including a plurality of functional groups for reading data stored in the first integrated circuit unit; A chip inoperation setting unit for setting a first state when the semiconductor device is determined to be defective; A chip inoperation release portion for setting a second state only during the desired time in response to a pad application signal applied through a pad of the device to ensure that the first state is bypassed only during a desired time; A first level or a second level output signal to the at least one functional group according to the first and second states, and connected to the chip inoperation setting unit and the chip inoperation canceling unit; And a function selector for permanently inhibiting the operation of the device after this elapses, wherein the first level of the output signal is generated to prohibit normal operation of the semiconductor device and the second level of the output signal. Is generated to restore the disabled operation to the enabled state only during the desired time. The semiconductor device according to claim 5, wherein the desired time period is set as an application time of the pad application signal. A semiconductor device having a memory cell array and a plurality of internal functional circuits for allowing data to be stored in or to be output from the memory cell array. A chip inoperation setting unit which outputs a chip inoperation signal when the semiconductor device is determined to be a defect; A chip inoperation canceling unit for outputting a chip inoperation canceling signal for causing the chip inoperational signal to be converted into a chip inoperable signal in response to an externally applied signal; And a function selector which generates a chip driving signal for releasing the chip disable signal in response to the chip disable release signal and provides the chip drive signal to at least one internal function circuit. 8. The semiconductor device of claim 7, wherein the internal functional circuits include at least one input buffer. The semiconductor device of claim 8, wherein the internal functional circuits include at least one output buffer. The semiconductor device of claim 9, wherein the internal functional circuits include at least one DC voltage generator. (delete)