KR100361082B1 - Semiconductor device with malfunction control circuit and control method therefore - Google Patents

Abstract

In order to fundamentally prevent normal operation of a defective chip, a semiconductor device having a chip inoperable control circuit and a chip inoperable control method thereof are disclosed. Such a semiconductor device has a cutting part determined in a manufacturing process according to whether a chip is found to be defective or not, and one end is connected to a first power source, and the other end is connected between the other end of the fusing part and a second power source, depending on whether the cutting part is cut or not. The chip internal function circuits are provided with a chip inoperation control circuit inside the chip, the chip generating unit including a signal generator for generating a determination signal for determining a bad chip and supplying the at least one chip internal function circuit. Characterized in that it is activated or deactivated according to the value of the determination signal.

Description

Semiconductor device with malfunction control circuit and control method therefore

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor integrated circuit device having a circuit which essentially prevents operation of a chip, and a method of controlling chip inoperability.

Typically, semiconductor device manufacturers are conducting electrical tests on each chip to see if the integrated circuit chips in the wafer state and the chips in the package state reliably perform their respective set operations. Such electrical tests include DC parameter tests, which check the characteristics of the device's current and voltage, and dynamic tests, which test the device's actual operating functions.

Each chip tested in the wafer state is classified as good or bad according to the test results. Here, the defective products which can be repaired by using the redundancy parts manufactured as spares among the defective products are repaired for improving the yield. After the test is performed again only on the repaired chip, the bad chip is finally screened. In this way, a semiconductor manufacturing process for testing and repairing chips is called an electrical die sorting (EDS) process, which is designed to recover a repairable chip and to feed back an abnormal lot early. In order to do so, it is also an essential process performed to reduce the packaging cost in the subsequent assembly process and the test cost of the package inspection line by removing the defective chip early. After the die process is completed, the chips are separated from each other by a shoring operation that cuts along the cutting line of the wafer, and the separated chips are assembled by the assembly process. Subsequently, package tests, including on / off tests to check for wiring defects that may have occurred in the dies or assembly process, and burn-in tests that apply electrical characteristics to stress the chip to eliminate initial defects, are typically performed. Is done. According to the result of the package test, a chip having a malfunction in chip operation is screened as a defective chip.

On the other hand, for some users who do not prefer a repaired chip and require a high reliability integrated circuit, the user has a function to recognize whether the repaired chip is a repaired chip, and a recognition signal providing circuit installed in the integrated circuit chip is washed out. (Varshney) et al., Are incorporated under the title "IDENTIFICATION OF REPAIRED INTEGRATED CIRCUITS" of US Pat. No. 4,480,199, issued October 30, 1984. FIG. 1 shows a representative circuit diagram of the circuit diagram of the prior patent, and is composed of transistors T1 and T2 and a fuse F1 installed between the pin 10 and the power supply voltage Vcc. The transistors T1 and T2 are turned on according to whether the fuse F1 is cut when a voltage equal to or greater than the sum of the power voltage Vcc and the threshold voltages of the transistors T1 and T2 is applied to the pin 10. Turned off or turned on. When the fuse F1 is cut off, since the transistors T1 and T2 are turned off, no current flow is detected between the pin 10 and the power supply voltage Vcc. When the fuse F1 is not cut, since the transistors T1 and T2 are turned on, a current flow is detected between the pin 10 and the power supply voltage Vcc. Therefore, as the fuse F1 is not cut or not cut, the presence or absence of a chip repair can be notified to the user. For example, if the manufacturer has defined to cut the fuse F1 when the chip is repaired, the user of the chip may check the repaired chip according to whether the current flow is detected.

However, it is very difficult to make a bad chip inoperable by using or applying the above circuit. This is because the circuit of the prior patent does not affect the normal operation of the chip. That is, a repaired chip, an unrepaired good chip, an unrepaired defective chip, a defective chip that is difficult to operate normally, and a non-repaired chip, regardless of whether the fuse F1 in the circuit is cut or not, aperiodically This is because both repeated chips and non-repairable defective chips provide room for operation as a normal chip. If a bad chip is shipped and operated as a normal chip, it may not perform a normal function, thereby degrading the performance of the entire system employing the chip and causing a fatal error.

A defective chip that is unrepairably screened in the wafer state or in the package state is intended to intentionally undermine the image of the manufacturer or manufacturer making the finished product due to management negligence or after receiving the wafer from which the chip was manufactured by the manufacturer. A manufacturer may receive a demage in terms of cost and image of the manufacturer when the product is classified and manufactured as a good chip or shipped as a good chip by an intentional party or group of intent. Therefore, it is necessary for the defective chip to be essentially prohibited from the operation of the chip even in the post-process or after shipping.

Since the prior art as described above provides the chip with normal operating conditions irrespective of whether the chip is good or bad, it is necessary to permanently prohibit the operation of the chip permanently even in the post-process or after the product is shipped. There is a problem that is difficult to use. Therefore, the manufacturer has been burdened with strictly managing accordingly in order to prevent de-magination in terms of cost and image of the maker.

Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit device having a circuit which essentially prohibits the operation of the chip for a defective chip.

It is another object of the present invention to provide a method for permanently prohibiting normal operation of a chip, which can not be repaired, even in a post-process or after shipment.

It is still another object of the present invention to provide a semiconductor memory device and a chip inoperation control method that can alleviate the burden of a manufacturer who must strictly manage a defective chip in order to prevent de-magnetization in terms of cost and image of a maker. have.

It is still another object of the present invention to provide a semiconductor memory or non-memory and thus a chip which can substantially prevent a non-repairable defective chip from being shipped to a customer even if the chip is sold or provided to a secondary processor as it is. An operation control method is provided.

In order to achieve the above objects and other objects, the semiconductor device according to an aspect of the present invention comprises a fusing portion having one end connected to a first power source and whether or not cutting is determined in a manufacturing process according to whether chips are found to be defective; It is connected between the other end of the fusing unit and the second power supply to generate a determination signal for determining whether the chip is bad according to the cutting state of the fusing unit and supplied as a signal indicating the operation prohibition to at least one of the internal chip functional circuit of the chip A signal generation unit comprising: a chip inoperable control circuit including a chip inside the chip, so that the chip internal functional circuits are activated or deactivated according to the value of the determination signal.

The method of controlling chip inoperation may include determining whether a fuse is cut in a manufacturing process according to whether a chip is found to be defective, generating a status signal according to whether the fuse is cut under normal operating conditions, and generating the chip. And providing a status signal as a signal indicating the operation prohibition to at least one of the control terminals of the chip internal function circuits, so that only a chip that is found to be inoperable is in an inoperable state.

According to the above-described semiconductor device and method, the normal operation of the chip can be permanently prohibited in the post-process or even after the product is released for the non-repairable defective chip. The burden on the manufacturer, who must strictly control the product, is reduced.

1 is a recognition signal generation circuit diagram according to the related art employed in a semiconductor device for recognizing a repaired integrated circuit chip;

2 is a block diagram of a semiconductor device having a chip inoperable control circuit according to an embodiment of the present invention; and

3A to 7 are detailed circuit diagrams of respective parts of FIG. 2.

The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention described below with reference to the accompanying drawings. It should be noted that in the drawings, the same or similar parts to each other are described with the same or similar reference numerals for convenience of description and understanding.

First, FIG. 2 is a block diagram of a semiconductor device including a chip inoperable control circuit 10 according to an exemplary embodiment of the present invention, which is also referred to as a potential signal (or a state signal provided by the chip inoperable control circuit 10). Jim) The connection structure is shown so that the PMF is applied to the input buffer 11, the output buffer 12, the chip internal circuitry 13, and the chip internal DC voltage generator 14. The potential signal may be provided only to at least one of the input buffer 11, the output buffer 12, the chip internal circuit 13, and the chip internal DC voltage generator 14. This is because, under normal operation, if any one of the above blocks does not function properly, the chip operation becomes impossible.

Specific embodiments of the chip inoperable control circuit 10 of FIG. 2 are shown in FIGS. 3A and 3B, respectively. Referring to FIG. 3A, it is shown that one end of the fuse F10 serving as a fusing part is connected to a first power source, for example, a power supply voltage VCC and the other end thereof is connected to an anode of the diode D1. A resistor R1 is connected between the cathode terminal of the diode D1 and a second power supply, for example, the ground voltage VSS. At the node N21, which is the cathode terminal of the diode D1, the potential signal, also called a state signal, is obtained. The state signal is provided in the form of a voltage signal as a response signal according to whether the fuse F10 is cut. For example, if any chip in the wafer condition test turns out to be a non-repairable chip, the fuse F10 is cut. Then, the diode D1 is in a non-conducting state, and a low level voltage is generated at the node N21. Conversely, if any chip is found to be a good good chip in a wafer condition test, the fuse F10 is not cut. Then, when the power supply voltage VCC is applied, the diode D1 is in a conductive state, and a high level voltage is generated at the node N21. In the drawing, the fuse F10 may be made of polysilicon or metal, and the cutting of the fuse may be performed by laser, high current, or another technique well known in the art. Preferably, blown by a laser when using a doped polysilicon fuse.

Referring to FIG. 3B, similarly to FIG. 3A, it is shown that one end of the fuse F10 serving as the fusing part is connected to the power supply voltage VCC and the other end thereof is connected to the source of the channel channel transistor (PMOS) Q21. The drain of the transistor Q21 is connected to the source of another channeled transistor Q22, and the drain of the transistor Q22 is connected in common with the gates of the transistors Q21 and Q22. Thus, since the transistors Q21 and Q22 function as diodes, they may correspond to the diode D1 in FIG. 3A. A resistor R1 is connected between the drain terminal of the transistor Q22 and the ground voltage VSS. The potential signal is substantially obtained at the node N21 which is the drain terminal of the transistor Q22. In order to shape the waveform of the potential signal obtained at the node N21, a buffer 10-1 consisting of inverters Q23, Q24 to Q26 may be connected to the node N21. As in the case of FIG. 3A, the status signal as the potential signal indicates whether the fuse F10 is cut. When the chip employing the circuit of Fig. 3B is found to be a bad chip, the fuse F10 is blown by the laser. Then, even when the power supply voltage VCC is applied, the two transistors Q21 and Q22 functioning as diodes are turned off, and a low level voltage is generated at the node N21. The low level voltage is buffered by the buffer 10-1 and then output as a standardized low level. The normalized low level is the status signal indicating a bad chip. In contrast, when the chip employing the circuit of Fig. 3B is found to be a normal good chip, the fuse F10 is not cut. Then, when the power supply voltage VCC is applied, the two transistors Q21 and Q22 are turned on so that a high level voltage appears at the node N21. The high level voltage is output as a formatted high level after being buffered by the buffer 10-1. The standardized high level is the status signal indicating a good chip. The state signal PMF controls at least one of chip internal function circuits such as at least one of control terminals among the input buffer 11, the output buffer 12, the chip internal circuit 13, and the chip internal DC voltage generator 14. Are provided at the end. The chip inoperable circuit can be made on a semiconductor substrate using a known CMOS manufacturing process, and it is advantageous in terms of cost to manufacture together the semiconductor memory.

How the chip inoperable control circuit 10 including the fusing part corresponding to the fuse (F10) and the signal generating part corresponding to the diode (D1) and the resistor (R1) is how the input buffer 11, the output buffer ( 12), the operation of controlling the operation of the chip internal circuit unit 13 or the chip internal DC voltage generation unit 14 to a driving state (enabled) or disabled state (disabled) will become more apparent in the following description.

First, referring to FIG. 4, an example of the configuration of the input buffer 11 in FIG. 2 is shown. In the drawing, an external input signal is commonly applied to the gates of the transistors Q32 and Q33 constituting the clocked inverter through the input pin 11-1 of the semiconductor device, and is driven by the inverting operation of the clocked inverter. After the phase is inverted, it is output from the output inverter Q38 via the buffering inverter Q37. Here, when the external input signal is a chip select signal for selecting a chip, the input pin 11-1 becomes a chip select / CS pin, and the signal Pint obtained from the inverter Q38 controls chip selection within the chip. Is applied to the control signal generating circuit. The clocked inverter further includes transistors Q31 and Q34 and a control signal inverting inverter Q35, and the N-channel MOS transistor Q36 grounds the potential of the output terminal when the control signal is in a first state, for example, a low level. Discharge to the level. When the potential signal or the state signal PMF generated from the chip inoperable control circuit 10 as shown in FIG. 3A or 3B is applied as a control signal to the conventional input buffer 11 having the above-described configuration, the chip is a bad chip. In this case, the operation of the input buffer 11 is disabled. That is, when the chip is found to be a bad chip and the state signal PMF is provided at the low level, the transistors Q31 and Q34 always maintain the turn-off state. As a result, the transistors Q32 and Q33 cannot permanently perform the inverting function and thus do not serve as an input buffer. On the contrary, when the chip turns out to be a good chip and the state signal PMF is provided as a high level, the transistors Q31 and Q34 are kept turned on. Thus, the inverting operation can be performed on the input signal, thereby fulfilling the function of the input buffer. Although only one state signal PMF is shown to be applied to the control terminal of the input buffer 11 in the drawing, the input buffer is actually applied by merging with the control signal for controlling enable and disable. It is desirable to. In the case of integrating the state signal PMF and the control signal, the combinational logic preferably uses a logic gate that generates an end or a NAND response. As a result, the signal generator in the chip inoperable control circuit 10 that generates a potential signal representing one of the first and second states, depending on whether the fusing unit is cut or not, disables or disables the input buffer 11. As a result of the control, it can be seen that the defective chip that is shipped even if the input buffer becomes inoperable, the entire chip becomes inoperable.

Although the internal circuit configuration is different from that of the input buffer 11, the technical control principle is similar, and the state signal PMF may be applied to the output buffer. In this case, the output buffer becomes inoperable in the case of a bad chip. 5, the output driver transistors Q41 and Q42, the transistors Q43a, Q44a, Q45a, Q46c and Q47a constituting the clocked inverter for the output control signal A and the output control signal B The transistors Q43b, Q44b, Q45b, Q46b, and Q47b constituting the clocked inverter and the discharge transistors Q48a and Q48b constitute the output buffer 12. An output pin 12-1 is connected to the common drain of the output driver transistors Q41 and Q42 to provide a high or low level to the outside during normal operation. When the status signal PMF is applied as a control signal to the normal output buffer 12 having the above-described configuration, when the chip is a bad chip, the operation of the output buffer 12 is disabled. That is, when the chip is found to be a bad chip and the state signal PMF is provided at the low level, the transistors Q43a, Q46a, Q43b, and Q46b always maintain the turn-off state. As a result, the two clocked inverters will not be able to perform their respective inverting functions permanently, resulting in an incorrect output buffer. On the contrary, when the chip is found to be a good chip and the state signal PMF is provided at a high level, the transistors Q43a, Q46a, Q43b, and Q46b remain turned on. Thus, it is possible to perform the inverting operation on the signals A and B applied, thereby fulfilling its function as an output buffer. Similarly, although only one state signal PMF is shown to be applied to the control terminal of the output buffer 12, it is preferable to actually apply the output buffer with a control signal for controlling the enable and disable. Do. The combination of the state signal PMF and the control signal uses a logic gate to generate an end or NAND response. As a result, the signal generator in the chip inoperable control circuit 10 controls the enable or disable of the output buffer 12, so that the output buffer in a defective chip shipped out of the device becomes inoperable.

Similarly, the state signal PMF is also applied to the chip internal circuitry 13 to control the chip internal circuitry to an inoperable state in the case of a bad chip. Referring to FIG. 6, the NAND gate Q51 and the inverters Q52 and Q53 to Q56 which are sequentially connected to each other constitute a conventional chip internal circuit 13 positioned in a peripheral circuit of a semiconductor memory device. do. Here, the second clock signal P2 for controlling the internal operation of the chip is normally generated only when the first clock signal P1 is properly transmitted. When the state signal PMF is applied as a control signal to the normal chip internal circuitry 13 having the above-described configuration, when the chip is a bad chip, the operation of the chip internal circuitry 13 becomes disabled. That is, when a chip is found to be a bad chip and the state signal PMF is provided at a low level, the output of the NAND gate Q51 is always kept high regardless of the logic level of the first clock signal P1. As a result, the output of the inverter Q56 connected to the last stage is fixed at a low level, which in turn does not produce an output in response to the logic of the first clock signal P1. On the contrary, when a chip is found to be a good chip and the state signal PMF is provided as a high level, the output of the NAND gate Q51 becomes logic inverting the logic level of the first clock signal P1. That is, in this case, the NAND gate Q51 is operated as an inverter. Accordingly, the applied first clock signal P1 is properly transmitted and processed to fulfill the function of the chip internal circuit unit 13.

Although the circuit configuration is different, the technical control principle similarly, the state signal PMF may be applied to the internal DC (direct current) voltage generator 14. In this case, in the case of a defective chip, the internal DC voltage generator 14 becomes inoperable. Examples of the internal DC voltage generator 14 include an internal power supply voltage generator for generating an internal power supply voltage IVCC, a boosted voltage generator for generating a boosted voltage VPP, a negative voltage generator for generating a negative voltage VBB, and a half. ) Half power voltage generator to generate power supply voltage (1 / 2VCC) VBL. In the present exemplary embodiment, only the internal power supply voltage generator 14 ′ that generates the internal power supply voltage IVCC is shown in FIG. 7 and the control thereof will be described. Referring to FIG. 7, the operation of the current-mirror circuit is enabled in response to the states of the transistors Q61, Q62, Q63, and Q64 and a control signal applied to constitute a current-mirror circuit. Alternatively, the control transistor Q65 for disabling and the driving transistors Q66 and Q67 having drains connected to the output node N61 and the internal power supply voltage stage IVCC, respectively, constitute a conventional internal power supply voltage generator 14 '. . When the status signal PMF is applied as the control signal to the internal power supply voltage generator 14 ', the operation of the internal power supply voltage generator 14' becomes disabled when the chip is a bad chip. That is, when a chip is found to be a bad chip and the state signal PMF is provided at a low level, the transistor Q65 is turned off and the transistor Q56 is turned on so that the node N61 remains high and eventually drives. The transistor Q67 is always kept turned off. Therefore, since the internal power supply voltage generator 14 'cannot permanently perform the internal power supply voltage generation operation by the current mirror method, the internal power supply voltage generator 14' never generates the internal power supply voltage IVCC following the reference voltage Vref. As a result, the internal power supply voltage generator 14 'becomes inoperable. On the contrary, when the chip is found to be a good chip and the state signal PMF is provided as the high level, the transistor Q65 goes to the turn-on state to form a current path, so that the current mirror operation is performed. In this case, the transistor Q56 is turned off. This makes it possible to generate an internal power supply voltage that follows the reference voltage Vref, thus fulfilling the function as the internal power supply voltage generator 14 '. Similarly, although only one state signal PMF is shown to be applied to the control terminal of the internal power supply voltage generator 14 ', the control signal actually controls the enable and disable of the internal power supply voltage generator 14'. It is preferable to merge with and apply. In this case, the integration of the state signal PMF and the control signal uses an AND gate or a NAND gate. As a result, the signal generator in the chip inoperable control circuit 10 controls the enable or disable of the internal power supply voltage generator 14 ', so that the internal power supply voltage generator 14' in a defective chip that is shipped out of operation operates. It becomes impossible.

As described above, the present invention has been described by way of example only with reference to the drawings, but is not limited thereto and various changes and modifications by those skilled in the art to which the present invention pertains without departing from the technical spirit of the invention. Of course this is possible. For example, depending on the case, the internal structure of the fusing unit and the signal generating unit may be changed or the number of transistors functioning as a diode may be decreased, or the fuse may not be cut in the case of a bad chip, or as a generated state signal, in addition to the internal circuits of the chip. It is also noted that it is possible to disable the control function of an external device such as a microprocessor or a memory controller or to make the microprocessor recognize the status signal so that the content of the bad chip is displayed on the screen as text.

As described above, according to the present invention, there is an effect that the normal operation of the chip can be permanently inhibited even in the post-process or after shipping the defective chip that cannot be repaired. Therefore, the burden on the manufacturer to strictly follow-up on the defective chip is reduced, which has the advantage of reducing the de-magination in terms of cost and image. In addition, since the shipment of defective chips is virtually prevented, the advantage of contributing to the activation of the wafer business is obtained.

Claims (18)

A fusing unit in which a cutting part is determined in a manufacturing process according to whether a chip is found to be defective and one end is connected to a first power source; It is connected between the other end of the fusing unit and the second power supply to generate a determination signal for determining whether the chip is bad according to the cutting state of the fusing unit and supplied as a signal indicating the operation prohibition to at least one of the internal chip functional circuits Signal generator: And a chip inoperable control circuit inside the chip, wherein the chip internal function circuits are activated or deactivated according to the level of the determination signal so that the operation of the chip is inherently prohibited when the chip is deactivated. Integrated circuit devices. The semiconductor integrated circuit device of claim 1, wherein the chip internal functional circuits include at least one input buffer. 2. The semiconductor integrated circuit device of claim 1, wherein the chip internal functional circuits comprise at least one output buffer. The semiconductor integrated circuit device of claim 1, wherein the chip internal functional circuits include at least one DC voltage generator. 2. The semiconductor integrated circuit device according to claim 1, wherein the first power source is a power source voltage and the second power source is a ground voltage. The semiconductor integrated circuit device according to claim 1, further comprising a signal waveform shaping buffer between the signal generator and the chip internal function circuit. The semiconductor integrated circuit device according to claim 1, wherein the chip is a semiconductor memory device. 8. The semiconductor integrated circuit device according to claim 7, wherein the fuse is a fuse capable of cutting by laser light. 8. The semiconductor integrated circuit device according to claim 7, wherein the fuse part is a fuse that can be cut by a current. The method of claim 1, wherein the signal generating unit, the anode corresponding terminal is connected to the other end of the fusing unit to form a current path when the fuse is not blown fuse unit and the cathode corresponding terminal of the diode equivalent device and the second power source And a resistor connected between the semiconductor integrated circuit device. The method of claim 1, wherein the signal generator comprises a MOS transistor connected to a source of the other end of the fusing part to form a current path when the fuse of the fusing part is not blown, a resistor connected between the drain of the MOS transistor and the second power supply. Semiconductor integrated circuit device characterized in that. In the chip inoperation control method: Determining whether a fuse is cut in a manufacturing process according to whether a chip is found to be defective; Generating a signal for determining that the chip is defective according to whether the fuse is cut; By providing the generated determination signal to the chip internal function circuits as a signal indicating whether operation is prohibited, A control method characterized in that the control is performed so that only a defective chip is found to be inoperable. 13. The method of claim 12, wherein the chip internal functional circuits comprise at least one input buffer. 13. The method of claim 12, wherein the chip internal functional circuits comprise at least one output buffer. The control method of claim 12, wherein the internal chip circuits include at least one DC voltage generator. 13. The method of claim 12, wherein the chip is a semiconductor memory device. The control method of claim 16, wherein the fuse is a fuse that can be cut by laser light. The control method of claim 16, wherein the fuse is a fuse that can be cut by a current.