TW502427B - Semiconductor device with malfunction control circuit and controlling method thereof - Google Patents

Abstract

An integrated circuit of a semiconductor device has a chip malfunction controlling circuit embedded in a chip. The circuit comprises a fusing part, to which a cutting will be made in the manufacturing process according to the result of the discrimination of a defect in a chip, with one end thereof being connected to a first power terminal. A signal generating part is connected to the other end of the fusing part, and to a second power terminal. The signal generating part generates a discrimination signal of discriminating whether the chip is defective or not, by whether the fusing part has been cut or not. The discrimination signal is supplied to at least one internal function circuit, and inhibits its operation if the fusing part has been cut. Furthermore, the chip malfunction controlling method comprises generating a discrimination signal that has a first state, if a test fuse has been cut and a second state if the test fuse has not been cut. Then the discrimination signal is applied to the chip internal function circuits, to thereby inhibit their operation if the fuse has been cut.

Description

JVU427 V. Description of the invention (l) The parent also refers to the related application. This application claims priority from Korean Priority Document No. 99-23426, which was submitted to the Korea Industrial Property Agency on June 22, 1999. Its documents are therefore available reference. BACKGROUND OF THE INVENTION The scope of the invention The invention relates to a semiconductor device, more specifically a semiconductor device product. The circuit has a wafer malfunction control circuit, and a method for prohibiting the operation of the wafer components, which was previously regarded as a defective wafer. Description of the prior art Generally speaking, semiconductor devices complete all chip power tests, and check whether the integrated circuit of the wafer I5 white segment S chip or the wafer integrated circuit can reliably perform its pre-operation. An electrical test like that is classified as a parameter test for detecting the current- or voltage-like properties of a device, and a dynamic test is used to check the computing function of the device. The test wafers in the white circle segment P are classified into non-defective products according to the test wafers: and: defective products. At this time, some defective products can be repaired and used as spare parts and spare parts. If this improves the final product output rate. Then, a test is performed to allow the repaired wafer to screen out the last defective wafer. In just the case, the wafer has been tested or repaired in the process of manufacturing semiconductor devices, and the electrical die screening (EDS) process. This EDS procedure has been used to repair the wafer, perform an early feedback step to a defective section, and remove the defective wafer as soon as possible. If this reduces the packaging cost in the next combination process, or the test cost of the test line in the next packaging stage .纟 Complete the eds process

Page 6 502427 V. Description of the invention (2), after the sequence, each wafer is cut by a dicing process' and cut according to each wafer cutting line, and then assembled in subsequent procedures. On the other hand, subsequent packaging level tests are generally implemented: an on / off test to detect defective wiring that may have occurred in the previous EDS or its assembly process; a burn-in test to detect the electrical properties of the chip under pressure, Remove defective wafers as soon as possible. According to the results of the packaging test, any defective wafers will be screened out. On the other hand, users do not like repaired wafers. Their demand for high-reliability integrated circuits usually results in a necessary condition that the wafers they do not need to be identified are originally defective and finally repaired. Prior uranium technology focused on circumventing this necessary condition and instead agreed to it. For example, a line has been introduced to generate identification signals, which provides a function of user information to check whether the chip has been repaired. This circuit was described by Barshney and others in U.S. Patent 4,480,199, entitled "Identified by Repairing Integrated Circuits," which attempted to provide a method of repairing the circuit and behaved as if the chip had not been repaired before. Article: 1 由 系The spoon diagram case is used to illustrate a different representative circuit, which is described in the previous patent documents, including the transistor between 1 VCC. In T2 and a fuse at the 10th pin and power supply 1 When not, when a test, voltage Voltage, and Lei Yuelin T1 το, electric power, add the VCC supply transistor η, T2 = K: 2 threshold voltage is applied to the 10th pin, the off state. Fuse two :, electric = front fuse F1 cut A breaking or non-cutting current flows through the 丨. Pin and supply 1 fuse π will be detected before it is not cut. If 'τ2 will be in its ON state. If so, 〇υ ^ 427 friend, invention description ( 3) The current flowing between the 10th pin and the supply voltage vcc will be detected. Based on whether fuse F 1 is cut or not, the user can identify whether the chip has been repaired. For example, if the chip manufacturer decides Fuse F 丨 If a When repaired, the chip must be cut off, and the user can determine that the chip has been repaired by detecting the current flowing through the chip. The point is that the manufacturer will know a specific voltage test beyond a normal parameter ~ specific pins. In fact, It is a voltage with at least two critical voltages higher than the normal voltage before attempting to detect the current. In the opposite case the end user will not know where to test or how to test, but the manufacturer knows it. Therefore, it is difficult. It is difficult to implement after repair and cannot be estimated, and the group normally performs the previous normal operation. The product introduction has been repaired with a significant meaning. The energy is the action previously mentioned. Finally, it is ignored to implement the non-defective wafer. Wafers, repaired wafers become semiconducting functions, and technology exists — right after the market. The fact is that the burden is strictly controlled. In fact, 'If the previous test is cut off, the wafer is not operated often. The correct evaluation may not be unified. The implementation of the wafers that are being made by the end-users and the wafer producers harm their lives and finally they may The user's circuit makes the fuse F1 in the repaired chip identification circuit cut or there is no type of wafer. If the repaired, unrepaired defective chip is irregular, normal operation is not flawless. Right chip Decided to be a non-defective wafer in a non-defective device. It produces a fatal operation that fails the entire system problem, where the defective wafer will allow the process to be made, or even in the case of a defective tortoise wafer, the fact that this process is concealed will eventually make the right Conceal the maker. If so, crystallography to avoid increased production costs, or the wafers becoming integrated with larger devices, have shown flaws. This is the most

Observation 427 V. Description of Invention (4) You can be sure that the device was not ruled out at the beginning. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an integrated circuit of a semiconductor device for fundamentally prohibiting a defective wafer to avoid performing any operation. Another object of the present invention is to provide an integrated circuit for a semiconductor device to prevent defective wafers that cannot be repaired from performing their normal operations during the manufacturing process, or even after the final product is put on the market. The burden of action control of the present invention further avoids the present invention and its wafers from being misplaced, in case the most chip may be sold. In order to complete the circuit, there is a fuse assembly in which a group source is generated based on the identification signal. Signal to determine the internal function line, and the crystal number, if one test is another method is used to mitigate any endangering the other purpose is the cancellation of the sale or provision of the previous chip of the invention. Whether the defective chip is connected to the fuse produced by the production module, and if the chip climbing test-controlled fuse has provided the semiconductor manufacturer with strict production costs and the semiconductor method, it is used by the actual producer to detect the second producer. For the purpose, its control circuit is embedded with a first power supply, a fuse element is generated and an identification crystal is cut off, and then the fuse assembly manufacturing method includes cut-off, and the first memory device, which manages defective business image. Memory or non-memory can not be avoided, even if the wafer provides semiconductors into it. For the wire end, one end of the cutting action will be connected, and whether the defect identification signal is connected to the cut, the first state and the second state are prohibited. If it is a negative memory device of the wafer and the wafer is wrong, repair the defective crystal device. The integration path includes a guarantee that will be achieved during the manufacturing process. As soon as the second electrical identification is received, it is added to the chip to stop its operation. Identification of the status of the fuse is not cut. 5. Description of the invention (5). An identification signal is then applied to the chip if the fuse is cut. Depending on the semiconductor device and its wafers, it is always forbidden to work on the wafers, or even if the wafers are made of defective ^ wafers. . If the internal function circuit prohibits its operation control method by mistake, the manufacturing process that cannot be repaired will be implemented after the normal operation of the product is introduced into the market. This simplifies the reduction of production costs and the protection of the business conglomerate. The purpose and content of the present invention can be described briefly below. Among them, the following description of the embodiments of the drawings is shown in FIG. 1 is a circuit diagram, using your # Including a semiconductor nightmare for identification signal generation circuit, its integrated circuit; &; clothing manufacturer identification according to the repair in the prior art Figure 2 is a block diagram, used for one of the seven examples of minor tasks $ 私 & ^ + Conductor device, if the Japanese film malfunction control circuit according to the embodiment of the present invention; and Figures 3a to 7 are used; ^ h main- # ^, the component specific circuit diagram described in FIG. 2 type. In the detailed description of the invention, t2: 2 and: The contents can be read from the following description of the embodiments of the drawings. 7 ,,,,, and must be the same or similar reference numerals for the same and similar components in the diagrams. Conducive to narration and understanding. First, the phase gate f. First, FIG. 2 is a block diagram for describing a semiconductor device for controlling a malfunction circuit according to an embodiment of the present invention. -Controlled by the malfunction of the chip, the potential signal PMF (or also referred to as a status signal) supplied by the circuit 10 is added to an input buffer H11,-an output buffer 12,-the internal circuit components of the chip.

Page 10 502427 V. Description of the invention (6) and two internal DC voltage generating components 14 which will be connected to each other. After 迳%, the potential signal can provide at least those input buffers u π chip internal circuit components 13 and chip internal components = at least one of the _. If any of those sections does not work correctly: it becomes impossible for the chip to complete its normal operation. Figure 2 is a better implementation of the chip operation control and circuit, which is described in Figure 3 & In addition, the anode end of the pole D1 and the resistor R1 are connected to the cathode 1 and the power source end of the diode D1, for example, between the ground voltage vss. A potential voltage is also •, the status signal is obtained from the node N21 at the cathode terminal of the diode D1. The status signal is a response signal, according to whether the fuse F10 is cut or not, = = = the signal is supplied. For example, if a predetermined wafer is tested for repair at the wafer stage, the fuse F10 is cut off. The secondary ship then goes to its state, which is grounded to node N21. In the opposite case, if the predetermined wafer 疋 and 疋 are regular non-defective wafers, the fuse F0 is not cut. The most round 3 adds the voltage KX, the diode D1 || to its continuous state, a high level;-the voltage is generated at the node N21. In the figure, the fuse F10 can be made of polysilicon or gold. The fuse can be made by laser beam, high current or its well-known technology. It is better to cut the fuse through the jet laser beam. Polysilicon fuse. In order to trim the waveform of the potential signal required by the node, a buffer 10- 丨 is composed of inverters Q2 3 to Q26 and can be connected to node N21. Status signal,

Page 11 502427 V. Description of the invention (7) '~~~ — Change the electric potential signal indicating fuse F1 to 0 or not. If the fuse F 1 0J; the knife is broken, then even if the power supply vc (:, a low-level voltage is generated at node N2 1. The low-level voltage is buffered by the buffer 丨 〇— 丨 and the output is a shaping logic low-level voltage The shaping low-level voltage is a status signal used to refer to a defective chip. On the contrary, if the fuse F 1 0 is not cut off, then the supply voltage vcc generates a high-level voltage at N21. The high-level voltage is from the punch 10 Buffered by -1, the output is a shaping logic high-level voltage. The shaping south voltage is a status signal to indicate a non-defective chip. The status signal PMF is supplied to the input buffer n, the output buffer, and the internal circuit components of the chip. 13 And at least one control end of the section of the chip's internal DC voltage generating component 14. The chip malfunction control circuit can be made on a semiconductor base, and through a well-known 2CM manufacturing process for manufacturing semiconductor memory devices, it is beneficial to the production cost of the conductor .

If & shown in Fig. 3b, in another embodiment similar to Fig. 3a, one end of the fuse F 10 operates as if a fuse assembly is connected to the power supply π. The other end of the fuse F10 is connected to a power source of a p-channel Mos transistor (pMos' Q2i). The drain of transistor Q21 is connected to another power source of p-channel Mos transistor Q22. In addition, the drain of transistor Q22 is usually connected to the transistor Qn, the gate of Q22. If so, the transistors q21 and Q22 work as a diode, similar to diode_ shown in Fig. 3a. The resistor R1 is connected between the transistor dead end and the ground voltage VSS. In fact, the '-potential signal can be obtained from the transistor Q 2 2 and the electrode, that is, the node n 2 1. Thereafter, it will describe how the chip malfunctions the control circuit.

Page 12 502427 V. Description of the invention (8) The fuse component of fuse F 1 0 and the signal generating component of related diode D 丨 'and resistor R 1 can control the operation of those components to be activated or deactivated, if the input buffer Device 11, output buffer 2 and chip internal circuit components 3 and chip DG voltage generating component 14. The fuse is cut according to the previous test of a chip defect. The identification signal is generated on the chip and has a first state if the chip is cut, and a second state if the fuse is not cut. What matters is the first state. That is why the identification signal is equivalent to the generated signal. If the fuse is cut, the operation of the internal circuit is prohibited if the fuse is cut.

Initially, FIG. 4 illustrates an embodiment of the input buffer 11 of FIG. In the figure, an external input signal is usually input to the transistors Q32 and Q33 through a semiconductor device input pin U-1, which becomes a pulse wave inverter for performing two signal phase inversion. However, the phase inversion signal is output through a buffer inverter Q37 to an output inverter Q38. At this time, if the external input signal is a chip selection signal for selecting a chip, the input pin ^ 4 becomes a chip selection / CS pin. The signal Pint is generated by the inverter Q38. When it is added to the control signal generation circuit, its control selects a chip. The pulse wave inverter can additionally include transistors Q31, Q34 and an inverter Q3 5 N-channel transistor Q36 to work to discharge an output terminal's electrical phase to its ground level. 'If the control signal or status signal The pMF is generated from the chip malfunction control circuit 10 (shown in Fig. 3a or 31). It is applied as a control signal to the general round-in f punch 1 1. With this structure, the defective chip input buffer is transferred to its dissatisfaction. In other words, if the chip decides that the defect and status signal pMF is supplied to its low level, the transistors Q31 and Q34 maintain their 0FF state. Therefore, electricity

Page 13 502427 V. Description of the invention (9), the crystals Q32 and Q33 can never perform their reverse, if they lose their function as an input buffer. If this happens, the authentication signal is prohibited from operating, and the forced input signal P i n t reaches a certain value. On the contrary, if the chip is determined to be a non-defective and a state signal PMF is provided as its high level, the transistors Q31 and Q34 remain in their ON state. If so, the transistors Q32 and Q33 perform their inversion, and if this is done their function is an input buffer. Even if only a signal PMF is supplied to the control terminal of the input buffer 11 in the figure, it is better to combine the application of the signal PMF with a control signal to activate or deactivate the input buffer. If the status signal PMF and the control signal are combined, it is better that a logic gate generates an AND or NAND response as a combination logic. Therefore, the chip malfunctioning control circuit 1 Q generates a potential signal in the signal generating component. According to whether the fuse is cut or not cut to indicate one of its states, the input buffer 丨 is activated and released. Therefore, even if any defective turtle input buffer is introduced into the market, its malfunction state is changed to further cause malfunction to the entire wafer. The status signal PMF can be applied to the output buffer, which can be operated similar to the control principle of the input buffer, even if its structure is somewhat different, so the defective chip output buffer reaches its malfunction state. According to the example shown in Fig. 5, the output buffer 12 is configured with output driving transistors Q41, Q42, transistors Q43a, Q44a, Q45a, 仏, 以. Clock pulse inverter is used to output control signal A, transistors ㈣b, g44b (34 5b, Q4 7b are clock pulse inverters used to output control signal B, and discharge transistors _a, Q48b. One output pin Connected to the-common drain for the wheel-out drive transistor ⑷, Q42 is used to supply high or low. 5. Description of the invention (10) = 2 = 5 output: In normal operating procedures. If-status signal PMF is applied Η end * via- Fat /, out of the buffer ^ 1 2, if the structure of this crystal is defective :, 2 :: ^ reached its release operation. In other words, if the chip is identified as cufT, the flood PMM system is supplied to a low order to maintain the transistor 0433, The Q46 is in its 0FF state. S Λ, the two clock pulse inverters are undefeated ^ the lamp is reversed 'if this causes the output buffer 12 to malfunction. In other words, the identification signal is prohibited to operate to force the output signals A, B to a fixed In the situation, if the chip is determined to be non-defective, the state signal rain is applied to its plane level to maintain the transistors 9433, Q46a, Q43b

0; status. Finally, the inverter can reverse the signals A and B. If this makes J the buffer work correctly. ^ Even if only one signal PMF is added to the control end of the output buffer 2 in the figure, it is better to use the signal PMF application by combining a control signal to activate or deactivate the input buffer. If the status signal pMF and the control signal are combined, its better case is that a logic gate generates an AND * NAND response for combinational logic. Therefore, the signal of the chip misoperation control circuit 丨 0 is generated ... The device control activates or deactivates the input buffer 12. Therefore, any defective wafer turns into a buffer, even if it may be introduced into the market, and its malfunctioning state is changed to produce malfunctioning to the entire wafer step by step. Referring to FIG. 6, a chip internal circuit assembly 3 uses a clock signal P1. The present invention teaches that the AND gate clock pulse signal pi is an identification signal. ^ Can be obtained from NAND gate Q51 and inverter Q52 via an AND gate. The signal can then be delayed through the quadrature inverters Q53-Q56 to the output signal P2. Similarly, if the status signal PMF is applied to the wafer internal line of the defective wafer

502427 V. Description of the invention (11) The circuit module 1 3 can also control the chip circuit assembly i 3 to change the wafer to a malfunction state. At this time, only when the first clock pulse signal ρ is correctly applied, the 'clock pulse signal P2 can be correctly generated for controlling the internal operation of the chip. If: The state signal PMF is applied as a control signal to operate the internal circuit components of the chip, the defect, and the internal circuit component 13 of the chip reaches its release operation. In other words, if the chip decides that the defect and status signal PMF is applied at a low level, the output of the NAND gate Q51 usually remains at its high state, regardless of the logic level of the first clock pulse signal P1. Therefore, the output of the inverter Q56 is connected to the terminal 3 of the internal circuit component of the crystal to keep it at a low level. In order that the internal circuit 13 of the chip cannot generate an output in response to the logic of the first clock pulse signal ρ. Coincidentally, if the chip is determined to be non-defective and the state pMF is applied to its high level, the NAND gate Q51 outputs a logic level before its first clock pulse signal P1 has been inverted. In this case, 1 ^ 〇 gate 051 implements its function as an inverter. The internal circuit component 13 of the chip executes its function by allowing the first clock pulse signal P1 to be correctly transmitted and processed therein. The f-state signal PMF can be added to the chip's "voltage generating component 丨 4, which can be operated in the same way. The control principle of the chip's internal circuit component 1 3, even if it can be structurally different. In this case, defects Inside the chip, this package pressure generating component 14 is converted to its malfunction state. There are many kinds of 4DC private pressure generating components 14 in the chip. For example, if the internal voltage generator is used to generate internal ', and the private MIVCC' negative voltage generator is used to Generates negative voltage VBb, half-wave 2, and the voltage generator is used to generate half-wave supply voltage VBL (l / 2VCC) and similar shapes. However, if shown in FIG. 7, only the internal supply voltage generator 14 is used to generate Internal supply voltage ^ ⑶, and its control program will be described

502427 Fifth, the description of the invention (12) is described as an embodiment. > If shown in Fig. 7, the general internal donors Q61, Q62, Q63, Q64fA, ^ r: The pressure generator 14 series has a transistor for activating or deactivating the current mirror circuit. The pole is connected to the output node N61, so that Q67 drives the current mirror line with its own. " And the internal supply voltage terminal UCC is used if the status signal PMF is applied as a protection part supply voltage generator 14 ', internal 佴: voltage :: =, chip internal removal status. In other words, “if the chip decides that the electricity is generated, ^ 1 4 reaches its solution, m ^ .., 疋 is a defect,” the state signal PMF is used as a low-level library, and the transistor Q65 reaches the state of 0N. Therefore, the festival, the discussion of the protection of the Japanese body reached its -t ^ JL0FF ^ ^ w son in the shape of the evil spirit, this keeps the transistor Q67 straight / OFF. In this way, the internal supply voltage generator "implements the operation of generating the internal supply voltage in the manner of a current mirror, and therefore never generates the internal supply voltage 卩" related to the reference voltage Vref. Finally, the two supply voltage generators 14 reach their malfunction state. Conversely, if the wafer system is determined to be non-defective, and the status signal PMF is applied at its high level, = the crystal Q65 reaches its 0N state to form a current path for current mirror operation. In this case, transistor Q66 is in its 0FF state. Therefore, the internal supply voltage generator 14 'performs its function correctly by generating the internal supply voltage phase with respect to the reference voltage Vref. Even if only one signal PMF is added to the internal supply voltage generator 4 in the figure, it will have a better shape of the moon PMF plus a control signal to activate or deactivate the operation of the internal supply voltage generator 14. If the status signal PMF and the control signal are combined, it may be better that a logic gate generates

Page 17 502427 $ itch month household s repair $ Amendment Case No. 89111722 Year J Month V. Invention Description. (13) ‘AND or NAND response is used as a combination of logic. Therefore, the signal malfunctioning component of the chip control circuit 10 controls the activation or deactivation of the internal supply voltage generator 14 '. Therefore, even if a defective wafer is supplied with a voltage generator 1 4 ′, even if it may be introduced into the market, changing its malfunction state further induces malfunction to the entire wafer. When the present invention has been described according to the preferred embodiments, those skilled in the art will recognize that the present invention can learn modifications made in accordance with the spirit and purpose of the additional items of the scope of patent application. For example, the internal structure of the fuse module and the signal generating module can be modified. The number of transistors that can work like a diode can be increased and decreased. For example, if a defective wafer is used, the cutting action will not be achieved in the fuse. In addition to using the internal working circuits of the chip to generate a status signal, a written signal indicates that the defective chip can display the device as if it were a microprocessor or a memory controller screen for its control function or to recognize its status signal. As mentioned above, the internal control circuit of the wafer of the present invention has an advantage in that defective wafers that cannot be repaired will be permanently prohibited from performing their normal operations in the subsequent manufacturing process, or even after the final product of the defective wafer is introduced into the market. This reduces wafer manufacturers' strict management of defective wafers, to avoid endangering their production costs or business image, and to contribute to the wafer stage wafer business. Explanation of Symbols of Schematic Components 10 Chip Malfunction 1 0- 1 Buffer 11 Input Buffer 1 1 Input Pin 12 Output Buffer

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Claims (1)

502427 _Case No. 89111722 (L 'Month $ __ ,. VI. Patent Application Scope']] 1. A semiconductor wafer 'includes a fuse assembly, if a previous wafer test has detected a defect, cut it off Off, the fuse assembly has a first end connected to a first power end, and a second end; and a signal generating component connected between the second end of the fuse assembly and the second power end for generating an identification signal if The fuse component has been cut off and used to provide an identification signal to the internal function circuit of a chip, where the identification signal prohibits the operation of the internal function circuit if the fuse component is cut off. 2. If the semiconductor chip of the first scope of the patent application, where The internal function circuit is an input buffer. 3. For a semiconductor chip with a scope of patent application item 1, the internal function circuit is an output buffer. 4. For the semiconductor chip with a scope of patent application item 1, the internal function circuit It is a DC voltage generating component. 5. For the semiconductor chip of the first scope of the patent application, wherein the first power supply terminal is the supply terminal, and the second Source terminal and ground terminal. 6. If the semiconductor chip of the scope of the patent application is applied for, the device further includes a signal waveform shaping buffer for shaping the identification signal. 7. For the semiconductor chip of the scope of the patent application, the fuse assembly is a A laser beam-cutting fuse. 8. If the semiconductor chip of the scope of patent application item 1, the fuse is a fuse cut by a current. 9. If the semiconductor chip of the scope of patent application item 1, where the fuse O: \ 64 \ 64729.ptc Page 1 2001.10. 02. 021 502427 Case No. 89111722 Amendment VI. Patent application scope 'The component is not cut off, then the signal generating component includes a diode to form a current path And a resistor is connected to the diode and the second power terminal. 10. The semiconductor wafer as claimed in claim 9 wherein the diode includes a MOS transistor. 1 1 · A method of generating and applying an identification signal on a chip, including: Defective test and cut off, then produce a circuit to prohibit internal work. Further include plastic identification. Further include power supply to drive. Among them, the internal function circuit is forbidden to input the identification signal to a fixed value. Among them, the internal function circuit is forbidden to input the identification signal to a fixed value. Among them, the internal function circuit number is a clock pulse. • Among the internal function circuits, if the chip's fuse has generated an identification signal on a chip based on a chip defect; and the operation of applying an identification signal to a chip's internal function circuit. 1 2. Method for applying for item 11 in the scope of patent application: Other signals. 1 3. The method according to item 11 of the scope of patent application is sourced to the chip, and the identification signal is provided. 1 4. The method according to item 11 of the scope of patent application is an input buffer receiving an output signal, and The operation of the buffer uses a forced input signal. 5. The method according to item 11 of the scope of patent application is an output buffer to output an output signal, and the operation of a buffer uses a forced output signal. 16 The method of item 11 of the patent application uses a clock signal and the AND gate of the identification signal. 1 7. The method as described in item 11 of the scope of patent application O: \ 64 \ 64729.ptc Page 2 2001.10. 02. 022 502427 _ Case No. 89111722 Rev. C Year β Month J Amendment _ 6. The scope of patent application is a DC voltage generating component with a current mirror, and its identification The signal prohibits the operation of the signal current mirror. 1 8. A method for controlling a wafer malfunction of one of the semiconductor wafers, including: The determination of whether a fuse is cut off in the wafer manufacturing process is based on whether the wafer is defective according to the result of identification; and generating an identification signal for identifying whether the wafer is defective. According to whether the fuse is cut off or not; and provide an identification signal to the internal function circuit of the chip to control and maintain the defective chip in its malfunction state. O: \ 64 \ 64729.ptc Page 3 2001.10.02. 023