KR100399074B1 - Formation Method of FeRAM having BLT ferroelectric layer - Google Patents

Formation Method of FeRAM having BLT ferroelectric layer Download PDF

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KR100399074B1
KR100399074B1 KR10-2001-0023075A KR20010023075A KR100399074B1 KR 100399074 B1 KR100399074 B1 KR 100399074B1 KR 20010023075 A KR20010023075 A KR 20010023075A KR 100399074 B1 KR100399074 B1 KR 100399074B1
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ferroelectric
film
forming
memory device
capacitor
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KR20020083628A (en
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김남경
염승진
양우석
권순용
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주식회사 하이닉스반도체
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Priority to JP2001375497A priority patent/JP4296375B2/en
Priority to US10/133,505 priority patent/US6747302B2/en
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Abstract

본 발명은 강유전체 캐패시터의 전기적 특성을 향상시킬 수 있으며, 상대적으로 낮은 온도에서 결정화를 실시할 수 있는 비엘티 강유전체막을 구비하는 강유전체 메모리 소자 제조 방법에 관한 것으로, 캐패시터의 축전물질로서 소자 신뢰성이 우수한 (BixLay)Ti3O12박막을 형성하는데 그 특징이 있다. Bi와 La 조성을 조절하여 500 ℃ 내지 675 ℃ 온도범위에서 결정화를 위한 열처리 공정을 실시할 수 있으며 캐패시터의 우수한 전기적 특성을 확보할 수 있다. 또한, 본 발명은 (BixLay)Ti3O12의 Bi의 원자 조성비(atomic concentration) 'x'는 3.25 내지 3.35가 되도록 하고, La의 원자 조성비 'y'는 0.70 내지 0.90이 되도록 형성하는 방법을 제시한다.The present invention relates to a method of manufacturing a ferroelectric memory device having a non-EL ferroelectric film capable of improving electrical characteristics of a ferroelectric capacitor and performing crystallization at a relatively low temperature, and having excellent device reliability as a capacitor storage material of a capacitor ( Bi x La y ) Ti 3 O 12 It is characterized by forming a thin film. By controlling the Bi and La composition can be carried out a heat treatment process for crystallization in the temperature range of 500 ℃ to 675 ℃ and can secure excellent electrical properties of the capacitor. In addition, the present invention is formed so that the atomic concentration ratio 'x' of Bi of (Bi x La y ) Ti 3 O 12 is 3.25 to 3.35, and the atomic composition ratio 'y' of La is 0.70 to 0.90. Give a way.

Description

비엘티 강유전체막을 구비하는 강유전체 메모리 소자 제조 방법{Formation Method of FeRAM having BLT ferroelectric layer}A method of manufacturing a ferroelectric memory device having a non-EL ferroelectric layer {Formation Method of FeRAM having BLT ferroelectric layer}

본 발명은 강유전체 메모리 소자 제조 분야에 관한 것으로, 특히 비엘티 강유전체막을 구비하는 강유전체 메모리 소자 제조 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of manufacturing ferroelectric memory devices, and more particularly, to a method of manufacturing a ferroelectric memory device having a non-EL ferroelectric film.

FeRAM(ferroelectric random access memory)은 DRAM(dynamic random access memory)의 정보저장 기능, SRAM(static random access memory)의 빠른 정보처리 속도, 플래쉬 메모리(flash memory)의 정보 보존 기능을 결합한 비휘발성 반도체 메모리 소자로서 종래의 플래쉬 메모리나 EEPROM(electrically erasable programmable read only memory) 보다 동작 전압이 낮고 정보 처리 속도가 1000배 이상 빠른 미래형 반도체 메모리 소자이다. SiO2또는 SiON 등과 같은 유전막을 구비하는 DRAM의 캐패시터는 전압을 인가한 후 전압공급을 중단하면 다시 원점으로 돌아오게 된다. 강유전체는 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remnant polarization) 상태를 갖고 있어 DRAM의 캐패시터와 달리 FeRAM을 이루는 강유전체 캐패시터는 양의 전압을 인가한 후 전압공급을 중단할 경우에도 강유전체 고유의 잔류분극 특성으로 인하여 데이터를 잃어버리지 않고 보유하게 된다.Ferroelectric random access memory (FeRAM) is a nonvolatile semiconductor memory device that combines the information storage function of dynamic random access memory (DRAM), the fast information processing speed of static random access memory (SRAM), and the information retention function of flash memory. This is a future semiconductor memory device having a lower operating voltage and 1000 times faster information processing speed than conventional flash memory or electrically erasable programmable read only memory (EEPROM). The capacitor of a DRAM having a dielectric film such as SiO 2 or SiON is returned to the origin when the voltage supply is stopped after the voltage is applied. Ferroelectrics have dielectric constants of several hundreds to thousands at room temperature and have two stable remnant polarization states. Unlike DRAM capacitors, ferroelectric capacitors that form FeRAM, even when the voltage supply stops after applying a positive voltage, Due to the intrinsic residual polarization characteristics of the ferroelectric, the data is retained without loss.

FeRAM 소자는 캐패시터와 트랜지스터가 각각 워드라인과 플레이트 라인에 접속되는 점에서 DRAM 소자와 동일하나, 캐패시터가 강유전체 박막을 갖는다는 점과 플레이트 라인과 연결되는 캐패시터의 전극이 접지 전위 또는 전원전압의 1/2 등의 고정 전위에 연결되는 것이 아니라 셀 마다 전압인가가 가능한 개별 플레이트 라인으로 되어 있다는 점에서 DRAM 소자와 차이가 있다.The FeRAM element is the same as the DRAM element in that the capacitor and the transistor are connected to the word line and the plate line, respectively, but the capacitor has a ferroelectric thin film and the electrode of the capacitor connected to the plate line has one-tenth of the ground potential or the supply voltage. It differs from DRAM devices in that it is not connected to a fixed potential such as 2, but is a separate plate line to which voltage can be applied to each cell.

첨부된 도면 도 1a는 종래 1 개의 트랜지스터와 1개의 강유전체 캐패시터로 이루어지는 FeRAM 소자의 메모리 셀 구성을 보이는 회로도로서, 워드라인(WL)과 연결되는 게이트 전극, 그 각각이 비트 라인(BL) 및 캐패시터(C) 중 어느 하나와 연결되는 소오스 및 드레인으로 이루어지는 트랜지스터(Tr), 그 제1 전극이 플레이트 라인(PL)과 연결되고 강유전체막을 사이에 두고 상기 제1 전극과 중첩되는 제2 전극이 트랜지스터(Tr)와 연결되어 전하저장 전극으로서 역할하는 캐패시터(C)를 보이고 있다.1A is a circuit diagram illustrating a memory cell configuration of a FeRAM device including a conventional transistor and a ferroelectric capacitor, each of which includes a gate electrode connected to a word line WL, each of which includes a bit line BL and a capacitor. A transistor Tr comprising a source and a drain connected to any one of C), and a second electrode connected to the plate line PL and overlapping the first electrode with a ferroelectric layer interposed therebetween. Capacitor C serving as a charge storage electrode is shown.

도 1b는 종래 기술에 따른 FeRAM 소자 제조 공정 단면도로서, 소자분리막(11) 그리고 게이트 절연막(12), 게이트 전극(13) 및 소오스·드레인(14)으로 이루어지는 트랜지스터 형성이 완료된 반도체 기판(10)을 덮는 제1 층간절연막(15) 상에 접착막(16)을 형성하고, 접착막(16) 상에 하부전극(17), 강유전체막(18) 및 상부전극(19)으로 이루어지는 캐패시터를 형성한 다음, 전체 구조 상에 캐패시터를 덮는 제2 층간절연막(20)을 형성하고, 캐패시터의 상부전극(19)을 노출시키는 콘택홀과 반도체 기판(10)에 형성된 소오스·드레인(14)을 노출시키는 콘택홀을 형성한 후, Ti막 및 TiN막의 적층구조로 이루어지는 금속확산방지막(21)을 형성하고, 캐패시터와 트랜지스터의 연결배선(interconnection line, 22)을 형성한 상태를 보이고 있다.FIG. 1B is a cross-sectional view of a FeRAM device fabrication process according to the prior art, in which a semiconductor substrate 10 including a device isolation film 11 and a gate insulating film 12, a gate electrode 13, and a source drain 14 is completed. An adhesive film 16 is formed on the covering first interlayer insulating film 15, and a capacitor including a lower electrode 17, a ferroelectric film 18, and an upper electrode 19 is formed on the adhesive film 16. A second interlayer insulating film 20 covering the capacitor on the entire structure, the contact hole exposing the upper electrode 19 of the capacitor, and the contact hole exposing the source and drain 14 formed in the semiconductor substrate 10. After the formation, the metal diffusion prevention film 21 having the stacked structure of the Ti film and the TiN film was formed, and the interconnection line 22 of the capacitor and the transistor was formed.

강유전체의 이력특성을 보이는 도 2를 참조하여 FeRAM 소자의 동작을 설명한다. 다음의 설명에서 양의 전압은 비트 라인의 전위가 플레이트 라인의 전위보다 높은 경우로 정하고, 잔류분극 "a" 점, "c"점의 상태를 각각 데이터 "1", "0"으로 정의한다. 데이터 "1"을 쓸 때 트랜지스터를 켜고 비트라인의 전위에 대하여 플레이트 라인에 양의 전압을 인가하면 강유전체 캐패시터에 인가되는 전압은 음이 되고 이력특성 곡선에서 "d" 점을 통과하게 된다. 이후 인가된 전압을 "0 V"로 돌리면 분극치가 잔류분극 "a"점으로 되고 데이터 "1"이 저장된다. 한편, 데이터 "0"을 써넣을 때는 강유전체 캐패시터에 인가하는 전압을 양으로 하여 "b"점을 통과시킨 후 인가전압을 "0 V"로 돌리면 분극량은 잔류분극 "C"점으로 기억되어 데이터 "0"이 기록된다.The operation of the FeRAM device will be described with reference to FIG. 2 showing the hysteretic characteristics of the ferroelectric. In the following description, the positive voltage is defined as the case where the potential of the bit line is higher than that of the plate line, and the states of the residual polarization points "a" and "c" are defined as data "1" and "0", respectively. When writing the data "1", turning on the transistor and applying a positive voltage to the plate line with respect to the potential of the bit line, the voltage applied to the ferroelectric capacitor becomes negative and passes the "d" point in the hysteresis curve. Then, when the applied voltage is turned to "0 V", the polarization value becomes the residual polarization "a" point and data "1" is stored. On the other hand, when the data "0" is written, the voltage applied to the ferroelectric capacitor is positive and the point "b" is passed. Then, when the applied voltage is turned to "0 V", the polarization amount is stored as the residual polarization "C" point. "0" is recorded.

데이터 읽어내기는 강유전체 캐패시터에 전압을 인가한 순간에 비트라인 상으로 흘러나가는 전하량을 검출하는 것으로 이루어진다. 즉, 양의 전압을 캐패시터에 인가하면 데이터가 "0"인 때 전하량 ΔQ0가 흘러나간다. 비트 라인상으로 흘러나가는 전하량의 크기가 캐패시터에 기억된 정보에 의하여 차이난다.Reading data consists of detecting the amount of charge that flows out on the bit line at the moment the voltage is applied to the ferroelectric capacitor. That is, if a positive voltage is applied to the capacitor, the charge amount ΔQ 0 flows out when the data is "0". The amount of charge flowing out on the bit line varies depending on the information stored in the capacitor.

강유전체 캐패시터로부터 비트라인으로 흘러나가는 전하는 비트라인의 전위를 변동시킨다. 비트라인에는 그 자체가 갖고 있는 캐패시터인 기생 비트라인 캐패시턴스 "Cb"가 존재한다. 트랜지스터가 켜져서 읽어낼 메모리가 선택되면 "ΔQ1"과 "ΔQ0" 만큼의 전하가 출력된다. 이 전하를 비트라인 캐패시턴스(Cb)와 강유전체 캐패시터(C)의 캐패시턴스값 "Cs"의 합으로 나눈 값이 다음의 수학식1과 같이 비트선의 전위 "V1", "V0"가 된다.The charge flowing out of the ferroelectric capacitor to the bit line changes the potential of the bit line. There is a parasitic bit line capacitance " Cb " that is a capacitor itself. When the transistor is turned on and the memory to be read is selected, as much as "ΔQ 1 " and "ΔQ 0 " are output. The charge divided by the sum of the bit line capacitance Cb and the capacitance value "Cs" of the ferroelectric capacitor C becomes the potentials "V1" and "V0" of the bit line as shown in Equation 1 below.

V1 = ΔQ1V1 = ΔQ1

V0 = ΔQ0/ (Cb+Cs)V0 = ΔQ 0 / (Cb + Cs)

따라서 데이터 "1"과 "0"의 차이에 의하여 비트라인에 나타나는 전위가 다르다. 워드라인에 전압을 인가하여 트랜지스터가 켜지면 비트라인의 전위가 "V1" 또는 "V0"로 변한다. 비트라인의 전위가 "V1"인가 또는 "V0" 인가를 판정하기 위해서는 "V1"과 "V0" 사이 값의 기준전위(Vref)와 "V1" 또는 "V0" 전위 각각의 크기 관계를 비교하면 된다.FeRAM의 축전물질로는 Pb(Zr,Ti)O3(이하 PZT)와 Bi-레이어드 계열의 SrBi2Ta2O9(이하 SBT), SrBi2(Ta, Nb)O9(이하 SBTN) 박막이 주로 사용된다. 강유전체는 결정이기 때문에 그 박막 성장에는 하부의 재료가 중요하다. 즉, 강유전체 캐패시터에서는 전극 재료의 선택이 강유전체의 특성에 크게 영향을 미치기 때문에 전기저항이 충분히 낮아야 하고, 강유전체 재료와 격자상수 부정합이 작아야 하고, 내열성이 높아야하며, 반응성이 낮고, 하부층 및 강유전체막 각각과의 접착성이 양호하여야 한다.Therefore, the potential appearing on the bit line is different due to the difference between the data "1" and "0". When the transistor is turned on by applying a voltage to the word line, the potential of the bit line changes to "V1" or "V0". To determine whether the potential of the bit line is "V1" or "V0", the magnitude relationship between the reference potential Vref of the value between "V1" and "V0" and each of the potentials of "V1" or "V0" is compared. PRAM (Zr, Ti) O 3 (hereinafter PZT) and Bi-layered SrBi 2 Ta 2 O 9 (hereinafter SBT) and SrBi 2 (Ta, Nb) O 9 (hereinafter SBTN) thin films This is mainly used. Since the ferroelectric is a crystal, the underlying material is important for thin film growth. That is, in ferroelectric capacitors, the choice of electrode material greatly affects the characteristics of the ferroelectric, so the electrical resistance must be sufficiently low, the ferroelectric material and the lattice constant mismatch must be small, the heat resistance must be high, the reactivity is low, and the lower layer and the ferroelectric film, respectively Good adhesion with

전술한 바와 같이 비휘발성 메모리 소자의 캐패시터 축전물질로서 Pb-계열의 PZT 계열과 Bi-레이어드 특성을 갖는 SBT, SBTN 등이 주로 개발되고 있지만 Pb-계열은 소자의 수명과 관계되는 특성인 피로도(fatigue), 보유력(retention) 및 임프린트(imprint) 특성이 열악하여 적용이 어려우며, SBT 계열은 신뢰성면에서는 우수하나 결정화 열처리 온도가 800 ℃ 이상이 되어야 하기 때문에 소자 제조 공정 과정에서 캐패시터 보다 먼저 형성된 층의 심각한 산화를 일으키는 문제점이 있다.As described above, PBT-based PZT series and SBT and SBTN, which have Bi-layered characteristics, have been mainly developed as capacitor storage materials of nonvolatile memory devices. ), It is difficult to apply due to poor retention, imprint, and imprint characteristics.The SBT series has excellent reliability, but the crystallization heat treatment temperature should be 800 ℃ or higher, so that the layers formed earlier than the capacitor during the device manufacturing process There is a problem that causes oxidation.

특히, 캐패시터의 하부전극과 트랜지스터의 소오스·드레인을 연결하기 위한 플러그 구조를 이용하는 경우 강유전체 결정 형성을 위한 열처리 과정에서 플러그가 산화되기 때문에, 종래에는 전술한 도 1b의 구조와 같이 상부전극(19)과 트랜지스터의 소오스·드레인(14)을 연결하는 구조로 형성하여 소자의 면적이 증가하는 단점이 있다.In particular, when the plug structure is used to connect the lower electrode of the capacitor and the source / drain of the transistor, the plug is oxidized during the heat treatment process for forming the ferroelectric crystal. Thus, the upper electrode 19 is conventionally formed as shown in FIG. There is a disadvantage in that the area of the device is increased by forming a structure in which the source and drain 14 of the transistor are connected to each other.

상기와 같은 문제점을 해결하기 위한 본 발명은 강유전체 캐패시터의 전기적 특성을 향상시킬 수 있으며, 상대적으로 낮은 온도에서 결정화를 실시할 수 있는 비엘티 강유전체막을 구비하는 강유전체 메모리 소자 제조 방법을 제공하는데 목적이 있다.The present invention for solving the above problems is to provide a method of manufacturing a ferroelectric memory device having a non-EL ferroelectric film that can improve the electrical characteristics of the ferroelectric capacitor, and can be crystallized at a relatively low temperature. .

도 1a는 종래 1 개의 트랜지스터와 1개의 강유전체 캐패시터로 이루어지는 FeRAM 소자의 메모리 셀 구성을 보이는 회로도,1A is a circuit diagram showing a memory cell configuration of a conventional FeRAM element consisting of one transistor and one ferroelectric capacitor;

도 1b는 종래 기술에 따른 FeRAM 소자 제조 공정 단면도,Figure 1b is a cross-sectional view of the FeRAM device manufacturing process according to the prior art,

도 2는 강유전체의 이력특성을 보이는 그래프,2 is a graph showing the hysteresis characteristics of ferroelectrics;

도 3a 내지 도 3d는 본 발명의 제1 실시예에 따른 강유전체 메모리 소자 제조 공정 단면도,3A to 3D are cross-sectional views of a ferroelectric memory device manufacturing process according to the first embodiment of the present invention;

도 4는 본 발명에 따른 BLT 강유전체 캐패시터의 분극특성을 보이는 그래프,4 is a graph showing polarization characteristics of a BLT ferroelectric capacitor according to the present invention;

도 5a 내지 도 5d는 본 발명의 제2 실시예에 따른 강유전체 메모리 소자 제조 공정 단면도,5A through 5D are cross-sectional views illustrating a process of manufacturing a ferroelectric memory device according to a second embodiment of the present invention;

도 6a 내지 도 6e는 본 발명의 제3 실시예에 따른 강유전체 메모리 소자 제조 공정 단면도,6A through 6E are cross-sectional views illustrating a process of manufacturing a ferroelectric memory device according to a third embodiment of the present invention;

도 7은 도 6d의 'A' 부분 확대도,7 is an enlarged view of a portion 'A' of FIG. 6D;

도 8은 본 발명에 따른 BLT 강유전체 캐패시터를 구비하는 셀 어레이 크기에 따른 델타분극의 변화를 보이는 그래프.8 is a graph showing the change in delta polarization according to the size of the cell array having a BLT ferroelectric capacitor according to the present invention.

*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *

39: 플러그 40: 하부전극39: plug 40: lower electrode

41, 63: (BixLay)Ti3O12막 42: 상부전극41, 63: (Bi x La y ) Ti 3 O 12 Membrane 42: Upper electrode

52: 제1 하부전극 53: 제2 하부전극52: first lower electrode 53: second lower electrode

51: Ti 실리사이드층 및 TiN 확산방지막51: Ti silicide layer and TiN diffusion barrier

61: 전도성 산화물층 62: 금속막61: conductive oxide layer 62: metal film

64: 전도막64: conductive film

상기와 같은 목적을 달성하기 위한 본 발명은, 강유전체 메모리 소자 제조 방법에 있어서, 반도체 기판 상부에 하부전극을 이루는 제1 전도막을 형성하는 단계; 상기 제1 전도막 상에 상기 Bi의 원자 조성비 'x'가 3.25 내지 3.35이고, La의 원자 조성비 'y'는 0.70 내지 0.90인 (BixLay)Ti3O12강유전체막을 형성하는 단계; 400 ℃ 내지 800 ℃ 온도에서 핵생성을 위한 열처리를 실시하는 단계; 및 500 ℃ 내지 675 ℃ 온도범위에서 상기 (BixLay)Ti3O12강유전체막의 결정화를 위한 열처리를 실시하는 단계; 및 상기 (BixLay)Ti3O12강유전체막 상에 상부전극을 이루는 제2 전도막을 형성하는 단계를 포함하는 강유전체 메모리 소자 제조 방법을 제공한다.According to an aspect of the present invention, there is provided a method of manufacturing a ferroelectric memory device, the method including: forming a first conductive film forming a lower electrode on an upper surface of a semiconductor substrate; Forming a (Bi x La y ) Ti 3 O 12 ferroelectric film on which the atomic composition ratio 'x' of Bi is 3.25 to 3.35 and La's atomic composition ratio 'y' is 0.70 to 0.90 on the first conductive film; Performing a heat treatment for nucleation at a temperature of 400 ° C. to 800 ° C .; And performing a heat treatment for crystallization of the (Bi x La y ) Ti 3 O 12 ferroelectric film at a temperature ranging from 500 ° C. to 675 ° C .; And forming a second conductive film forming an upper electrode on the (Bi x La y ) Ti 3 O 12 ferroelectric film.

본 발명은 캐패시터의 축전물질로서 소자 신뢰성이 우수한 (BixLay)Ti3O12박막을 형성하는데 그 특징이 있다. Bi와 La 조성을 조절하여 500 ℃ 내지 675 ℃ 온도범위에서 결정화를 위한 열처리 공정을 실시할 수 있으며 캐패시터의 우수한 전기적 특성을 확보할 수 있다.The present invention is characterized in forming a (Bi x La y ) Ti 3 O 12 thin film having excellent device reliability as a capacitor material of a capacitor. By controlling the Bi and La composition can be carried out a heat treatment process for crystallization in the temperature range of 500 ℃ to 675 ℃ and can secure excellent electrical properties of the capacitor.

본 발명은 (BixLay)Ti3O12(이하, BLT막이라 함)의 Bi의 원자 조성비(atomic concentration) 'x'는 3.25 내지 3.35가 되도록 하고, La의 원자 조성비 'y'는 0.70 내지 0.90이 되도록 형성하는 방법을 제시한다.In the present invention, the atomic concentration ratio 'x' of Bi in (Bi x La y ) Ti 3 O 12 (hereinafter referred to as BLT film) is set to 3.25 to 3.35, and the atomic composition ratio 'y' of La is 0.70. To 0.90 is provided.

증착 방법으로는 스핀-온(spin-on), PVD(physical vapor deposition), CVD(chemical vapor deposition), ALD(atomic layer deposition), MOD(metal organic deposition) 또는 PECVD(plasma enhanced chemical vapor deposition) 방식을 이용하여 형성한다.Deposition methods include spin-on, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic deposition (MOD), or plasma enhanced chemical vapor deposition (PECVD). To form.

PECVD 방식을 이용할 경우 증착온도는 400 ℃ 내지 700 ℃ 온도가 되도록 하고, 스핀-온 방법으로 BLT막을 형성할 경우 액체상태의 BLT 물질을 코팅하고, 물질 내에 함유된 용제(solvent)를 제거하기 위해 100 ℃ 내지 200 ℃ 온도에서 1차 열처리(bake) 공정을 실시한 다음 유기물(organic matter)을 제거하기 위해 200 ℃ 내지 350 ℃ 온도에서 2차 열처리 공정을 실시한다.When using the PECVD method, the deposition temperature is 400 ° C. to 700 ° C., and when the BLT film is formed by the spin-on method, the liquid BLT material is coated and 100 to remove the solvent contained in the material. The first heat treatment process is performed at a temperature of 200 ° C. to 200 ° C., and then the second heat treatment process is performed at a temperature of 200 ° C. to 350 ° C. to remove organic matter.

BLT막의 증착 후에는 O2와 N2의 혼합가스, N2, NH3, O2또는 N2O 가스 분위기에서 50 ℃ /초 내지 300 ℃ /초의 승온 속도로 온도를 올려가면서 400 ℃ 내지 800 ℃ 온도에서 핵생성을 위한 급속열처리(rapid thermal anneal)를 실시하고, O2와 N2의 혼합가스, O2또는 N2O 가스 분위기에서 상압 및 500 ℃ 내지 675 ℃ 온도 조건으로 결정립 성장을 위한 로 열처리 공정을 실시한다.After the deposition of the BLT film, the temperature was increased from 50 ° C./sec to 300 ° C./sec in a mixed gas of O 2 and N 2 , N 2 , NH 3 , O 2 or N 2 O gas at 400 ° C. to 800 ° C. Rapid thermal anneal for nucleation at temperature, and furnace for grain growth at atmospheric pressure and temperature from 500 ℃ to 675 ℃ in mixed gas of O 2 and N 2 , O 2 or N 2 O gas atmosphere A heat treatment step is carried out.

이하, 도 3a 내지 도 3d를 참조하여 본 발명의 제1 실시예에 따른 강유전체 메모리 소자 제조 방법을 설명한다.Hereinafter, a method of manufacturing a ferroelectric memory device according to a first embodiment of the present invention will be described with reference to FIGS. 3A to 3D.

먼저 도 3a에 도시한 바와 같이 소자분리막(31) 그리고 게이트 절연막(32), 게이트 전극(33) 및 소오스·드레인(34)으로 이루어지는 트랜지스터 형성이 완료된 반도체 기판(30)을 덮는 제1 층간절연막(36)을 선택적으로 식각하여 소오스·드레인(34)을 노출시키는 제1 콘택홀을 형성하고, 상기 제1 콘택홀을 통하여 상기 소오스·드레인(34)과 접하는 비트라인(37)을 형성하고, 전체 구조 상에 제2 층간절연막(38)을 형성한 다음, 제2 층간절연막(38) 및 제1 층간절연막(36)을 선택적으로식각하여 상기 소오스·드레인(34)을 노출시키는 제2 콘택홀을 형성한 다음, 상기 제2 콘택홀 내에 플러그(39)를 형성한다. 도 3a에서 미설명 도면부호 '35'는 절연막 스페이서를 나타낸다.First, as shown in FIG. 3A, the first interlayer insulating film covering the semiconductor substrate 30 on which the transistor isolation, which is composed of the device isolation film 31 and the gate insulating film 32, the gate electrode 33, and the source and drain 34, is completed. 36 is selectively etched to form a first contact hole exposing the source and drain 34, and forming a bit line 37 in contact with the source and drain 34 through the first contact hole, After forming the second interlayer insulating film 38 on the structure, the second contact hole for selectively exposing the second interlayer insulating film 38 and the first interlayer insulating film 36 to expose the source and drain 34 is formed. After the formation, the plug 39 is formed in the second contact hole. In FIG. 3A, reference numeral 35 denotes an insulating film spacer.

다음으로 도 3b에 보이는 바와 같이, 플러그(39) 상에 Pt, Ir, IrOx, Ru, RuOx, LSCO(La, Sr, Co, O) 또는 YBCO(Y, Ba, Co, O)을 MOCVD(metal organic chemical vapor deposition), PVD, 스핀-온, PECVD 등 다양한 증착 방식을 이용하여 500 Å 내지 3000 Å 두께의 하부전극(40)을 형성한다. 상기 플러그(39)와 하부전극(40) 사이에 오믹 콘택(Ohmic contact)을 이루기 위하여 Ti 실리사이드층 및 TiN 장벽금속층을 형성할 수도 있다.Next, as shown in FIG. 3B, Pt, Ir, IrO x , Ru, RuO x , LSCO (La, Sr, Co, O) or YBCO (Y, Ba, Co, O) is MOCVD on the plug 39. The lower electrode 40 having a thickness of 500 mV to 3000 mV is formed using various deposition methods such as metal organic chemical vapor deposition (PVD), spin-on, and PECVD. A Ti silicide layer and a TiN barrier metal layer may be formed to form ohmic contact between the plug 39 and the lower electrode 40.

이어서 도 3c에 도시한 바와 같이, 전술한 방법에 따라 하부전극(40) 상에 (BixLay)Ti3O12막(이하, BLT막이라 함)막(41)을 형성하고, BLT막(41) 상에 상부전극(42)을 형성한다.Subsequently, as shown in FIG. 3C, a (Bi x La y ) Ti 3 O 12 film (hereinafter referred to as a BLT film) film 41 is formed on the lower electrode 40 according to the above-described method. The upper electrode 42 is formed on the 41.

다음으로 도 3d에 보이는 바와 같이, 강유전체 캐패시터 형성이 완료된 전체 구조 상에 제3 층간절연막(43)을 형성하고, 제3 층간절연막(43) 상에 제1 금속배선(44), 금속배선간 절연막(45) 및 제2 금속배선(46)을 형성한다.Next, as shown in FIG. 3D, a third interlayer insulating film 43 is formed on the entire structure where the ferroelectric capacitor is formed, and the first metal wiring 44 and the intermetallic insulating film are formed on the third interlayer insulating film 43. 45 and the second metal wiring 46 are formed.

이후, 후속 공정을 진행하여 FeRAM 소자 제조 공정을 완료한다.Thereafter, a subsequent process is performed to complete the FeRAM device manufacturing process.

도 4는 전술한 본 발명의 제1 실시예에 따라 형성된 강유전체 캐패시터의 분극 특성을 보이는 그래프로서, 도 4를 통하여 BLT막을 축전물질로 이용하는 강유전체 캐패시터의 분극 특성이 양호함을 보이고 있다.4 is a graph showing the polarization characteristics of the ferroelectric capacitor formed according to the first embodiment of the present invention described above, and shows that the polarization characteristics of the ferroelectric capacitor using the BLT film as a storage material are good through FIG. 4.

한편, Pt 등의 금속으로 하부전극(40)을 형성하고, 그 상부에 BLT막(41)을 형성하면 650 ℃ 정도 온도에서 실시하는 결정화 열처리 조건에서 분극 특성과 누설전류 특성이 우수하다. 그러나, 산소분위기에서 실시되는 결정화를 위한 열처리 과정에서 하부전극 아래의 플러그(39)는 산화되고, Ti 실리사이드 또는 장벽금속층 등을 플러그(39)와 하부전극(40) 사이에 형성할 경우에도 Ti 실리사이드 또는 장벽금속층 등이 산화되어 계면 박리가 심하게 발생한다. 반면, IrOx, RuOx등과 같은 전도성 산화물로 하부전극(40)을 형성하면 650 ℃ 이상의 온도에서도 산소의 확산을 우수하게 방지할 수 있으나, Pt 등의 금속으로 하부전극(40)을 형성할 때보다 분극특성이 감소할 수 있다.On the other hand, when the lower electrode 40 is formed of a metal such as Pt, and the BLT film 41 is formed thereon, the polarization characteristics and the leakage current characteristics are excellent under the crystallization heat treatment conditions performed at about 650 ° C. However, even when the plug 39 under the lower electrode is oxidized in the heat treatment process for crystallization performed in the oxygen atmosphere, even when a Ti silicide or a barrier metal layer is formed between the plug 39 and the lower electrode 40, the Ti silicide is used. Alternatively, the barrier metal layer and the like are oxidized to cause severe interface peeling. On the other hand, if the lower electrode 40 is formed of a conductive oxide such as IrO x , RuO x, etc., the diffusion of oxygen can be excellently prevented even at a temperature of 650 ° C. or higher, but the lower electrode 40 is formed of a metal such as Pt. Multipolarization characteristics can be reduced.

상기와 같은 문제점을 해결하기 위하여 본 발명의 제2 실시예에서는 RuOx, IrOx등과 같은 산화물 전도층 위에 Pt 등과 같은 금속 전극을 다양한 방법으로 증착하여 다중층 구조의 하부전극을 형성함으로써, BLT 강유전체막이 Pt막과 접하여 양호한 분극특성과 누설전류 특성을 가지며 산화물 전도층이 산소의 확산을 효과적으로 방지할 수 있는 강유전체 메모리 소자 및 그 제조 방법을 제공한다.In order to solve the above problems, in the second embodiment of the present invention, a BLT ferroelectric is formed by depositing a metal electrode such as Pt on an oxide conductive layer such as RuO x , IrO x, etc. by various methods to form a lower electrode of a multilayer structure. Provided are a ferroelectric memory device and a method of manufacturing the same, wherein the film is in contact with the Pt film, has good polarization characteristics and leakage current characteristics, and the oxide conductive layer can effectively prevent oxygen diffusion.

이하, 도 5a 내지 도 5d를 참조하여 본 발명의 제2 실시예를 보다 상세하게 설명한다.Hereinafter, a second embodiment of the present invention will be described in more detail with reference to FIGS. 5A to 5D.

먼저 도 5a에 도시한 바와 같이 소자분리막(31) 그리고 게이트 절연막(32), 게이트 전극(33) 및 소오스·드레인(34)으로 이루어지는 트랜지스터 형성이 완료된 반도체 기판(30)을 덮는 제1 층간절연막(36)을 선택적으로 식각하여 소오스·드레인(34)을 노출시키는 제1 콘택홀을 형성하고, 상기 제1 콘택홀을 통하여 상기 소오스·드레인(34)과 접하는 비트라인(37)을 형성하고, 전체 구조 상에 제2 층간절연막(38)을 형성한 다음, 제2 층간절연막(38) 및 제1 층간절연막(36)을 선택적으로 식각하여 상기 소오스·드레인(34)을 노출시키는 제2 콘택홀을 형성한 다음, 상기 제2 콘택홀 내에 플러그(39)를 형성하고, 플러그(39) 상의 콘택홀 내에 오믹 콘택 이루기 위한 Ti 실리사이드층 및 TiN 확산방지막(51)을 피복(step coverage) 특성이 우수한 CVD(chemical vapor deposition) 방법으로 증착하고, 이웃하는 플러그(39) 상의 Ti 실리사이드층 및 TiN 확산방지막(51)을 분리시키기 위해 CMP(chemical mechanical polishing)을 실시한다. 도 5a에서 미설명 도면부호 '35'는 절연막 스페이서를 나타낸다.First, as shown in FIG. 5A, a first interlayer insulating film covering the semiconductor substrate 30 on which the transistor isolation layer 31 including the device isolation film 31, the gate insulating film 32, the gate electrode 33, and the source and drain 34 is completed. 36 is selectively etched to form a first contact hole exposing the source and drain 34, and forming a bit line 37 in contact with the source and drain 34 through the first contact hole, After forming the second interlayer insulating film 38 on the structure, the second contact hole for selectively etching the second interlayer insulating film 38 and the first interlayer insulating film 36 to expose the source and drain 34 is formed. After the formation, the plug 39 is formed in the second contact hole, and the Ti silicide layer and the TiN diffusion barrier layer 51 for ohmic contact are formed in the contact hole on the plug 39. by chemical vapor deposition And, subjected to CMP (chemical mechanical polishing) to remove the Ti silicide layer and a TiN diffusion prevention layer 51 on the neighboring plug 39. In FIG. 5A, reference numeral 35 denotes an insulating film spacer.

다음으로 도 5b에 보이는 바와 같이, 플러그(39) 상에 IrOx또는 RuOx등과 같은 전도성 산화물층을 50 Å 내지 2950 Å 두께로 증착하여 제1 하부전극(52)을 형성하고, 제1 하부전극 상에 Pt, Ru, Ir 또는 W 또는 WN 등의 금속막으로 50 Å 내지 2950 Å 두께의 제2 하부전극(53)을 형성한다. 상기 제1 하부전극(52)과 제2 하부전극(53) 각각은 CVD(chemical vapor deposition), PVD, 스핀-온, ALD(atomic layer deposition) 등 다양한 증착 방식을 이용하여 형성하며, 총 두께는 100 Å 내지 3000 Å이 되도록 한다.Next, as shown in FIG. 5B, a conductive oxide layer such as IrO x or RuO x is deposited on the plug 39 to a thickness of 50 to 2950 μs to form a first lower electrode 52, and the first lower electrode. A second lower electrode 53 having a thickness of 50 mV to 2950 mV is formed on the metal film such as Pt, Ru, Ir or W or WN. Each of the first lower electrode 52 and the second lower electrode 53 is formed using various deposition methods such as chemical vapor deposition (CVD), PVD, spin-on, and atomic layer deposition (ALD), and the total thickness is 100 kV to 3000 kV.

이어서 도 5c에 도시한 바와 같이, 전술한 방법에 따라 제2 하부전극(53) 상에 BLT막(41)을 형성하고, BLT막(41) 상에 상부전극(42)을 형성한다.5C, the BLT film 41 is formed on the second lower electrode 53 and the upper electrode 42 is formed on the BLT film 41 according to the above-described method.

또한, BLT 박막의 결정면이 c-축 배향 즉, 기판과 나란 방향 특성을 가질 경우 분극값이 약 4μC/㎠이고, BLT 박막의 결정면이 a-b축 배향 즉, 기판이 이루는 각이 0 °보다 크고 90 °보다 작을 경우의 분극값은 약 50μC/㎠으로서 배향 특성에 따라 분극값이 10 배 이상 차이난다. 그러나, 금속층 상에 형성된 BLT 박막은 로 열처리를 통해 결정화를 이루게 되면 박막의 배향성은 대부분 c-축으로 이루어지고 국부적으로 다른 축의 배향 성질을 가지기 때문에 분극값이 낮아지게 된다. 이러한 문제점을 해결하기 위하여 본 발명의 제3 실시예에서는 하부전극, BLT 강유전체막, 상부전극을 형성하고, 캐패시터 패턴 형성을 위한 식각을 실시하여 BPT 강유전체막 측면을 노출시키고 열처리 공정을 실시하여 강유전체막 측면이 분극값이 상대적으로 높은 a-b축 배향성 즉, BLT 박막의 결정면이 a-b축 배향 즉, 기판이 이루는 각이 0 °보다 크고 90 ° 보다 작도록 하는 방법을 제시한다.In addition, when the crystal plane of the BLT thin film has a c-axis orientation, that is, a direction characteristic parallel to the substrate, the polarization value is about 4 μC / cm 2, and the crystal plane of the BLT thin film has an ab axis orientation, that is, an angle formed by the substrate is greater than 0 ° and 90 °. When it is smaller than °, the polarization value is about 50 µC / cm 2, and the polarization value differs by 10 times or more depending on the orientation characteristic. However, when the BLT thin film formed on the metal layer is crystallized through the furnace heat treatment, the polarization value is lowered because the orientation of the thin film is mostly made of the c-axis and has the alignment property of the other axis locally. In order to solve this problem, in the third embodiment of the present invention, the lower electrode, the BLT ferroelectric film, and the upper electrode are formed, the etching is performed to form the capacitor pattern, and the side of the BPT ferroelectric film is exposed to perform a heat treatment process. The present invention proposes a method in which the side has an ab axis orientation having a relatively high polarization value, that is, the crystal plane of the BLT thin film has an ab axis orientation, that is, an angle between the substrate is greater than 0 ° and less than 90 °.

이하, 도 6a 내지 도 6e 및 도 7을 참조하여 본 발명의 제3 실시예를 보다 상세하게 설명한다.Hereinafter, a third embodiment of the present invention will be described in more detail with reference to FIGS. 6A to 6E and 7.

먼저 도 6a에 도시한 바와 같이 소자분리막(31) 그리고 게이트 절연막(32), 게이트 전극(33) 및 소오스·드레인(34)으로 이루어지는 트랜지스터 형성이 완료된 반도체 기판(30)을 덮는 제1 층간절연막(36)을 선택적으로 식각하여 소오스·드레인(34)을 노출시키는 제1 콘택홀을 형성하고, 상기 제1 콘택홀을 통하여 상기 소오스·드레인(34)과 접하는 비트라인(37)을 형성하고, 전체 구조 상에 제2 층간절연막(38)을 형성한 다음, 제2 층간절연막(38) 및 제1 층간절연막(36)을 선택적으로 식각하여 상기 소오스·드레인(34)을 노출시키는 제2 콘택홀을 형성한 다음, 상기 제2 콘택홀 내에 플러그(39)를 형성하고, 플러그(39) 상의 콘택홀 내에 오믹 콘택이루기 위한 Ti 실리사이드층 및 TiN 확산방지막(51)을 피복 특성이 우수한 CVD 방법으로 증착하고, 이웃하는 플러그(39) 상의 Ti 실리사이드층 및 TiN 확산방지막(51)을 분리시키기 위해 CMP(chemical mechanical polishing)를 실시한다. 도 6a에서 미설명 도면부호 '35'는 절연막 스페이서를 나타낸다.First, as shown in FIG. 6A, a first interlayer insulating film covering the semiconductor substrate 30 on which the transistor isolation formed of the device isolation film 31, the gate insulating film 32, the gate electrode 33, and the source and drain 34 is completed. 36 is selectively etched to form a first contact hole exposing the source and drain 34, and forming a bit line 37 in contact with the source and drain 34 through the first contact hole, After forming the second interlayer insulating film 38 on the structure, the second contact hole for selectively etching the second interlayer insulating film 38 and the first interlayer insulating film 36 to expose the source and drain 34 is formed. After the formation, a plug 39 is formed in the second contact hole, and a Ti silicide layer and a TiN diffusion barrier layer 51 for ohmic contact are deposited in the contact hole on the plug 39 by a CVD method having excellent coating properties. Ti on neighboring plug 39 Chemical mechanical polishing (CMP) is performed to separate the silicide layer and the TiN diffusion barrier film 51. In FIG. 6A, reference numeral 35 denotes an insulating film spacer.

다음으로 도 6b에 보이는 바와 같이, 플러그(39) 상에 IrOx또는 RuOx등과 같은 전도성 산화물층(61)을 형성하고, 전도성 산화물층(61) 상에 Pt 등의 금속막(62)을 CVD 방법으로 증착한 다음, 전술한 방법에 따라 금속막(62) 상에 BLT막(63)을 형성한다. 본 발명의 실시예에서는 상기 하부전극을 이루는 전도막을 Pt/IrOx, Pt/RuOx등과 같은 이중층 구조로 형성하는 것을 예로서 설명하였지만, Pt, Ru, Ir, RuOx, IrOx, W 또는 WN 등을 이용하여 단일층 구조로 형성할 수도 있다. 한편, 하부전극을 이루는 전도막의 총 두께는 500 Å 내지 3000 Å이 되도록 한다.Next, as shown in FIG. 6B, a conductive oxide layer 61 such as IrO x or RuO x or the like is formed on the plug 39, and a metal film 62 such as Pt is deposited on the conductive oxide layer 61. After the deposition, the BLT film 63 is formed on the metal film 62 according to the method described above. In the embodiment of the present invention, the conductive film forming the lower electrode has been described as an example of forming a double layer structure such as Pt / IrO x , Pt / RuO x , but Pt, Ru, Ir, RuO x , IrO x , W or WN It can also be formed in a single layer structure using. On the other hand, the total thickness of the conductive film forming the lower electrode is to be 500 kPa to 3000 kPa.

이어서 도 6c에 도시한 바와 같이, BLT막(63) 상에 상부전극을 이루는 전도막(64)을 형성한다.Subsequently, as shown in FIG. 6C, a conductive film 64 forming an upper electrode is formed on the BLT film 63.

다음으로 도 6d에 보이는 바와 같이, 전도막(64), BLT막(63), 금속막(62) 및 전도성 산화물층(61)을 선택적으로 식각하여 캐패시터 패턴을 형성한다. 이러한 캐패시터 패턴 형성에 따라 BLT막(63)의 측면이 노출된다. 이어서, O2, N2O, H2O2, H2O, N2, Ar 또는 Ne 가스 분위기에서 50 ℃/초 내지 300 ℃/초의 속도로 승온시키면서 500 ℃ 내지 800 ℃ 온도에서 급속열처리를 실시하여 BLT막(63) 측면의 배향성을 a-b축 방향 즉, BLT막(63) 측면의 결정면과 상기 하부전극 및 상기 하부전극이 이루는 각은 0 °보다 크고 90 °보다 작도록 변화시킨다. 이후, 안정화(relaxation) 및 캐패시터 패턴 형성을 위한 식각시 플라즈마에 의해 발생된 손상(plasma damage)을 제거하기 위해서 500 ℃ 내지 800 ℃ 온도에서 로 열처리를 실시한다.Next, as shown in FIG. 6D, the conductive film 64, the BLT film 63, the metal film 62, and the conductive oxide layer 61 are selectively etched to form a capacitor pattern. As the capacitor pattern is formed, the side surface of the BLT film 63 is exposed. Subsequently, rapid heat treatment is performed at a temperature of 500 ° C. to 800 ° C. while raising the temperature at a rate of 50 ° C./second to 300 ° C./second in an O 2 , N 2 O, H 2 O 2 , H 2 O, N 2 , Ar, or Ne gas atmosphere. The orientation of the side surfaces of the BLT film 63 is changed so that the angle between the abaxial direction, that is, the crystal surface of the BLT film 63 side surface, the lower electrode and the lower electrode is greater than 0 ° and smaller than 90 °. Subsequently, a furnace heat treatment is performed at a temperature of 500 ° C. to 800 ° C. to remove plasma damage generated during etching for stabilization and formation of a capacitor pattern.

도 7은 도 6d의 'A' 부분 확대도로서, c축 배향이 주로 일어나는 BLT막(63) 중심부와 급속열처리에 의해 a-b축 배향된 BLT막(63) 측면부(B)를 보이고 있다. 다음으로 도 6e에 도시한 바와 같이, 강유전체 캐패시터 형성이 완료된 전체 구조 상에 제3 층간절연막(43)을 형성하고, 제3 층간절연막(43) 상에 제1 금속배선(44), 금속배선간 절연막(45) 및 제2 금속배선(46)을 형성한다.FIG. 7 is an enlarged view of a portion 'A' of FIG. 6D, and shows a central portion of the BLT film 63 in which the c-axis orientation mainly occurs, and a side portion B of the BLT film 63 oriented a-b by the rapid heat treatment. Next, as shown in FIG. 6E, the third interlayer insulating film 43 is formed on the entire structure where the ferroelectric capacitor is formed, and the first metal wiring 44 and the metal wiring between the third interlayer insulating film 43 are formed. The insulating film 45 and the second metal wiring 46 are formed.

이후, 후속 공정을 진행하여 FeRAM 소자 제조 공정을 완료한다.Thereafter, a subsequent process is performed to complete the FeRAM device manufacturing process.

도 8은 본 발명에 따른 BLT 강유전체 캐패시터를 구비하는 셀 어레이 크기에 따른 델타분극의 변화를 보이는 그래프이다. DRAM 소자와 마찬가지로 FeRAM 소자 역시 집적도가 향상될수록 캐패시터의 크기가 작아지고 그에 따른 도메인(domain) 및 결정립계(grain boundary) 손상, 가장자리 효과(edge effect)에 의해 분극값이 감소하게 된다. 그러나, 본 발명에 따라 캐패시터 패턴 형성 후 BLT 강유전체막 측면의 배향을 변화시켜 부분적으로 분극값을 증가시킴으로써, 셀 어레이의 크기 감소에 따라 작아지는 캐패시터의 분극값 감소를 방지할 수 있다.8 is a graph showing changes in delta polarization according to a cell array size having a BLT ferroelectric capacitor according to the present invention. Like DRAM devices, FeRAM devices have a smaller capacitor size as the degree of integration increases, thereby decreasing polarization values due to domain and grain boundary damage and edge effects. However, according to the present invention, the polarization value is partially increased by changing the orientation of the BLT ferroelectric film side after forming the capacitor pattern, thereby preventing the decrease in the polarization value of the capacitor, which decreases as the size of the cell array decreases.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명은 Bi와 La 조성을 조절하여 500 ℃ 내지 675 ℃ 온도범위에서 결정화를 위한 열처리 공정을 실시할 수 있어 캐패시터의 우수한 전기적 특성을 확보할 수 있다.The present invention made as described above can be carried out a heat treatment process for crystallization in the temperature range of 500 ℃ to 675 ℃ by controlling the Bi and La composition can ensure excellent electrical properties of the capacitor.

또한, RuOx, IrOx등과 같은 산화물 전도층 위에 Pt 등과 같은 금속 전극을 다양한 방법으로 증착하여 다중층 구조의 하부전극을 형성함으로써, BLT 강유전체막이 Pt막과 접하여 양호한 분극특성과 누설전류 특성을 가지며 산화물 전도층이 산소의 확산을 효과적으로 방지할 수 있다.In addition, by depositing a metal electrode such as Pt on an oxide conductive layer such as RuO x or IrO x in various ways to form a lower electrode having a multilayer structure, the BLT ferroelectric film has good polarization characteristics and leakage current characteristics in contact with the Pt film. The oxide conductive layer can effectively prevent the diffusion of oxygen.

그리고, 하부전극, BLT 강유전체막, 상부전극을 형성하고, 캐패시터 패턴 형성을 위한 식각을 실시하여 BPT 강유전체막 측면을 노출시키고 열처리 공정을 실시하여 강유전체막 측면이 분극값이 상대적으로 높은 a-b축 배향성을 갖도록 할 수 있다.In addition, the lower electrode, the BLT ferroelectric film, and the upper electrode are formed, the etching is performed to form a capacitor pattern, and the side of the BPT ferroelectric film is exposed, and a heat treatment process is performed, so that the side of the ferroelectric film has a relatively high polarization of the ab-axis orientation. You can have it.

Claims (9)

강유전체 메모리 소자 제조 방법에 있어서,In the ferroelectric memory device manufacturing method, 반도체 기판 상부에 하부전극을 이루는 제1 전도막을 형성하는 단계;Forming a first conductive film forming a lower electrode on the semiconductor substrate; 상기 제1 전도막 상에 상기 Bi의 원자 조성비 'x'가 3.25 내지 3.35이고, La의 원자 조성비 'y'는 0.70 내지 0.90인 (BixLay)Ti3O12강유전체막을 형성하는 단계;Forming a (Bi x La y ) Ti 3 O 12 ferroelectric film on which the atomic composition ratio 'x' of Bi is 3.25 to 3.35 and La's atomic composition ratio 'y' is 0.70 to 0.90 on the first conductive film; 400 ℃ 내지 800 ℃ 온도에서 핵생성을 위한 열처리를 실시하는 단계; 및Performing a heat treatment for nucleation at a temperature of 400 ° C. to 800 ° C .; And 500 ℃ 내지 675 ℃ 온도범위에서 상기 (BixLay)Ti3O12강유전체막의 결정화를 위한 열처리를 실시하는 단계; 및Performing a heat treatment for crystallization of the (Bi x La y ) Ti 3 O 12 ferroelectric film at a temperature ranging from 500 ° C. to 675 ° C .; And 상기 (BixLay)Ti3O12강유전체막 상에 상부전극을 이루는 제2 전도막을 형성하는 단계Forming a second conductive film forming an upper electrode on the (Bi x La y ) Ti 3 O 12 ferroelectric film 를 포함하는 강유전체 메모리 소자 제조 방법.Ferroelectric memory device manufacturing method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제2 전도막을 형성하는 단계 후,After forming the second conductive film, 열처리 공정을 실시하여 상기 (BixLay)Ti3O12강유전체막 측면의 결정면과 상기 하부전극 및 상기 하부전극이 이루는 각이 0 °보다 크고 90 °보다 작도록 하는 단계를 더 포함하는 것을 특징으로 하는 강유전체 메모리 소자 제조 방법.And performing an annealing process such that an angle formed between the crystal surface of the side surface of the (Bi x La y ) Ti 3 O 12 ferroelectric film and the lower electrode and the lower electrode is greater than 0 ° and less than 90 °. A ferroelectric memory device manufacturing method. 제 2 항에 있어서,The method of claim 2, 상기 제1 전도막을 형성하는 단계는,Forming the first conductive film, IrOx또는 RuOx으로 이루어는 산화물층을 형성하는 단계;Forming an oxide layer consisting of IrO x or RuO x ; 상기 산화물층 상에 Pt, Ru, Ir 또는 W 또는 WN으로 이루어지는 금속막을 형성하는 단계Forming a metal film made of Pt, Ru, Ir, or W or WN on the oxide layer 를 포함하는 것을 특징으로 하는 강유전체 메모리 소자 제조 방법.A ferroelectric memory device manufacturing method comprising a. 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 (BixLay)Ti3O12강유전체막을 형성하는 단계에서,In the forming of the (Bi x La y ) Ti 3 O 12 ferroelectric film, 상기 (BixLay)Ti3O12강유전체막을 스핀-온(spin-on), PVD(physical vapor deposition), CVD(chemical vapor deposition), ALD(atomic layer deposition), MOD(metal organic deposition) 또는 PECVD(plasma enhanced chemical vapor deposition) 방식으로 형성하는 것을 특징으로 하는 강유전체 메모리 소자 제조 방법.The (Bi x La y ) Ti 3 O 12 ferroelectric film is spin-on, spin-on, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic deposition (MOD) or A method of manufacturing a ferroelectric memory device, which is formed by plasma enhanced chemical vapor deposition (PECVD). 제 1 항에 있어서,The method of claim 1, 상기 (BixLay)Ti3O12강유전체막을 형성하는 단계에서,In the forming of the (Bi x La y ) Ti 3 O 12 ferroelectric film, 상기 (BixLay)Ti3O12강유전체막을 PECVD 방식으로 400 ℃ 내지 700 ℃ 온도에서 형성하는 것을 특징으로 하는 강유전체 메모리 소자 제조 방법.The (Bi x La y ) Ti 3 O 12 ferroelectric film is formed by a PECVD method at a temperature of 400 ℃ to 700 ℃ characterized in that the ferroelectric memory device manufacturing method. 제 5 항에 있어서,The method of claim 5, 상기 (BixLay)Ti3O12강유전체막을 형성하는 단계는,Forming the (Bi x La y ) Ti 3 O 12 ferroelectric film, 상기 기판 상에 액체상태의 (BixLay)Ti3O12물질을 스핀-온 코팅하는 단계;Spin-on coating a liquid (Bi x La y ) Ti 3 O 12 material on the substrate; 100 ℃ 내지 200 ℃ 온도에서 열처리하여 상기 (BixLay)Ti3O12물질 내에 함유된 용제(solvent)를 제거하는 단계; 및Heat-treating at a temperature of 100 ° C. to 200 ° C. to remove the solvent contained in the (Bi x La y ) Ti 3 O 12 material; And 200 ℃ 내지 350 ℃ 온도에서 열처리하여 상기 (BixLay)Ti3O12물질 내에 함유된 유기물(organic matter)을 제거하는 단계를 포함하는 것을 특징으로 하는 강유전체 메모리 소자 제조 방법.And removing the organic matter contained in the (Bi x La y ) Ti 3 O 12 material by heat treatment at a temperature of 200 ° C to 350 ° C. 제 1 항에 있어서,The method of claim 1, 상기 핵생성을 위한 열처리는,The heat treatment for nucleation, O2와 N2의 혼합가스, N2, NH3, O2또는 N2O 가스 분위기에서 50 ℃/초 내지 300 ℃/초 속도로 온도를 증가시키면서 실시하는 것을 특징으로 하는 강유전체 메모리 소자 제조 방법.Method for manufacturing a ferroelectric memory device, characterized in that the temperature is increased at a rate of 50 ℃ / sec to 300 ℃ / second in a mixed gas of O 2 and N 2 , N 2 , NH 3 , O 2 or N 2 O gas atmosphere . 제 1 항에 있어서,The method of claim 1, 상기 (BixLay)Ti3O12강유전체막의 결정화를 위한 열처리는,The heat treatment for crystallization of the (Bi x La y ) Ti 3 O 12 ferroelectric film, O2와 N2의 혼합가스, O2또는 N2O 가스 분위기에서 상압 조건에서 실시하는 것을 특징으로 하는 강유전체막 메모리 소자 제조 방법.A method of manufacturing a ferroelectric film memory device, which is carried out at atmospheric pressure in a mixed gas of O 2 and N 2 , O 2 or N 2 O gas.
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