WO2004075296A1 - Method for manufacturing ferroelectric capacitor - Google Patents

Method for manufacturing ferroelectric capacitor Download PDF

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Publication number
WO2004075296A1
WO2004075296A1 PCT/JP2003/001773 JP0301773W WO2004075296A1 WO 2004075296 A1 WO2004075296 A1 WO 2004075296A1 JP 0301773 W JP0301773 W JP 0301773W WO 2004075296 A1 WO2004075296 A1 WO 2004075296A1
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Prior art keywords
film
metal element
bismuth
ferroelectric
manufacturing
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PCT/JP2003/001773
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French (fr)
Japanese (ja)
Inventor
Mineharu Tsukada
Hideki Yamawaki
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Fujitsu Limited
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Priority to JP2004568466A priority Critical patent/JPWO2004075296A1/en
Priority to PCT/JP2003/001773 priority patent/WO2004075296A1/en
Publication of WO2004075296A1 publication Critical patent/WO2004075296A1/en

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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40Oxides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/65Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B53/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B53/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/55Capacitors with a dielectric comprising a perovskite structure material

Definitions

  • the present invention relates to a method of manufacturing a ferroelectric capacitor suitable for manufacturing a Bi layer thin film capacitor used for a ferroelectric nonvolatile memory (FRAM) or the like.
  • a ferroelectric nonvolatile memory is provided with a thin film capacitor.
  • a lower electrode film is formed by a sputtering method, and then a ferroelectric film is formed by a sol-gel method, a sputtering method, or a MOCVD method. Is formed.
  • a ferroelectric film a PZT-based ferroelectric film and a Bi-layered ferroelectric film are mainly used.
  • Patent Document 1
  • the present invention has been made in view of the difficult problem, and provides a method of manufacturing a ferroelectric capacitor in which a ferroelectric film and an electrode film can be continuously formed in the same chamber.
  • the purpose is to do.
  • a method for manufacturing a ferroelectric capacitor according to the present invention is directed to a method for manufacturing a ferroelectric capacitor including a Bi layered ferroelectric film.
  • a gas containing a first metal element is placed in a CVD chamber. To form a lower electrode film containing the first metal element.
  • a gas containing Bi and O is formed.
  • a first conductive compound film containing a metal element and Bi is formed.
  • the introduction of the first metal element into the CVD champer is stopped.
  • the ferroelectric material excluding Bi among the metal elements constituting the Bi layered ferroelectric film is further added.
  • a gas containing a metal element for a film is introduced to form the Bi layered ferroelectric film on the first conductive compound film.
  • introduction of Bi and the metal element for the ferroelectric film into the CVD chamber is stopped.
  • an upper electrode film is formed on the Bi layered ferroelectric film.
  • a lower electrode film is formed.
  • a gas containing Bi and a metal element for a ferroelectric dielectric film excluding Bi among metal elements constituting the Bi-layered ferroelectric film and O is introduced.
  • the Bi layered ferroelectric film is formed on the lower electrode film.
  • the introduction of the metal element for a ferroelectric film into the CVD chamber is stopped.
  • a gas containing a second metal element is introduced, and the gas containing the second metal element is introduced onto the Bi layered ferroelectric film.
  • Forming a second conductive compound film containing the second metal element and Bi is stopped.
  • a gas containing the second metal element is continuously introduced into the CVD champer to form an upper electrode film containing the second metal element on the second conductive compound film. .
  • the metal element in the electrode film such as Ru reacts with the Bi in the Bi-layered ferroelectric film to increase the leakage current.
  • an electrode film (lower electrode film and / or upper electrode film) and a ferroelectric film are formed continuously in the same CVD chamber, and a conductive compound is formed between these films. A material film is formed.
  • FIG. 1 is a timing chart showing a method for manufacturing a ferroelectric memory according to the first embodiment of the present invention.
  • FIGS. 2A to 2G are cross-sectional views illustrating a method of manufacturing the ferroelectric memory according to the first embodiment of the present invention in the order of steps.
  • FIG. 3 is a cross-sectional view showing a ferroelectric capacitor manufactured in the first embodiment of the present invention.
  • FIG. 4 is a timing chart showing a method for manufacturing a ferroelectric memory according to the second embodiment of the present invention.
  • FIG. 5 is a cross-sectional view illustrating a method for manufacturing a ferroelectric memory according to the second embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a ferroelectric capacitor manufactured in the second embodiment of the present invention. ⁇
  • FIG. 7 is a timing chart showing a method for manufacturing a ferroelectric memory according to the third embodiment of the present invention.
  • FIG. 8 is a cross-sectional view illustrating a method for manufacturing a ferroelectric memory according to the third embodiment of the present invention.
  • FIG. 9 is a cross-sectional view showing a ferroelectric capacitor manufactured in the third embodiment of the present invention.
  • FIG. 10 is a timing chart showing a modification of the third embodiment of the present invention.
  • FIG. 1 is a timing chart showing a method for manufacturing a ferroelectric memory according to the first embodiment of the present invention.
  • 2A to 2G are cross-sectional views showing the same manufacturing method in the order of steps, and
  • FIG. 3 is a cross-sectional view showing the ferroelectric capacitor manufactured in the first embodiment.
  • an element isolation region 12 is formed on the surface of a semiconductor substrate 11 such as a silicon substrate by, for example, STI (shallow trench isolation).
  • a well 13 is formed on the surface of the semiconductor substrate 11 in the element active region partitioned by the element isolation region 12.
  • a gate insulating film 17, a gate electrode 18, a silicide layer 19, a low-concentration diffusion layer 15, a sidewall 20, and a high-concentration diffusion layer 16 are formed on the surface of the well 13.
  • the S transistor 14 is formed.
  • Each MOS transistor 14 has two high-concentration diffusion layers 16 for source and drain, one of which is shared by the two MOS transistors 14.
  • a silicon oxynitride film 21 is formed on the entire surface so as to cover the MOS transistor 14, and a silicon oxide film 22 is further formed on the entire surface by, for example, an organic CVD method.
  • the silicon oxynitride layer 21 is formed to prevent the gate insulating film 17 and the like from forming hydrogen when the silicon oxide film 22 is formed.
  • a contact hole reaching between the high concentration diffusion layers 16 is formed in the silicon oxide film 22 and the silicon oxynitride film 21 to open a plug contact portion.
  • a W film is buried by, for example, the CVD method, and the CMP ( The W plug 24 is formed by carrying out and carrying out.
  • the entire surface R u film (lower electrode film) 2 5 the lower conductive compound film 2 5 a ⁇ Pi BLT ((B i, L a ) 4 T i 3 0 1 2)
  • the film 26 is formed continuously by the MOCVD method in the same champer.
  • these B25, 25a and 26 will be described.
  • these raw materials for example, those shown in Table 1 are used.
  • the solvent for example, n-hexane is used. It is desirable to use a MOC VD device that can vaporize these raw materials in the same vaporizer.
  • the temperature of the susceptor in the MOCVD chamber is set to 500 ° C., and then the semiconductor substrate 11 is mounted on the susceptor. Then, after the temperature of the semiconductor substrate 11 becomes constant, a Ru raw material is supplied into the MOCVD chamber together with a nitrogen gas as a carrier gas, as shown in FIG. By maintaining this state, the Ru film 25 is formed.
  • the nitrogen gas is reduced to 20% by volume, the supply of oxygen gas for 80% by volume as a reaction gas is started, and the supply of Bi raw material is started.
  • the supply of the Ru raw material is stopped.
  • the amount of Bi in the MOCVD chamber increases and the amount of Ru decreases.
  • the lower conductive compound month trillions (B i 2 Ru 2 0 7 one x film) 25 a is formed.
  • Ru 25, lower conductive compound film 25a, and BLT film 26 are formed.
  • the semiconductor substrate 11 is removed from the MOCVD chamber, and the PLT is deposited on the BLT film 26 as shown in FIG. 2B.
  • a t film (upper electrode film) 27 is formed by sputtering, and annealing is performed for 60 minutes in an oxygen atmosphere at 500 ° C., for example. By this annealing, the plasma damage of the BLT film 26 due to the sputter deposition of the Pt film 27 is recovered. Subsequently, as shown in FIG. 2C, the Pt film 27 and the BLT film are formed by using patterning and etching techniques.
  • an alumina protective film 28 covering the ferroelectric capacitor is formed on the entire surface.
  • the alumina protective film 28 is formed, for example, by the CVD method, and has a thickness of, for example, 5 to 20 nm, and 10 nm in the present embodiment.
  • an interlayer insulating film 29 is formed on the entire surface, it is planarized by CMP.
  • the interlayer insulation layer 29 for example, a silicon oxide film is formed using an HDP (High Density Plasma) CVD apparatus. Further, a TEOS oxide film may be formed as the interlayer insulating film 29.
  • the remaining film thickness after the CMP is, for example, 300 nm on the Pt film 27.
  • the high-concentration diffusion layer 1 shared by the two MOS transistors 14 is added to the interlayer insulating film 29 and the alumina protective film 28.
  • a glue film 30 is formed in this contact hole, for example, a 50-nm-thick TiN film, and then a W film is buried by, for example, a CVD method, and planarized by CMP (chemical mechanical polishing).
  • CMP chemical mechanical polishing
  • a W oxidation preventing film (not shown) is formed on the entire surface.
  • a SiON film can be used, and its thickness is, for example, about 10 ⁇ ⁇ .
  • a contact hole reaching the Pt film 27 serving as the upper electrode is formed in the W oxidation preventing film and the interlayer insulating film 29. I do.
  • an anneal is applied to recover the damage caused by the etching.
  • This Aniru for example 5 5 0 ° C in may be a furnace Aniru 0 2 atmosphere, the time is for example for 60 minutes. After this annealing, the W oxidation preventing film is removed by etch back.
  • a glue film, a wiring material film, and a glue film are sequentially deposited.
  • the lower glue film for example, a laminated film of a 70 nm thick TiN film and a 5 nm Ti film may be formed.
  • the upper glue film may be, for example, a laminated film of a 30 nm thick TiN film and a 6011111 thin film.
  • an anti-reflection film is formed on the upper glue film by coating, and a resist is further applied.
  • the resist film is processed so as to match the wiring pattern, and the antireflection film, the upper glue film, the wiring material film, and the lower glue film are etched using the processed resist film as a mask.
  • a SiON film can be used as the antireflection film, and its thickness is, for example, about 30 nm.
  • an interlayer insulating film is formed, a contact plug is formed, and wirings for the second and subsequent layers from the bottom are formed.
  • a cover film made of, for example, a TEOS oxide film and a SiN film is formed to complete a ferroelectric memory having a ferroelectric capacitor.
  • the order of starting and stopping the supply of the raw material is determined.
  • the lower conductive compound film 25a is formed before the BLT film 26 is formed, and the reaction between Ru and Bi is completed in the lower conductive compound film 25a. . Therefore, when the BLT film 26 is formed, the diffusion of Ru into the BLT film 26 is prevented by the lower conductive compound film 25a. Therefore, according to the present embodiment, even if the Ru film 25 is used as the lower electrode, the leak current does not increase as before.
  • the result of the inventors of the present invention verifying the manufacturing method according to the first embodiment will be described.
  • a SiO 2 film and a Ti N film were formed on a Si substrate (wafer), and a ferroelectric capacitor was formed thereon.
  • the conditions for forming the ferroelectric capacitor are the same as in the first embodiment.
  • the thickness of the Ru film 25 was about 10 Onm
  • the thickness of the BLT film 26 was about 100 nm.
  • the composition in the thickness direction of the stacked film including the BLT film 26 and the Ru film 25 was analyzed by SIMS. A region where Bi and Ru coexist is observed over a thickness of about 20 nm. Was. This region is the lower conductive compound film 25a. Also, no diffusion of 1 u into the BLT film 26 was observed.
  • a Pt film 27 as an upper electrode film was formed by a sputtering method using a metal through mask, and after annealing for 60 minutes in an oxygen atmosphere at 500 ° C., a leakage current of 5 V was obtained. was measured density, the current density was O over da one 1 X 1 0- 6 a / cm 2. Also, the 1.5 V switch charge amount Qsw indicating the polarization characteristic was about 30 ⁇ C / cm 2 . As a result, according to the first embodiment, it was confirmed that a ferroelectric capacitor having good characteristics could be obtained.
  • FIG. 4 is a timing chart showing a method for manufacturing a ferroelectric memory according to the second embodiment of the present invention.
  • FIG. 5 is a cross-sectional view illustrating a method of manufacturing a ferroelectric memory according to a second embodiment of the present invention, and FIG. 6 illustrates a ferroelectric capacitor manufactured according to the second embodiment. It is sectional drawing.
  • FIG. 5 corresponds to FIG. 2B showing a part of the steps of the first embodiment.
  • the steps up to the formation of the W plug 24 are performed in the same manner as in the first embodiment.
  • an Ir film (lower electrode film) 35 is formed on the entire surface by sputtering.
  • these films 26, 37a and 37 will be described.
  • these raw materials (precursors) and solvents for example, those shown in Table 1 and n-hexane are used as in the first embodiment.
  • the temperature of the susceptor of the MOC VD chamber is set to 500 ° C., and the semiconductor substrate 11 is placed on the susceptor. And half MOCVD After the temperature of the conductor substrate 11 becomes constant, as shown in FIG. 4, the oxygen gas 80 vol 0/0 as nitrogen gas 20 vol 0/0 and the reaction gas as a carrier gas, a B i starting material Supply into the chamber. Immediately after that, supply of Ti raw material and La raw material is started. By maintaining this state, the BLT film 26 is formed. Next, the supply of the Ti raw material and the La raw material was stopped, and after the Ti raw material and the La raw material were not completely introduced into the MOCVD chamber, the supply of the Ru raw material was started as shown in FIG.
  • the supply of the Bi raw material is stopped.
  • the amount of Ru in the MOCVD champer increases and the amount of Bi decreases.
  • the upper conductive tens raw compound film (B i 2 Ru 2 0 7 _ x film) 37 a is formed.
  • the RuO 2 film 37 is formed instead of the Ru film is that the supply of oxygen gas is maintained in the present embodiment, unlike the case of forming the Ru film 25 in the first embodiment. .
  • the BLT film 26, the upper conductive compound film 37a and the RuO 2 film 37 are formed.
  • the semiconductor substrate 11 is taken out of the MOCVD chamber, and the processes after the ferroelectric capacitor are processed as in the first embodiment.
  • the upper conductive compound film 37a is formed, and the reaction between Ru and Bi in the upper conductive compound film 37a is performed. Has been completed. Therefore, when forming the RuO 2 film 37, the diffusion of Ru into the BLT film 26 is prevented by the upper conductive compound film 37a. Therefore, according to the present embodiment, even if the RuO 2 film 37 is used as the upper electrode, the leak current does not increase as before.
  • the results of verification of the manufacturing method according to the second embodiment by the present inventor will be described.
  • a SiO 2 film and a Ti N film were formed, and a ferroelectric capacitor was formed thereon.
  • the conditions for forming the ferroelectric capacitor are the same as in the second embodiment.
  • the thickness of the BLT film 26 was about 100 nm
  • the thickness of the Ru 2 film 37 was about 100 nm.
  • composition of the film thickness direction of the laminated film including a Ru_ ⁇ 2 film 37 and BLT film 26 was analyzed by S IMS, R u O 2 film 37 and the B LT film 26 In between, a region where Bi and Ru coexist was observed over a thickness of about 20 nm. This region is the upper conductive compound film 37a. Further, diffusion of Ru into the BLT film 26 was not observed.
  • FIG. 1 is a timing chart showing a method for manufacturing a ferroelectric memory according to a third embodiment of the present invention.
  • FIG. 8 is a cross-sectional view illustrating a method of manufacturing a ferroelectric memory according to the third embodiment of the present invention, and
  • FIG. 9 illustrates a ferroelectric capacitor manufactured according to the third embodiment. It is sectional drawing.
  • FIG. 8 corresponds to FIG. 2B showing some steps of the first embodiment.
  • the steps up to the formation of the W plug 24 are performed in the same manner as in the first embodiment.
  • Electrode films) 37 are continuously formed by MOCVD in the same chamber.
  • a method for forming these films 25, 25a, 26, 37a and 37 will be described.
  • these raw materials (precursors) and solvents for example, those shown in Table 1 and n-hexane are used as in the first embodiment.
  • the temperature of the susceptor in the MOCVD chamber is set to 500 ° C., and then the semiconductor substrate 11 is mounted on the susceptor. Then, after the temperature of the semiconductor substrate 11 becomes constant, a Ru raw material is supplied into the MOCVD chamber together with a nitrogen gas as a carrier gas as shown in FIG. By maintaining this state, the Ru film 25 is formed.
  • the nitrogen gas is reduced to 20% by volume, the supply of oxygen gas of 80% by volume as a reaction gas is started, and the supply of Bi raw material is started.
  • the supply of the Ru raw material is stopped.
  • the amount of Bi in the MOCVD champer increases and the amount of Ru decreases.
  • the lower conductive compound film (B i 2 Ru 2 0 7 - x film) 25 a is formed.
  • the supply of the Ti raw material and the La raw material was stopped, and after the Ti raw material and the La raw material were not completely introduced into the MOCVD chamber, the supply of the Ru raw material was started as shown in FIG. Immediately thereafter, the supply of the Bi raw material is stopped. As a result, as shown in FIG. 7, the Ru amount in the MOCVD chamber increases and the Bi amount decreases. During this time, the upper conductive compound film (B i 2 Ru 2 0 7 x film) 37 a is formed. After the B i material could be introduced completely MOCVD chamber also, as shown in FIG. 7, by continuing the supply of the Ru material, length 10 2 film 37 is made form.
  • a 111 film 25, a lower conductive compound film 25a, a BLT film 26, an upper conductive compound film 37a and a RuO 2 film 37 are formed. Then, after the Ru raw material is not completely introduced into the MOCVD chamber, the semiconductor substrate 11 is taken out of the MOCVD chamber, and the processes after the ferroelectric capacitor are processed as in the first embodiment. Complete a ferroelectric memory having a ferroelectric capacitor.
  • the lower conductive compound film 25a is formed, and the reaction between Ru and Bi is completed in the lower conductive compound film 25a.
  • an upper conductive compound Moon 37a is formed, and the reaction with Ru and Bi in the upper conductive compound film 37a is performed. Has been completed. Therefore, when the BLT film 26 is formed, the diffusion of Ru from the Ru film 25 into the BLT film 26 is prevented by the lower conductive film 25 a, and the Ru 2 film 37 is formed. At the time of formation, diffusion of Ru from the 11 ⁇ 2 film 37 into the BLT film 26 is prevented by the upper conductive compound film 37a.
  • the Ru film 25 is used as the lower electrode and the RuOj 37 is used as the upper electrode, the leak current does not increase as in the related art.
  • a description will be given of the result of the inventors of the present application verifying the manufacturing method according to the third embodiment.
  • a SiO 2 film and a Ti N film were formed on a Si substrate (wafer), and a ferroelectric capacitor was formed thereon.
  • the conditions for forming the ferroelectric capacitor are the same as in the third embodiment.
  • the thickness of 13 ⁇ 4 11 film 25 is 100 1 1111 extent
  • the thickness of the BLT layer 26 is about 100 nm
  • the thickness of the Ru_ ⁇ 2 film 37 was set to about 1 00 nm.
  • composition of the film thickness direction of the laminated film including a scale 11_Rei 2 film 37, 81 ⁇ Chomaku 26 and R u film 25 was analyzed by S IMS, R u O 2 Between the film 37 and the BLT film 26 and between the BLT film 26 and the Ru film 25, regions where Bi and Ru coexist over a thickness of about 20 nm were observed. This region is the upper conductive compound film 37a and the lower conductive compound film 25a, respectively. In addition, diffusion of Ru into the BLT film 26 was not observed.
  • the supply of the Ru raw material is stopped.
  • the supply of the Ru raw material may be stopped after the supply amount of Ru reaches a steady state.
  • the supply of the Bi raw material was stopped, but as shown in FIG. 10, the supply amount of the Ru raw material reached a steady state. After that, the supply of the Bi raw material may be stopped.
  • 1 11 use Ite 1 110 2 film generations Wari membrane may be used Ru film instead of Ru_ ⁇ 2 film.
  • the material of the electrode film is not particularly limited.
  • the ferroelectric film of B i layered system is not limited to the B LT film, for example, instead of BLT film, SBT (S r B i 2 T a 2 0 7) film, SBN (S r B i 2 Nb 2 O g) film or a BIT (B i 4 T i 3 0 12) may be formed film.
  • SBT S r B i 2 T a 2 0 7
  • SBN S r B i 2 Nb 2 O g
  • a BIT B i 4 T i 3 0 12
  • an Sr raw material and a Ta raw material may be supplied, or three raw materials and three raw materials may be used.
  • the power to supply the raw materials or only the Ti raw materials may be supplied.
  • a MOCVD apparatus suitable for implementing the present invention will be described.
  • a vaporizer is provided for each raw material, and raw gas is supplied from these vaporizers to a mixer via each pipe, and after each raw material gas is mixed in the mixer, Some are supplied from the shower head into the chamber.
  • a MOCVD apparatus in which a plurality of raw materials are degassed in one vaporizer to generate a raw material gas, and these powers are mixed and supplied from a shower head into a chamber. It has been developed.
  • the conventional MOC VD device In the conventional MOC VD device, a long pipe is required from when the gas is vaporized in the vaporizer to when it is supplied into the chamber. Before feed gas is supplied into the chamber, And the like may generate particles inside. In contrast, the recently developed MOC VD device suppresses the generation of such particles.
  • the present invention there are many steps of simultaneously supplying a plurality of source gases into the chamber, and it is necessary to appropriately switch on / off of the supply of these gases, so that a recently developed MOC VD apparatus is used.
  • the effect of suppressing generation of particles is remarkable.
  • the recently developed MOC VD device requires only one vaporizer, so when using many types of raw gas, the cost can be reduced by reducing the number of vaporizers.
  • a Bi layered system such as a Bi raw material (organic compound of Bi), a La raw material (organic compound of La), and a Ti raw material (organic compound of Ti) is used. It is desirable to use a ferroelectric film raw material supply system connected to a Ru raw material (organic compound of a metal element) supply system.
  • the temperature of the shower head and the temperature of the substrate are changed from the start of gas supply into the MOC VD chamber to the end of film formation in the MOC VD chamber. Is preferably kept constant. By keeping these constant, it becomes possible to form each film more stably. Industrial applicability
  • the formation of the electrode film and the formation of the ferroelectric film can be performed continuously in one chamber. For this reason, the manufacturing time can be reduced, and the cost of the manufacturing equipment can be reduced. Further, since the number of times of wafer transfer is reduced, contamination that may occur during transfer is suppressed, and high reliability can be obtained. Further, by forming the conductive compound film, a leak current in the ferroelectric film can be significantly reduced.
  • Ru raw material Ru (EtCp), (Ru (C 5 H 4 C 2 H 5 ) 2 Bis-ethyl-cyclo.
  • Ti raw material Ti (0iPr) 4 Ti [0CH (CH 3 ) 2 ] 4 : tetra-isofuran oxy-titanium

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Abstract

A nitrogen gas is supplied along with a Ru material into an MOCVD chamber. By maintaining this state, a Ru film is formed. While reducing the nitrogen gas to 20 volume%, supply of 80 volume% of oxygen gas as a reaction gas is started, supply of a Bi material is also started, and immediately after that the supply of the Ru material is stopped. As a result, the quantity of Bi in the MOCVD chamber increases, and that of Ru material decreases. During this, a lower conductive compound film is formed. After the introduction of the Ru material into the MOCVD chamber is completely stopped, supply of a Ti material and a La material is started while maintaining the supply of the Bi material. By maintaining this state, a BLT film is formed. The lower conductive compound film suppresses diffusion of Ru into the BLT film, thereby preventing an increase of the leak current.

Description

強誘電体キャパシタの製造方法 技術分野  Manufacturing method of ferroelectric capacitor
本発明は、 強誘電体不揮発性メモリ (FRAM) 等に用いる B i層状系薄膜キ ャパシタの製造に好適な強誘電体キャパシタの製造方法に関する。 背景技術  The present invention relates to a method of manufacturing a ferroelectric capacitor suitable for manufacturing a Bi layer thin film capacitor used for a ferroelectric nonvolatile memory (FRAM) or the like. Background art
強誘電体不揮発性メモリ (FRAM) には、 薄膜キャパシタが設けられている 。 そして、 従来、 この薄膜キャパシタを製造するに当たっては、 先ず、 スパッタ 法により下部電極膜を形成し、 次に、 ゾルーゲル法、 スパッタ法又は MOCVD 法により強誘電体膜を形成し、 その後、 上部電極膜を形成している。 強誘電体膜 としては、 P Z T系の強誘電体膜及ぴ B i層状系の強誘電体膜が主に用いられて いる。  A ferroelectric nonvolatile memory (FRAM) is provided with a thin film capacitor. Conventionally, in manufacturing this thin film capacitor, first, a lower electrode film is formed by a sputtering method, and then a ferroelectric film is formed by a sol-gel method, a sputtering method, or a MOCVD method. Is formed. As the ferroelectric film, a PZT-based ferroelectric film and a Bi-layered ferroelectric film are mainly used.
また、 P Z T系薄膜キャパシタ及び B i層状系薄膜キャパシタの電極材料とし ては、 P t、 I r、 I r〇2等が実際に用いられ、 .これらについて数多く研究が 行われている。 1990年代の中頃の PZT系薄膜キャパシタの研究段階におい ては、 Ru系 (Ru〇2を含む) の電極材料も検討されていた。 し力 し、 Ru系 の電極材料を用いると、 キャパシタのリークを制御することが難しく、 実用化に は至らなかつた。 これは、 強誘電体中の P bと電極膜中の R uとが反応し、 P b 2 R u 2 O 67のようなパイ口クロァ構造の導電性ィ匕合物が生成されるためである 。 伹し、 Ruには、 その地金価格が P t及ぴ I rのそれよりも低いという利点は める。 Also, as the electrode material of a PZT thin film capacitor and B i layer-type thin film capacitor, P t, I r, I R_〇 2, etc. actually used. Numerous studies on these have been made. At the research stage of PZT-based thin film capacitors in the mid-1990s, Ru-based (including Ru 電極2 ) electrode materials were also studied. However, if a Ru-based electrode material is used, it is difficult to control the leakage of the capacitor, and it has not been put to practical use. This will react with R u in P b and the electrode film in the ferroelectric, conductive I匕合of such pie port Kuroa structure as P b 2 R u 2 O 6 ~ 7 are generated That's why. However, Ru has the advantage that its bullion price is lower than that of Pt and Ir.
一般に、 P Z T膜の成膜時には、 膜中に P bが化学量論組成より多く入れられ る。 この超過分の Pbは結晶化初期の段階で重要な役割を果たすと共に、 高温で の P bの蒸発分を補う役割を持つており、 結晶化後は主に P Z T膜中の粒界に存 在する。 このような強誘電体膜に対して、 PZT膜との界面に Ruが存在すると 、 高温で?1 と反応して上記のょぅな?1)21 112067が生成され、 粒界に導電 パスが形成されてしまい、 リーク電流が増大するのである。 特許第 3 0 9 5 5 7 4号明細書には、 この現象を逆手にとって、 R u 02から なる電極と P Z Tからなる強誘電体膜との間に、 意図的に P b 2 R u 267から なる膜を形成する技術が記載されている。 Generally, when a PZT film is formed, Pb is contained in the film in an amount larger than the stoichiometric composition. This excess Pb plays an important role in the early stage of crystallization, and also has a role to supplement the evaporation of Pb at high temperature, and exists mainly at the grain boundaries in the PZT film after crystallization. I do. For such a ferroelectric film, if Ru exists at the interface with the PZT film at a high temperature? Is it the above mentioned in response to 1? 1) 2 11 12 26 to 7 are generated, and a conductive path is formed at the grain boundary, and the leakage current increases. Japanese Patent No. 3 0 9 5 5 7 4 Pat, this phenomenon for foul trick, between the ferroelectric layer made of the electrode and the PZT consisting of R u 0 2, deliberately P b 2 R u 2技術 A technique for forming a film consisting of 6 to 7 is described.
近時、 製造時間の短縮及び製造設備のコスト低減が要請されている。 しかし、 電極膜として P t膜等をスパッタ法により形成する場合には、 下部電極膜、 強誘 電体膜及び上部電極膜を形成するための各工程間でウェハの搬送が必要とされ、 また、 電極膜を形成するためのチヤンバ及び強誘電体膜を形成するためのチヤン バが必要とされる。 このため、 このような製造方法では、 製造時間の短縮及び製 造設備のコスト低減に限度がある。  Recently, there has been a demand for reduction of manufacturing time and cost of manufacturing equipment. However, when a Pt film or the like is formed as an electrode film by a sputtering method, it is necessary to transfer a wafer between steps for forming a lower electrode film, a strong dielectric film, and an upper electrode film. A chamber for forming an electrode film and a chamber for forming a ferroelectric film are required. For this reason, such a manufacturing method has limitations in shortening the manufacturing time and reducing the cost of the manufacturing equipment.
また、 R u系の電極膜を用いた場合には、 上述のように、 リーク電流が増大す るという欠点があり、 この欠点は、 特許第 3 0 9 5 5 7 4号明細書に記載された 技術によっても解決されていなレ、。 即ち、 この製造方法では、 R u〇2膜を形成 した後に、 その上に P Z T膜を形成し、 ァニールによってこれらの界面に、 P b 2 R u 206~7を形成しているが、 このような方法では、 ァニールの際に粒界拡散 が生じるため、 リーク電流の増大は避けられない。 このような現象は、 P Z T系 強誘電体膜の代わりに B i層状系強誘電体膜を用いた場合にも、 同様に、 B i 2 R u 20 7_xのようなパイ口クロア構造の導電性化合物が生成される可能性があ る。 Further, when a Ru-based electrode film is used, as described above, there is a drawback that the leak current increases. This drawback is described in Japanese Patent No. 3,095,574. It has not been solved by technology. That is, in this manufacturing method, after forming the R U_〇 2 film, a PZT film is formed thereon, these interfaces by Aniru, but forms a P b 2 R u 2 0 6 ~ 7, In such a method, an increase in leakage current is inevitable due to grain boundary diffusion during annealing. This phenomenon, in the case of using B i layered system ferroelectric film in place of the PZT system ferroelectric film likewise, B i 2 R u 2 0 of 7 _ x such pies port Croix structure Of the conductive compound may be generated.
特許文献 1  Patent Document 1
特許第 3 0 9 5 5 7 4号明細書 発明の開示  Patent No. 3 095 5 7 4 Disclosure of the Invention
本発明は、 力かる問題点に鑑みてなされたものであって、 強誘電体膜と電極膜 とを同一のチャンバ内で連続して形成することができる強誘電体キャパシタの製 造方法を提供することを目的とする。  SUMMARY OF THE INVENTION The present invention has been made in view of the difficult problem, and provides a method of manufacturing a ferroelectric capacitor in which a ferroelectric film and an electrode film can be continuously formed in the same chamber. The purpose is to do.
本願発明者は、 鋭意検討の結果、 以下に示す発明の諸態様に想到した。  As a result of intensive studies, the inventor of the present application has come up with the following aspects of the invention.
本発明に係る強誘電体キャパシタの製造方法は、 B i層状系強誘電体膜を備え た強誘電体キャパシタの製造方法を対象とする。  A method for manufacturing a ferroelectric capacitor according to the present invention is directed to a method for manufacturing a ferroelectric capacitor including a Bi layered ferroelectric film.
第 1の発明では、 先ず、 C VDチャンバ内に、 第 1の金属元素を含有するガス を導入して、 前記第 1の金属元素を含有する下部電極膜を形成する。 次に、 前記 C VDチャンバ内に、 前記第 1の金属元素を含有するガスを導入しつづけながら 、 更に B i及び Oを含有するガスを導入して、 前記下部電極膜上に前記第 1の金 属元素及び B iを含有する第 1の導電性化合物膜を形成する。 次いで、 前記 C V Dチャンパ内への前記第 1の金属元素の導入を停止する。 その後.. 前記 C VDチ ヤンパ内に、 B i及び Oを含有するガスを導入しつづけながら、 更に前記 B i層 状系強誘電体膜を構成する金属元素のうち B iを除く強誘電体膜用金属元素を含 有するガスを導入して、 前記第 1の導電性化合物膜上に前記 B i層状系強誘電体 膜を形成する。 続いて、 前記 C VDチャンバ内への B i及ぴ前記強誘電体膜用金 属元素の導入を停止する。 そして、 前記 B i層状系強誘電体膜上に上部電極膜を 形成する。 In the first invention, first, a gas containing a first metal element is placed in a CVD chamber. To form a lower electrode film containing the first metal element. Next, while continuously introducing the gas containing the first metal element into the CVD chamber, further introducing a gas containing Bi and O into the CVD chamber. A first conductive compound film containing a metal element and Bi is formed. Next, the introduction of the first metal element into the CVD champer is stopped. After that, while continuously introducing a gas containing Bi and O into the CVD chamber, the ferroelectric material excluding Bi among the metal elements constituting the Bi layered ferroelectric film is further added. A gas containing a metal element for a film is introduced to form the Bi layered ferroelectric film on the first conductive compound film. Subsequently, introduction of Bi and the metal element for the ferroelectric film into the CVD chamber is stopped. Then, an upper electrode film is formed on the Bi layered ferroelectric film.
第 2の発明では、 先ず、 下部電極膜を形成する。 次に、 前記 C VDチャンパ内 に、 B i、 前記 B i層状系強誘電体膜を構成する金属元素のうち B iを除く強誘 電体膜用金属元素及び Oを含有するガスを導入して、 前記下部電極膜上に前記 B i層状系強誘電体膜を形成する。 次いで、 前記 C VDチャンバ内への前記強誘電 体膜用金属元素の導入を停止する。 その後、 前記 C VDチャンバ内に、 B i及び Oを含有するガスを導入しつづけながら、 第 2の金属元素を含有するガスを導入 して、 前記 B i層状系強誘電体膜上に前記第 2の金属元素及び B iを含有する第 2の導電性化合物膜を形成する。 続いて、 前記 C VDチャンバ内への B iの導入 を停止する。 そして、 前記 C VDチャンパ内に、 前記第 2の金属元素を含有する ガスを導入しつづけて、 前記第 2の導電性化合物膜上に前記第 2の金属元素を含 有する上部電極膜を形成する。  In the second invention, first, a lower electrode film is formed. Next, into the CVD champer, a gas containing Bi and a metal element for a ferroelectric dielectric film excluding Bi among metal elements constituting the Bi-layered ferroelectric film and O is introduced. Then, the Bi layered ferroelectric film is formed on the lower electrode film. Next, the introduction of the metal element for a ferroelectric film into the CVD chamber is stopped. Thereafter, while continuously introducing a gas containing Bi and O into the CVD chamber, a gas containing a second metal element is introduced, and the gas containing the second metal element is introduced onto the Bi layered ferroelectric film. Forming a second conductive compound film containing the second metal element and Bi. Subsequently, the introduction of Bi into the CVD chamber is stopped. Then, a gas containing the second metal element is continuously introduced into the CVD champer to form an upper electrode film containing the second metal element on the second conductive compound film. .
前述のように、 従来の製造方法では、 R u等の電極膜中の金属元素と B i層状 系の強誘電体膜中の B iとが反応してリーク電流が増大する可能性があるが、 本 発明においては、 電極膜 (下部電極膜及び/又は上部電極膜) と強誘電体膜とを 同一の C VDチャンバ内で連続して形成すると共に、 これらの膜の間に導電性化 合物膜を形成している。 このように、 導電性化合物膜を C VD法で形成すること によって、 この膜内で B iと金属元素との反応を完了させることが可能となり、 強誘電体膜での反応を防止することができる。 この結果、 リーク電流の増大を防 止することができる。 図面の簡単な説明 As described above, in the conventional manufacturing method, there is a possibility that the metal element in the electrode film such as Ru reacts with the Bi in the Bi-layered ferroelectric film to increase the leakage current. In the present invention, an electrode film (lower electrode film and / or upper electrode film) and a ferroelectric film are formed continuously in the same CVD chamber, and a conductive compound is formed between these films. A material film is formed. Thus, by forming the conductive compound film by the CVD method, it is possible to complete the reaction between Bi and the metal element in this film, and to prevent the reaction in the ferroelectric film. it can. As a result, an increase in leakage current is prevented. Can be stopped. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明の第 1の実施形態に係る強誘電体メモリの製造方法を示すタイ ミングチヤートである。  FIG. 1 is a timing chart showing a method for manufacturing a ferroelectric memory according to the first embodiment of the present invention.
図 2 A乃至図 2 Gは、 本発明の第 1の実施形態に係る強誘電体メモリの製造方 法を工程順に示す断面図である。  2A to 2G are cross-sectional views illustrating a method of manufacturing the ferroelectric memory according to the first embodiment of the present invention in the order of steps.
図 3は、 本発明の第 1の実施形態において製造された強誘電体キャパシタを示 す断面図である。  FIG. 3 is a cross-sectional view showing a ferroelectric capacitor manufactured in the first embodiment of the present invention.
図 4は、 本発明の第 2の実施形態に係る強誘電体メモリの製造方法を示すタイ ミングチヤ一トである。  FIG. 4 is a timing chart showing a method for manufacturing a ferroelectric memory according to the second embodiment of the present invention.
図 5は、 本発明の第 2の実施形態に係る強誘電体メモリの製造方法を示す断面 図である。  FIG. 5 is a cross-sectional view illustrating a method for manufacturing a ferroelectric memory according to the second embodiment of the present invention.
図 6は、 本発明の第 2の実施形態において製造された強誘電体キャパシタを示 す断面図である。 ·  FIG. 6 is a cross-sectional view illustrating a ferroelectric capacitor manufactured in the second embodiment of the present invention. ·
図 7は、 本発明の第 3の実施形態に係る強誘電体メモリの製造方法を示すタイ ミングチヤ一トである。  FIG. 7 is a timing chart showing a method for manufacturing a ferroelectric memory according to the third embodiment of the present invention.
図 8は、 本発明の第 3の実施形態に係る強誘電体メモリの製造方法を示す断面 図である。  FIG. 8 is a cross-sectional view illustrating a method for manufacturing a ferroelectric memory according to the third embodiment of the present invention.
図 9は、 本発明の第 3の実施形態において製造された強誘電体キャパシタを示 す断面図である。  FIG. 9 is a cross-sectional view showing a ferroelectric capacitor manufactured in the third embodiment of the present invention.
図 1 0は、 本発明の第 3の実施形態の変形例を示すタイミングチヤ一トである  FIG. 10 is a timing chart showing a modification of the third embodiment of the present invention.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の実施の形態に係る強誘電体キャパシタの製造方法について添付 の図面を参照して具体的に説明する。  Hereinafter, a method for manufacturing a ferroelectric capacitor according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings.
(第 1の実施形態)  (First Embodiment)
先ず、 本発明の第 1の実施形態について説明する。 本実施形態では、 強誘電体 キャパシタを含む強誘電体メモリを製造する。 図 1は、 本発明の第 1の実施形態 に係る強誘電体メモリの製造方法を示すタイミングチヤ一トである。 また、 図 2 A乃至図 2 Gは、 同製造方法を工程順に示す断面図であり、 図 3は、 第 1の実施 形態において製造された強誘電体キャパシタを示す断面図である。 First, a first embodiment of the present invention will be described. In this embodiment, the ferroelectric A ferroelectric memory including a capacitor is manufactured. FIG. 1 is a timing chart showing a method for manufacturing a ferroelectric memory according to the first embodiment of the present invention. 2A to 2G are cross-sectional views showing the same manufacturing method in the order of steps, and FIG. 3 is a cross-sectional view showing the ferroelectric capacitor manufactured in the first embodiment.
先ず、 図 2 Aに示すように、 シリコン基板等の半導体基板 1 1の表面に、 例え ば S T I (shallow trench isolation) により素子分離領域 1 2を形成する。 次 いで、 素子分離領域 1 2により区画された素子活性領域において、 半導体基板 1 1の表面にゥエル 1 3を形成する。 続いて、 ゲート絶縁膜 1 7、 ゲート電極 1 8 、 シリサイド層 1 9、 低濃度拡散層 1 5、 サイドウオール 2 0及び高濃度拡散層 1 6をゥエル 1 3の表面に形成することにより、 MO S トランジスタ 1 4を形成 する。 なお、 各 MO Sトランジスタ 1 4には、 ソース及びドレイン用に 2個の高 濃度拡散層 1 6を形成するが、 その一方は、 2個の MO S トランジスタ 1 4間で 共有させる。  First, as shown in FIG. 2A, an element isolation region 12 is formed on the surface of a semiconductor substrate 11 such as a silicon substrate by, for example, STI (shallow trench isolation). Next, a well 13 is formed on the surface of the semiconductor substrate 11 in the element active region partitioned by the element isolation region 12. Subsequently, a gate insulating film 17, a gate electrode 18, a silicide layer 19, a low-concentration diffusion layer 15, a sidewall 20, and a high-concentration diffusion layer 16 are formed on the surface of the well 13. The S transistor 14 is formed. Each MOS transistor 14 has two high-concentration diffusion layers 16 for source and drain, one of which is shared by the two MOS transistors 14.
次に、 全面にシリコン酸窒ィ匕膜 2 1を、 MO Sトランジスタ 1 4を覆うように して形成し、 更に全面にシリコン酸化膜 2 2を、 例えば有機 C VD法により形成 する。 シリコン酸窒化莫 2 1は、 シリコン酸化膜 2 2を形成する際のゲート絶縁 膜 1 7等の水素劣ィ匕を防止するために形成されている。 その後、 各高濃度拡散層 1 6間で到達するコンタクトホールをシリコン酸化膜 2 2及びシリコン酸窒化膜 2 1に形成することにより、 プラグコンタクト部を開口する。 そして、 コンタク トホール内に、 グルー膜 2 3として、 5 0 n mの T i N膜及び 3 0 n mの T i膜 からなる積層膜を形成した後、 例えば C VD法により W膜を埋め込み、 CMP ( ィ匕学機械的研磨) を行つて 坦化することにより、 Wプラグ 2 4を形成する。 次いで、 図 2 Bに示すように、 全面に R u膜 (下部電極膜) 2 5、 下部導電性 化合物膜 2 5 a及ぴ B L T ( (B i , L a ) 4 T i 30 1 2) 膜 2 6を同一チャンパ 内で MO C V D法により連続して形成する。 Next, a silicon oxynitride film 21 is formed on the entire surface so as to cover the MOS transistor 14, and a silicon oxide film 22 is further formed on the entire surface by, for example, an organic CVD method. The silicon oxynitride layer 21 is formed to prevent the gate insulating film 17 and the like from forming hydrogen when the silicon oxide film 22 is formed. Thereafter, a contact hole reaching between the high concentration diffusion layers 16 is formed in the silicon oxide film 22 and the silicon oxynitride film 21 to open a plug contact portion. Then, after forming a laminated film composed of a 50 nm TiN film and a 30 nm Ti film as a glue film 23 in the contact hole, a W film is buried by, for example, the CVD method, and the CMP ( The W plug 24 is formed by carrying out and carrying out. Then, as shown in FIG. 2 B, the entire surface R u film (lower electrode film) 2 5, the lower conductive compound film 2 5 a及Pi BLT ((B i, L a ) 4 T i 3 0 1 2) The film 26 is formed continuously by the MOCVD method in the same champer.
ここで、 これらの B莫 2 5、 2 5 a及び 2 6を形成する方法について説明する。 これらの原料 (プリカーサ) として、 例えば表 1に示すものを用いる。 また、 溶 媒としては、 例えば n—へキサンを用いる。 MO C VD装置としては、 これらの 原料を同一の気化器内にて気化することが可能なものを用いることが望ましい。 Ru膜 25の形成に当たっては、 先ず、 MOCVDチャンバのサセプタの温度 を 500°Cにした後、 このサセプタに半導体基板 11を載置する。 そして、 半導 体基板 11の温度が一定となった後に、 図 1に示すように、 キヤリァガスとして の窒素ガスと共に、 Ru原料を MOCVDチャンバ内に供給する。 この状態を維 持することにより、 Ru膜 25が形成される。 Here, a method for forming these B25, 25a and 26 will be described. As these raw materials (precursors), for example, those shown in Table 1 are used. Further, as the solvent, for example, n-hexane is used. It is desirable to use a MOC VD device that can vaporize these raw materials in the same vaporizer. In forming the Ru film 25, first, the temperature of the susceptor in the MOCVD chamber is set to 500 ° C., and then the semiconductor substrate 11 is mounted on the susceptor. Then, after the temperature of the semiconductor substrate 11 becomes constant, a Ru raw material is supplied into the MOCVD chamber together with a nitrogen gas as a carrier gas, as shown in FIG. By maintaining this state, the Ru film 25 is formed.
次いで、 窒素ガスを 20体積%に減じると共に、 反応ガスとして 80体積%分 の酸素ガスの供給を開始し、 さらに B i原料の供給を開始する。 その直後に、 R u原料の供給を停止する。 この結果、 図 1に示すように、 MOCVDチャンバ内 の B i量が上昇すると共に、 Ru量は下降する。 この間に、 下部導電性化合物月莫 (B i 2Ru207x膜) 25 aが形成される。 Next, the nitrogen gas is reduced to 20% by volume, the supply of oxygen gas for 80% by volume as a reaction gas is started, and the supply of Bi raw material is started. Immediately thereafter, the supply of the Ru raw material is stopped. As a result, as shown in FIG. 1, the amount of Bi in the MOCVD chamber increases and the amount of Ru decreases. During this time, the lower conductive compound month trillions (B i 2 Ru 2 0 7 one x film) 25 a is formed.
Ru原料が完全に MOCVDチャンバ内に導入されなくなった後、 図 1に示す ように、 B i原料の供給を維持したまま、 T i原料及び La原料の供給を開始す る。 この状態を維持することにより、 B LT膜 26が形成される。  After the Ru source is no longer introduced into the MOCVD chamber, supply of the Ti source and La source is started while maintaining the supply of the Bi source, as shown in Fig. 1. By maintaining this state, the BLT film 26 is formed.
次いで、 図 1に示すように、 T i原料及び L a原料の供給を停止し、 その直後 に、 B i原料の供給も停止する。  Next, as shown in FIG. 1, the supply of the Ti raw material and the La raw material is stopped, and immediately thereafter, the supply of the Bi raw material is also stopped.
これらの工程により、 Ru 25、 下部導電性化合物膜 25 a及び BLT膜 2 6が形成される。  Through these steps, Ru 25, lower conductive compound film 25a, and BLT film 26 are formed.
B i原料、 T i原料及び L a原科が完全に MOCVDチャンパ内に導入されな くなつた後、 半導体基板 1 1を MOCVDチャンバから取り出し、 図 2Bに示す ように、 BLT膜 26上に P t膜 (上部電極膜) 27をスパッタ法により形成し 、 例えば 500°Cの酸素雰囲気中で 60分間のァニールを行う。 このァニールに より、 P t膜 27のスパッタ成膜による BLT膜 26のプラズマ損傷が回復する 続いて、 図 2 Cに示すように、 パターニング及ぴエッチング技術を用いて、 P t膜 27、 B L T膜 26、 下部導電性化合物膜 25 a及び R u膜 25を加工する ことにより、 P t膜 27を上部電極とし、 Ru膜 25を下部電極とし、 これらの 間に BLT膜 26が挟まれたスタック構造の強誘電体キャパシタを形成する。 な お、 この加工では、 例えばプラズマ TEOS (tetraethyl orthosilicate) 膜及 び T i N膜の積層膜 (図示せず) をハードマスクとして使用し、 1:膜27、 B L T膜 2 6、 下部導電性化合物膜 2 5 a及ぴ R u膜 2 5を一括してェッチングす る。 After the Bi raw material, the Ti raw material, and the La raw material are no longer completely introduced into the MOCVD chamber, the semiconductor substrate 11 is removed from the MOCVD chamber, and the PLT is deposited on the BLT film 26 as shown in FIG. 2B. A t film (upper electrode film) 27 is formed by sputtering, and annealing is performed for 60 minutes in an oxygen atmosphere at 500 ° C., for example. By this annealing, the plasma damage of the BLT film 26 due to the sputter deposition of the Pt film 27 is recovered. Subsequently, as shown in FIG. 2C, the Pt film 27 and the BLT film are formed by using patterning and etching techniques. 26, By processing the lower conductive compound film 25a and the Ru film 25, a stack structure in which the Pt film 27 is used as the upper electrode, the Ru film 25 is used as the lower electrode, and the BLT film 26 is sandwiched between them. Is formed. In this processing, for example, a laminated film (not shown) of a plasma TEOS (tetraethyl orthosilicate) film and a TiN film is used as a hard mask. The LT film 26, the lower conductive compound film 25a and the Ru film 25 are etched all at once.
次に、 図 2 Dに示すように、 強誘電体キャパシタを覆うアルミナ保護膜 2 8を 全面に形成する。 アルミナ保護膜 2 8は、 例えば C VD法により形成し、 その厚 さは、 例えば 5乃至 2 0 n m、 本実施形態では 1 0 n mとする。  Next, as shown in FIG. 2D, an alumina protective film 28 covering the ferroelectric capacitor is formed on the entire surface. The alumina protective film 28 is formed, for example, by the CVD method, and has a thickness of, for example, 5 to 20 nm, and 10 nm in the present embodiment.
次いで、 図 2 Eに示すように、 全面に層間絶縁膜 2 9を成膜した後、 これを C MPにより平坦化する。 層間絶縁 S莫 2 9としては、 例えば H D P (High Density Plasma) C V D装置を使用してシリコン酸ィ匕膜を成膜する。 また、 層間絶縁膜 2 9として T E O S酸化膜を成膜してもよい。 CMP後の残し膜厚は、 例えば P t 膜 2 7上で 3 0 0 n mとする。  Next, as shown in FIG. 2E, after an interlayer insulating film 29 is formed on the entire surface, it is planarized by CMP. As the interlayer insulation layer 29, for example, a silicon oxide film is formed using an HDP (High Density Plasma) CVD apparatus. Further, a TEOS oxide film may be formed as the interlayer insulating film 29. The remaining film thickness after the CMP is, for example, 300 nm on the Pt film 27.
続いて、 図 2 Fに示すように、 パターニング及びエッチング技術を用いて、 層 間絶縁膜 2 9及びアルミナ保護膜 2 8に、 2個の MO Sトランジスタ 1 4により 共有された高濃度拡散層 1 6に接続された Wブラグ 2 4まで到達するコンタクト ホールを形成する。 次に、 このコンタクトホール内にグルー膜 3 0として、 例え ば 5 0 n mの T i N膜を形成した後、 例えば C V D法により W膜を埋め込み、 C M P (化学機械的研磨) を行つて平坦化することにより、 Wプラグ 3 1を形成す る。 その後、 例えば 3 5 0 °Cで N 2プラズマに層間絶縁膜 2 9及び Wプラグ 3 1 の表面を晒す。 このプラズマ処理の時間は、 例えば 1 2 0秒間である。 Subsequently, as shown in FIG. 2F, using a patterning and etching technique, the high-concentration diffusion layer 1 shared by the two MOS transistors 14 is added to the interlayer insulating film 29 and the alumina protective film 28. Form a contact hole reaching W plug 24 connected to 6. Next, a glue film 30 is formed in this contact hole, for example, a 50-nm-thick TiN film, and then a W film is buried by, for example, a CVD method, and planarized by CMP (chemical mechanical polishing). Thus, a W plug 31 is formed. After that, the surface of the interlayer insulating film 29 and the surface of the W plug 31 are exposed to N 2 plasma at 350 ° C., for example. The time of this plasma processing is, for example, 120 seconds.
次いで、 全面に W酸ィ匕防止膜 (図示せず) を形成する。 W酸化防止膜としては 、 例えば S i O N膜を使用することができ、 その厚さは例えば 1 0 Ο η ηι程度で ある。 そして、 パタ一ユング及びエッチング技術を用いて、 図 2 Gに示すように 、 W酸ィ匕防止膜及び層間絶縁膜 2 9に、 上部電極たる P t膜 2 7まで到達するコ ンタクトホールを形成する。 続いて、 エッチングによる損傷を回復させるための ァニールを施す。 このァニールは、 例えば 5 5 0 °Cで 0 2雰囲気の炉内ァニール としてもよく、 その時間は例えば 6 0分間である。 このァニールの後、 W酸化防 止膜をェツチバックにより除去する。 Next, a W oxidation preventing film (not shown) is formed on the entire surface. As the W oxidation preventing film, for example, a SiON film can be used, and its thickness is, for example, about 10 程度 ηηι. Then, using a patterning and etching technique, as shown in FIG. 2G, a contact hole reaching the Pt film 27 serving as the upper electrode is formed in the W oxidation preventing film and the interlayer insulating film 29. I do. Subsequently, an anneal is applied to recover the damage caused by the etching. This Aniru, for example 5 5 0 ° C in may be a furnace Aniru 0 2 atmosphere, the time is for example for 60 minutes. After this annealing, the W oxidation preventing film is removed by etch back.
次に、 グルー膜、 配線材料膜及びグルー膜を順次堆積する。 下層のグルー膜と しては、 例えば厚さが 7 0 n mの T i N膜と 5 n mの T i膜との積層膜を形成し てもよく、 配線材料膜としては、 例えば厚さが 4 0 0 n mの A 1— C u合金膜を 形成してもよく、 上層のグルー膜としては、 例えば厚さが 30 nmの T i N膜と 6011111の丁 i膜との積層膜を形成してもよい。 Next, a glue film, a wiring material film, and a glue film are sequentially deposited. As the lower glue film, for example, a laminated film of a 70 nm thick TiN film and a 5 nm Ti film may be formed. 100 nm A 1—Cu alloy film The upper glue film may be, for example, a laminated film of a 30 nm thick TiN film and a 6011111 thin film.
次いで、 上層のグルー膜上に反射防止膜を塗布により形成し、 更にレジストを 塗布する。 続いて、 レジスト膜を配線パターンに整合するように加工し、 加工後 のレジスト膜をマスクとして、 反射防止膜、 上層のグルー膜、 配線材料膜及び下 層のグルー膜をエッチングする。 反射防止膜としては、 例えば S i ON膜を使用 することができ、 その厚さは例えば 30 nm程度である。 このようなエッチング により、 図 2 Gに示すように、 グルー膜 32、 配線 33及びグルー膜 34が形成 される。  Next, an anti-reflection film is formed on the upper glue film by coating, and a resist is further applied. Subsequently, the resist film is processed so as to match the wiring pattern, and the antireflection film, the upper glue film, the wiring material film, and the lower glue film are etched using the processed resist film as a mask. For example, a SiON film can be used as the antireflection film, and its thickness is, for example, about 30 nm. By such etching, as shown in FIG. 2G, a glue film 32, a wiring 33 and a glue film 34 are formed.
その後、 更に、 層間絶縁膜の形成、 コンタクトプラグの形成及び下から第 2層 目以降の配線の形成等を行う。 そして、 例えば T EOS酸化膜及ぴ S i N膜から なるカバー膜を形成して強誘電体キャパシタを有する強誘電体メモリを完成させ る。  Then, further, an interlayer insulating film is formed, a contact plug is formed, and wirings for the second and subsequent layers from the bottom are formed. Then, a cover film made of, for example, a TEOS oxide film and a SiN film is formed to complete a ferroelectric memory having a ferroelectric capacitor.
このように、 本実施形態においては、 下部電極膜たる Ru膜 25と強誘電体膜 たる BLT膜 26とを同一チャンバ内で連続して形成するに当たって、 原料の供 給開始及び供給停止の順序を適切に規定しており、 B L T膜 26を形成する前に 、 下部導電性化合物膜 25 aを形成すると共に、 この下部導電性化合物膜 25 a 内で Ruと B iとの反応を完了させている。 このため、 BLT膜 26を形成する 際には、 R uの B L T膜 26への拡散は下部導電性化合物膜 25 aにより防止さ れる。 従って、 本実施形態によれば、 Ru膜 25を下部電極として用いても、 従 来のようにリーク電流が増大することはない。  As described above, in the present embodiment, when the Ru film 25 as the lower electrode film and the BLT film 26 as the ferroelectric film are continuously formed in the same chamber, the order of starting and stopping the supply of the raw material is determined. The lower conductive compound film 25a is formed before the BLT film 26 is formed, and the reaction between Ru and Bi is completed in the lower conductive compound film 25a. . Therefore, when the BLT film 26 is formed, the diffusion of Ru into the BLT film 26 is prevented by the lower conductive compound film 25a. Therefore, according to the present embodiment, even if the Ru film 25 is used as the lower electrode, the leak current does not increase as before.
ここで、 本願発明者が第 1の実施形態に係る製造方法の検証を行った結果につ いて説明する。 この検証では、 S i基板 (ウェハ) 上に S i 02膜及び T i N膜 を形成し、 その上に強誘電体キャパシタを形成した。 強誘電体キャパシタの形成 条件は、 第 1の実施形態と同様である。 但し、 Ru膜 25の厚さは 10 Onm程 度とし、 BLT膜 26の厚さは 100 nm程度とした。 Here, the result of the inventors of the present invention verifying the manufacturing method according to the first embodiment will be described. In this verification, a SiO 2 film and a Ti N film were formed on a Si substrate (wafer), and a ferroelectric capacitor was formed thereon. The conditions for forming the ferroelectric capacitor are the same as in the first embodiment. However, the thickness of the Ru film 25 was about 10 Onm, and the thickness of the BLT film 26 was about 100 nm.
そして、 P t膜 27を形成する前に、 BLT膜 26及ぴ Ru膜 25を含む積層 膜の膜厚方向の組成を S IMSで分析したところ、 B L T膜 26と R u膜 25と の間に、 20 nm程度の厚さにわたって B i及ぴ R uが共存する領域が観察され た。 この領域が下部導電性化合物膜 2 5 aである。 また、 B L T膜 2 6中への1 uの拡散は観察されなかつた。 Before forming the Pt film 27, the composition in the thickness direction of the stacked film including the BLT film 26 and the Ru film 25 was analyzed by SIMS. A region where Bi and Ru coexist is observed over a thickness of about 20 nm. Was. This region is the lower conductive compound film 25a. Also, no diffusion of 1 u into the BLT film 26 was observed.
更に、 メタルスル一マスクを用いて上部電極膜たる P t膜 2 7をスパッタ法に より形成し、 5 0 0 °Cの酸素雰囲気中で 6 0分間のァニールを行った後に、 5 V のリーク電流密度を測定したところ、 当該電流密度は 1 X 1 0— 6 A/ c m2のォ ーダ一であった。 また、 分極特性を示す 1 . 5 Vのスィッチ電荷量 Q s wは、 3 0 μ C/ c m2程度であった。 これらの結果、 第 1の実施形態によれば、 良好な 特性の強誘電体キャパシタが得られることが確認された。 Further, a Pt film 27 as an upper electrode film was formed by a sputtering method using a metal through mask, and after annealing for 60 minutes in an oxygen atmosphere at 500 ° C., a leakage current of 5 V was obtained. was measured density, the current density was O over da one 1 X 1 0- 6 a / cm 2. Also, the 1.5 V switch charge amount Qsw indicating the polarization characteristic was about 30 μC / cm 2 . As a result, according to the first embodiment, it was confirmed that a ferroelectric capacitor having good characteristics could be obtained.
(第 2の実施形態)  (Second embodiment)
次に、 本発明の第 2の実施形態について説明する。 第 2の実施形態では、 強誘 電体キャパシタの製造方法が第 1の実施形態と相違している。 図 4は、 本発明の 第 2の実施形態に係る強誘電体メモリの製造方法を示すタイミングチヤ一トであ る。 また、 図 5は、 本発明の第 2の実施形態に係る強誘電体メモリの製造方法を 示す断面図であり、 図 6は、 第 2の実施形態において製造された強誘電体キャパ シタを示す断面図である。 なお、 図 5は、 '第 1の実施形態の一部の工程を示す図 2 Bに相当する。  Next, a second embodiment of the present invention will be described. The second embodiment differs from the first embodiment in the method of manufacturing a strong dielectric capacitor. FIG. 4 is a timing chart showing a method for manufacturing a ferroelectric memory according to the second embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a method of manufacturing a ferroelectric memory according to a second embodiment of the present invention, and FIG. 6 illustrates a ferroelectric capacitor manufactured according to the second embodiment. It is sectional drawing. FIG. 5 corresponds to FIG. 2B showing a part of the steps of the first embodiment.
本実施形態では、 先ず、 第 1の実施形態と同様にして、 Wプラグ 2 4の形成ま での工程を行う。  In the present embodiment, first, the steps up to the formation of the W plug 24 are performed in the same manner as in the first embodiment.
次いで、 図 5に示すように、 全面に I r膜 (下部電極膜) 3 5をスパッタ法に より形成する。  Next, as shown in FIG. 5, an Ir film (lower electrode film) 35 is formed on the entire surface by sputtering.
その後、 図 5に示すように、 B L TB莫 2 6、 上部導電†生化合物 B莫 3 7 a及ぴ R u O 2膜 3 7を同一チヤンバ内で M〇 C VD法により連続して形成する。 Then, as shown in FIG. 5, BL TB 26, upper conductive compound B 37 a and RuO 2 film 37 are continuously formed in the same chamber by the M〇C VD method. .
ここで、 これらの膜 2 6、 3 7 a及び 3 7を形成する方法について説明する。 これらの原料 (プリカーサ) 及び溶媒としては、 第 1の実施形態と同様に、 例え ば表 1に示すもの、 n—へキサンを用いる。 MO C VD装置としては、 第 1の実 施形態と同様に、 これらの原料を同一の気化器内にて気ィ匕することが可能なもの を用いることが望ましい。  Here, a method of forming these films 26, 37a and 37 will be described. As these raw materials (precursors) and solvents, for example, those shown in Table 1 and n-hexane are used as in the first embodiment. As in the first embodiment, it is desirable to use an MOC VD apparatus capable of degassing these raw materials in the same vaporizer, as in the first embodiment.
B L T膜 2 6の形成に当たっては、 先ず、 MO C VDチャンバのサセプタの温 度を 5 0 0 °Cにした後、 このサセプタに半導体基板 1 1を载置する。 そして、 半 導体基板 11の温度が一定となった後に、 図 4に示すように、 キャリアガスとし ての窒素ガス 20体積0 /0及び反応ガスとしての酸素ガス 80体積0 /0と共に、 B i 原料を MOCVDチャンバ内に供給する。 その直後に、 T i原料及び La原料の 供給を開始する。 この状態を維持することにより、 BLT膜 26が形成される。 次いで、 T i原料及び L a原料の供給を停止し、 T i原料及び L a原料が完全 に MOCVDチャンバ内に導入されなくなった後、 図 4に示すように、 Ru原料 の供給を開始し、 その直後に、 B i原料の供給を停止する。 この結果、 図 4に示 すように、 MOCVDチャンパ内の Ru量が上昇すると共に、 B i量は下降する 。 この間に、 上部導電十生化合物膜 (B i 2Ru207_x膜) 37 aが形成される。 そして、 B i原料が完全に MOCVDチャンバ内に導入されなくなった後にも 、 図 4に示すように、 Ru原料の供給を続けることにより、 11〇2膜37が形 成される。 Ru膜ではなく Ru02膜 37が形成されるのは、 第 1の実施形態に おける R u膜 25の形成時とは異なり、 本実施形態では、 酸素ガスの供給が維持 されているからである。 In forming the BLT film 26, first, the temperature of the susceptor of the MOC VD chamber is set to 500 ° C., and the semiconductor substrate 11 is placed on the susceptor. And half MOCVD After the temperature of the conductor substrate 11 becomes constant, as shown in FIG. 4, the oxygen gas 80 vol 0/0 as nitrogen gas 20 vol 0/0 and the reaction gas as a carrier gas, a B i starting material Supply into the chamber. Immediately after that, supply of Ti raw material and La raw material is started. By maintaining this state, the BLT film 26 is formed. Next, the supply of the Ti raw material and the La raw material was stopped, and after the Ti raw material and the La raw material were not completely introduced into the MOCVD chamber, the supply of the Ru raw material was started as shown in FIG. Immediately thereafter, the supply of the Bi raw material is stopped. As a result, as shown in FIG. 4, the amount of Ru in the MOCVD champer increases and the amount of Bi decreases. During this time, the upper conductive tens raw compound film (B i 2 Ru 2 0 7 _ x film) 37 a is formed. After the B i material could be introduced completely MOCVD chamber also, as shown in FIG. 4, by continuing the supply of the Ru material, 11_Rei 2 film 37 is made form. The reason why the RuO 2 film 37 is formed instead of the Ru film is that the supply of oxygen gas is maintained in the present embodiment, unlike the case of forming the Ru film 25 in the first embodiment. .
その後、 図 4に示すように、 Ru原料の供給を停止する。  Then, as shown in FIG. 4, the supply of the Ru raw material is stopped.
これらの工程により、 BLT膜 26、 上部導電性化合物膜 37 a及び R u O 2 膜 37が形成される。 Through these steps, the BLT film 26, the upper conductive compound film 37a and the RuO 2 film 37 are formed.
そして、 Ru原料が完全に MOCVDチャンバ内に導入されなくなった後、 半 導体基板 11を MOCVDチャンバから取り出し、 第 1の実施形態と同様に、 強 誘電体キャパシタの加工以降の工程を行うことにより、 強誘電体キャパシタを有 する強誘電体メモリを完成させる。  Then, after the Ru raw material is not completely introduced into the MOCVD chamber, the semiconductor substrate 11 is taken out of the MOCVD chamber, and the processes after the ferroelectric capacitor are processed as in the first embodiment. Complete a ferroelectric memory having a ferroelectric capacitor.
本実施形態においては、 上部電極膜たる Ru02膜 37を形成する前に、 上部 導電性化合物膜 37 aを形成すると共に、 この上部導電性化合物膜 37 a内で R uと B iとの反応を完了させている。 このため、 Ru02膜 37を形成する際に は、 R uの B L T膜 26への拡散は上部導電性化合物膜 37 aにより防止される 。 従って、 本実施形態によれば、 Ru02膜 37を上部電極として用いても、 従 来のようにリーク電流が増大することはなレ、。 In the present embodiment, before the RuO 2 film 37 serving as the upper electrode film is formed, the upper conductive compound film 37a is formed, and the reaction between Ru and Bi in the upper conductive compound film 37a is performed. Has been completed. Therefore, when forming the RuO 2 film 37, the diffusion of Ru into the BLT film 26 is prevented by the upper conductive compound film 37a. Therefore, according to the present embodiment, even if the RuO 2 film 37 is used as the upper electrode, the leak current does not increase as before.
ここで、 本願発明者が第 2の実施形態に係る製造方法の検証を行った結果につ いて説明する。 この検証では、 第 1の実施形態と同様に、 S i基板 (ウェハ) 上 に S i 02膜及び T i N膜を形成し、 その上に強誘電体キャパシタを形成した。 強誘電体キャパシタの形成条件は、 第 2の実施形態と同様である。 但し、 BLT 膜 26の厚さは 1 00 nm程度とし、 Ru〇2膜 37の厚さは 1 00 nm程度と した。 Here, the results of verification of the manufacturing method according to the second embodiment by the present inventor will be described. In this verification, as in the first embodiment, on the Si substrate (wafer) Then, a SiO 2 film and a Ti N film were formed, and a ferroelectric capacitor was formed thereon. The conditions for forming the ferroelectric capacitor are the same as in the second embodiment. However, the thickness of the BLT film 26 was about 100 nm, and the thickness of the Ru 2 film 37 was about 100 nm.
そして、 Ru〇2膜 37を形成した後に、 Ru〇2膜 37及び BLT膜 26を 含む積層膜の膜厚方向の組成を S IMSで分析したところ、 R u O 2膜 37と B LT膜 26との間に、 20 nm程度の厚さにわたって B i及び Ruが共存する領 域が観察された。 この領域が上部導電性化合物膜 37 aである。 また、 BLT膜 26中への Ruの拡散は観察されなかった。 Then, after forming the Ru_〇 2 film 37, composition of the film thickness direction of the laminated film including a Ru_〇 2 film 37 and BLT film 26 was analyzed by S IMS, R u O 2 film 37 and the B LT film 26 In between, a region where Bi and Ru coexist was observed over a thickness of about 20 nm. This region is the upper conductive compound film 37a. Further, diffusion of Ru into the BLT film 26 was not observed.
更に、 フォトリソグラフィ技術により、 Ru02膜 37及び上部導電性化合物 膜 37 aに相当する厚さが 1 20 nmの部分をパターニングし、 500°Cの酸素 雰囲気中で 60分間のァニールを行った後に、 5 Vのリーク電流密度を測定した ところ、 当該電流密度は 1 X 1 0一6 AZ cm2のオーダーであった。 また、 分極 特性を示す 1. 5Vのスィッチ電荷量 Q s wは、 30 μ CZcm2程度であった 。 これらの結果、 第 2の実施形態によれば、 良好な特性の強誘電体キャパシタが 得られることが確認された。 Further, by photolithography, patterning the thick portions of 1 20 nm, which corresponds to Ru0 2 layer 37 and the upper conductive compound film 37 a, after the Aniru for 60 minutes in an oxygen atmosphere at 500 ° C When the leakage current density of 5 V was measured, the current density was on the order of 1 × 10 16 AZcm 2 . Further, the 1.5 V switch charge amount Qsw indicating the polarization characteristic was about 30 μCZcm 2 . As a result, according to the second embodiment, it was confirmed that a ferroelectric capacitor having good characteristics could be obtained.
(第 3の実施形態)  (Third embodiment)
次に、 本発明の第 3の実施形態について説明する。 第 3の実施形態では、 強誘 電体キャパシタの製造方法が第 1及び第 2の実施形態と相違している。 図 1は、 本発明の第 3の実施形態に係る強誘電体メモリの製造方法を示すタイミングチヤ ートである。 また、 図 8は、 本発明の第 3の実施形態に係る強誘電体メモリの製 造方法を示す断面図であり、 図 9は、 第 3の実施形態において製造された強誘電 体キャパシタを示す断面図である。 なお、 図 8は、 第 1の実施形態の一部の工程 を示す図 2 Bに相当する。  Next, a third embodiment of the present invention will be described. The third embodiment differs from the first and second embodiments in the method of manufacturing a strong dielectric capacitor. FIG. 1 is a timing chart showing a method for manufacturing a ferroelectric memory according to a third embodiment of the present invention. FIG. 8 is a cross-sectional view illustrating a method of manufacturing a ferroelectric memory according to the third embodiment of the present invention, and FIG. 9 illustrates a ferroelectric capacitor manufactured according to the third embodiment. It is sectional drawing. FIG. 8 corresponds to FIG. 2B showing some steps of the first embodiment.
本実施形態では、 先ず、 第 1の実施形態と同様にして、 Wプラグ 24の形成ま での工程を行う。  In the present embodiment, first, the steps up to the formation of the W plug 24 are performed in the same manner as in the first embodiment.
次いで、 図 8に示すように、 全面に Ru膜 (下部電極膜) 25、 下部導電性ィ匕 合物膜 25 a、 B L T膜 26、 上部導電性化合物膜 37 a及び R u O 2膜 (上部 電極膜) 3 7を同一チャンバ内で MOCVD法により連続して形成する。 ここで、 これらの膜 25、 25 a、 26、 37 a及び 37を形成する方法につ いて説明する。 これらの原料 (プリカーサ) 及ぴ溶媒としては、 第 1の実施形態 と同様に、 例えば表 1に示すもの、 n—へキサンを用いる。 MOCVD装置とし ては、 第 1の実施形態と同様に、 これらの原料を同一の気化器内にて気化するこ とが可能なものを用いることが望まし 、。 Next, as shown in FIG. 8, Ru film (lower electrode film) 25, lower conductive film 25a, BLT film 26, upper conductive compound film 37a, and RuO 2 film (upper surface) are formed on the entire surface. Electrode films) 37 are continuously formed by MOCVD in the same chamber. Here, a method for forming these films 25, 25a, 26, 37a and 37 will be described. As these raw materials (precursors) and solvents, for example, those shown in Table 1 and n-hexane are used as in the first embodiment. As in the first embodiment, it is desirable to use a MOCVD apparatus capable of vaporizing these raw materials in the same vaporizer, as in the first embodiment.
Ru膜 25の形成に当たっては、 第 1の実施形態と同様に、 先ず、 MOCVD チャンバのサセプタの温度を 500°Cにした後、 このサセプタに半導体基板 11 を載置する。 そして、 半導体基板 11の温度が一定となった後に、 図 7に示すよ うに、 キヤリァガスとしての窒素ガスと共に、 Ru原料を MOCVDチャンバ内 に供給する。 この状態を維持することにより、 Ru膜 25が形成される。  In forming the Ru film 25, as in the first embodiment, first, the temperature of the susceptor in the MOCVD chamber is set to 500 ° C., and then the semiconductor substrate 11 is mounted on the susceptor. Then, after the temperature of the semiconductor substrate 11 becomes constant, a Ru raw material is supplied into the MOCVD chamber together with a nitrogen gas as a carrier gas as shown in FIG. By maintaining this state, the Ru film 25 is formed.
次レ、で、窒素ガスを 20体積%に減じると共に、 反応ガスとして 80体積%分 の酸素ガスの供給を開始し、 さらに B i原料の供給を開始する。 その直後に、 R u原料の供給を停止する。 この結果、 図 7に示すように、 MOCVDチャンパ内 の B i量が上昇すると共に、 Ru量は下降する。 この間に、 下部導電性化合物膜 (B i 2Ru207x膜) 25 aが形成される。 Next, the nitrogen gas is reduced to 20% by volume, the supply of oxygen gas of 80% by volume as a reaction gas is started, and the supply of Bi raw material is started. Immediately thereafter, the supply of the Ru raw material is stopped. As a result, as shown in FIG. 7, the amount of Bi in the MOCVD champer increases and the amount of Ru decreases. During this time, the lower conductive compound film (B i 2 Ru 2 0 7 - x film) 25 a is formed.
Ru原料が完全に MOCVDチャンパ内に導入されなくなった後、 図 7に示す ように、 B i原料の供給を維持したまま、 T i原料及び L a原料の供給を開始す る。 この状態を維持することにより、 BLT膜 26が形成される。  After the Ru source is no longer completely introduced into the MOCVD champer, as shown in Fig. 7, the supply of the Ti source and the La source is started while the supply of the Bi source is maintained. By maintaining this state, the BLT film 26 is formed.
次いで、 T i原料及び L a原料の供給を停止し、 T i原料及ぴ L a原料が完全 に MOCVDチャンバ内に導入されなくなった後、 図 7に示すように、 Ru原料 の供給を開始し、 その直後に、 B i原料の供給を停止する。 この結果、 図 7に示 すように、 MOCVDチャンバ内の Ru量が上昇すると共に、 B i量は下降する 。 この間に、 上部導電性化合物膜 (B i 2Ru 207 x膜) 37 aが形成される。 そして、 B i原料が完全に MOCVDチャンバ内に導入されなくなった後にも 、 図 7に示すように、 Ru原料の供給を続けることにより、 尺 102膜37が形 成される。 Next, the supply of the Ti raw material and the La raw material was stopped, and after the Ti raw material and the La raw material were not completely introduced into the MOCVD chamber, the supply of the Ru raw material was started as shown in FIG. Immediately thereafter, the supply of the Bi raw material is stopped. As a result, as shown in FIG. 7, the Ru amount in the MOCVD chamber increases and the Bi amount decreases. During this time, the upper conductive compound film (B i 2 Ru 2 0 7 x film) 37 a is formed. After the B i material could be introduced completely MOCVD chamber also, as shown in FIG. 7, by continuing the supply of the Ru material, length 10 2 film 37 is made form.
その後、 図 7に示すように、 Ru原料の供給を停止する。  Thereafter, as shown in FIG. 7, the supply of the Ru raw material is stopped.
これらの工程により、 1 11膜25、 下部導電性化合物膜 25 a、 BLT膜 26 、 上部導電性化合物膜 37 a及ぴ Ru02膜 37が形成される。 そして、 Ru原料が完全に MOCVDチャンバ内に導入されなくなった後、 半 導体基板 11を MOCVDチャンバから取り出し、 第 1の実施形態と同様に、 強 誘電体キャパシタの加工以降の工程を行うことにより、 強誘電体キャパシタを有 する強誘電体メモリを完成させる。 Through these steps, a 111 film 25, a lower conductive compound film 25a, a BLT film 26, an upper conductive compound film 37a and a RuO 2 film 37 are formed. Then, after the Ru raw material is not completely introduced into the MOCVD chamber, the semiconductor substrate 11 is taken out of the MOCVD chamber, and the processes after the ferroelectric capacitor are processed as in the first embodiment. Complete a ferroelectric memory having a ferroelectric capacitor.
本実施形態においては、 BLT膜 26を形成する前に、 下部部導電性化合物膜 25 aを形成すると共に、 この下部導電性化合物膜 25 a内で R uと B iとの反 応を完了させている。 更に、 上部電極膜たる Ru〇2膜 37を形成する前には、 上部導電性化合物月奠 37 aを形成すると共に、 この上部導電性化合物膜 37 a内 で Ruとん B iとの反応を完了させている。 このため、 BLT膜 26を形成する 際には、 R u膜 25からの R uの B L T膜 26への拡散は下部導電性ィ匕合物膜 2 5 aにより防止され、 Ru〇2膜 37を形成する際には、 11〇2膜37からの Ruの BLT膜 26への拡散は上部導電性化合物膜 37 aにより防止される。 従 つて、 本実施形態によれば、 Ru膜 25を下部電極として用い、 RuOj 37 を上部電極として用いても、 従来のようにリーク電流が増大することはない。 ここで、 本願発明者が第 3の実施形態に係る製造方法の検証を行つた結果につ いて説明する。 この検証では、 S i基板 (ウェハ) 上に S i 02膜及び T i N膜 を形成し、 その上に強誘電体キャパシタを形成した。 強誘電体キャパシタの形成 条件は、 第 3の実施形態と同様である。 但し、 1¾ 11膜25の厚さは10011111程 度とし、 BLT膜 26の厚さは 100 nm程度とし、 Ru〇2膜 37の厚さは1 00 nm程度とした。 In the present embodiment, before forming the BLT film 26, the lower conductive compound film 25a is formed, and the reaction between Ru and Bi is completed in the lower conductive compound film 25a. ing. Further, before forming the Ru〇 2 film 37 serving as the upper electrode film, an upper conductive compound Moon 37a is formed, and the reaction with Ru and Bi in the upper conductive compound film 37a is performed. Has been completed. Therefore, when the BLT film 26 is formed, the diffusion of Ru from the Ru film 25 into the BLT film 26 is prevented by the lower conductive film 25 a, and the Ru 2 film 37 is formed. At the time of formation, diffusion of Ru from the 11 膜2 film 37 into the BLT film 26 is prevented by the upper conductive compound film 37a. Therefore, according to the present embodiment, even if the Ru film 25 is used as the lower electrode and the RuOj 37 is used as the upper electrode, the leak current does not increase as in the related art. Here, a description will be given of the result of the inventors of the present application verifying the manufacturing method according to the third embodiment. In this verification, a SiO 2 film and a Ti N film were formed on a Si substrate (wafer), and a ferroelectric capacitor was formed thereon. The conditions for forming the ferroelectric capacitor are the same as in the third embodiment. However, the thickness of 1¾ 11 film 25 is 100 1 1111 extent, the thickness of the BLT layer 26 is about 100 nm, the thickness of the Ru_〇 2 film 37 was set to about 1 00 nm.
そして、 Ru02膜 37を形成した後に、 尺11〇2膜37、 81^丁膜26及び R u膜 25を含む積層膜の膜厚方向の組成を S IMSで分析したところ、 R u O 2膜 37と BLT膜 26との間及び BLT膜 26と Ru膜 25との間に、 夫々 2 0 nm程度の厚さにわたって B i及び Ruが共存する領域が観察された。 この領 域が、 夫々上部導電性化合物膜 37 a、 下部導電性化合物膜 25 aである。 また 、 BLT膜 26中への Ruの拡散は観察されなかった。 Then, after forming the Ru0 2 layer 37, composition of the film thickness direction of the laminated film including a scale 11_Rei 2 film 37, 81 ^ Chomaku 26 and R u film 25 was analyzed by S IMS, R u O 2 Between the film 37 and the BLT film 26 and between the BLT film 26 and the Ru film 25, regions where Bi and Ru coexist over a thickness of about 20 nm were observed. This region is the upper conductive compound film 37a and the lower conductive compound film 25a, respectively. In addition, diffusion of Ru into the BLT film 26 was not observed.
更に、 フォトリソグラフィ技術により、 RuOj莫 37及び上部導電性化合物 膜 37 aに相当する厚さが 120 nmの部分をパターニングし、 500°Cの酸素 雰囲気中で 60分間のァ-ールを行った後に、 5 Vのリーク電流密度を測定した ところ、 当該電流密度は 1 X 1 0一6 A/cm2のオーダーであった。 また、 分極 特性を示す 1. 5 Vのスィッチ電荷量 Q s wは、 30 C/cni2程度であった 。 これらの結果、 第 2の実施形態によれば、 良好な特性の強誘電体キャパシタが 得られることが確認された。 Furthermore, by using photolithography technology, a portion with a thickness of 120 nm corresponding to the RuOj 37 and the upper conductive compound film 37a was patterned, and an annealing was performed for 60 minutes in an oxygen atmosphere at 500 ° C. Later, 5 V leakage current density was measured However, the current density was on the order of 1 × 10 16 A / cm 2 . Moreover, 1. 5 V switches amounts Q sw of showing a polarization characteristic was 30 C / cni 2 about. As a result, according to the second embodiment, it was confirmed that a ferroelectric capacitor having good characteristics could be obtained.
なお、 第 3の実施形態では、 図 7に示すように、 B i原料の供給を開始した直 後に、 R u原料の供給を停止しているが、 図 1 0に示すように、 B i原料の供給 量が定常状態に達してから Ru原料の供給を停止してもよい。 また、 図 7に示す ように、 Ru原料の供給を開始した直後に、 B i原料の供給を停止しているが、 図 1 0に示すように、 R u原料の供給量が定常状態に達してから B i原料の供給 を停止してもよい。 これらは、 第 1及び第 2の実施形態においても同様である。 また、 いずれの実施形態においても、 1 11膜の代ゎりに1 1102膜を用ぃても よく、 Ru〇2膜の代わりに Ru膜を用いてもよい。 更に、 電極膜の材料も特に 限定されるものではない。 In the third embodiment, as shown in FIG. 7, immediately after the supply of the Bi raw material is started, the supply of the Ru raw material is stopped. However, as shown in FIG. The supply of the Ru raw material may be stopped after the supply amount of Ru reaches a steady state. Further, as shown in FIG. 7, immediately after the supply of the Ru raw material was started, the supply of the Bi raw material was stopped, but as shown in FIG. 10, the supply amount of the Ru raw material reached a steady state. After that, the supply of the Bi raw material may be stopped. These are the same in the first and second embodiments. In any embodiment, 1 11 use Ite 1 110 2 film generations Wari membrane may be used Ru film instead of Ru_〇 2 film. Further, the material of the electrode film is not particularly limited.
更に、 B i層状系の強誘電体膜は B LT膜に限定されるものではなく、 例えば 、 BLT膜の代わりに、 SBT (S r B i 2T a 207) 膜、 SBN (S r B i 2 Nb2Og) 膜又は B I T (B i 4T i 3012) 膜等を形成してもよい。 これらの 膜を形成する場合には、 B L T膜を形成する場合の L a原料及び T i原料の代わ りに、 例えば、 S r原料及ぴ T a原料を供給するか、 3 原料及ぴ^^1)原料を供 給する力、 又は T i原料のみを供給すればよい。 Further, the ferroelectric film of B i layered system is not limited to the B LT film, for example, instead of BLT film, SBT (S r B i 2 T a 2 0 7) film, SBN (S r B i 2 Nb 2 O g) film or a BIT (B i 4 T i 3 0 12) may be formed film. When these films are formed, instead of the La raw material and the Ti raw material in forming the BLT film, for example, an Sr raw material and a Ta raw material may be supplied, or three raw materials and three raw materials may be used. 1) The power to supply the raw materials or only the Ti raw materials may be supplied.
次に、 本発明の実施に好適な MOCVD装置について説明する。 従来の MOC VD装置としては、 原料ごとに気化器が設けられ、 これらの気化器から原料ガス が各配管を介して混合器に供給され、 この混合器内で各原料ガスが混合された後 、 シャワーヘッドからチャンバ内に供給されるものがある。 これに対し、 近時、 1つの気化器内で複数の原料が気ィ匕して原料ガスが生成すると共に、 これら力 S混 合してシャワーへッドからチャンバ内に供給される MOCVD装置が開発されて レ、る。  Next, a MOCVD apparatus suitable for implementing the present invention will be described. In the conventional MOC VD apparatus, a vaporizer is provided for each raw material, and raw gas is supplied from these vaporizers to a mixer via each pipe, and after each raw material gas is mixed in the mixer, Some are supplied from the shower head into the chamber. On the other hand, recently, a MOCVD apparatus in which a plurality of raw materials are degassed in one vaporizer to generate a raw material gas, and these powers are mixed and supplied from a shower head into a chamber. It has been developed.
従来の MO C VD装置では、 気化器内で気ィ匕してからチヤンバ内に供給される までの配管が長く必要であり、 また、 原料ガス間の温度差により、 他の原料ガス の温度の影響を受けやすいため、 原料ガスがチャンバ内に供給される前に、 配管 等の内部に粒子が発生することがある。 これに対し、 近時開発された MO C VD 装置では、 このような粒子の発生が抑制される。 In the conventional MOC VD device, a long pipe is required from when the gas is vaporized in the vaporizer to when it is supplied into the chamber. Before feed gas is supplied into the chamber, And the like may generate particles inside. In contrast, the recently developed MOC VD device suppresses the generation of such particles.
特に、 本発明では、 複数の原料ガスを同時にチャンバ内に供給する工程が多く 、 また、 これらの供給のオン/オフの切り替えを適宜行う必要があるので、 近時 開発された MO C VD装置による粒子の発生の抑制という効果が顕著である。 ま た、 近時開発された MO C VD装置では、 気化器が 1台で済むため、 多種の原科 ガスを用いる場合には、 気化器の数の低減によるコストの低減も可能である。 また、 このような気化器を用いるに当たっては、 B i原料 (B iの有機化合物 )、 L a原料 (L aの有機化合物) 及び T i原料 (T iの有機化合物) 等の B i 層状系強誘電体膜の原料の供給系と、 R u原料 (金属元素の有機化合物) の供給 系とが接続されたものを用いることが望ましい。  In particular, in the present invention, there are many steps of simultaneously supplying a plurality of source gases into the chamber, and it is necessary to appropriately switch on / off of the supply of these gases, so that a recently developed MOC VD apparatus is used. The effect of suppressing generation of particles is remarkable. In addition, the recently developed MOC VD device requires only one vaporizer, so when using many types of raw gas, the cost can be reduced by reducing the number of vaporizers. In using such a vaporizer, a Bi layered system such as a Bi raw material (organic compound of Bi), a La raw material (organic compound of La), and a Ti raw material (organic compound of Ti) is used. It is desirable to use a ferroelectric film raw material supply system connected to a Ru raw material (organic compound of a metal element) supply system.
なお、 いずれの実施形態においても、 MO C VDチャンバ内へのガスの供給が 開始されてから、 MO C VDチャンバ内での成膜が終了するまでの間、 シャワー へッドの温度及び基板温度を一定に保持することが望ましい。 これらの を一 定に保持することにより、 より安定して各膜を成膜することが可能となる。 産業上の利用可能性  In any of the embodiments, the temperature of the shower head and the temperature of the substrate are changed from the start of gas supply into the MOC VD chamber to the end of film formation in the MOC VD chamber. Is preferably kept constant. By keeping these constant, it becomes possible to form each film more stably. Industrial applicability
以上詳述したように、 本発明によ ば、 電極膜の形成と強誘電体膜の形成とを 1つのチャンバ内で連続して行うことができる。 このため、 製造時間を短縮する と共に、 製造設備のコストを低減することができる。 また、 ウェハの搬送回数が 低減されるため、 搬送中に生じ得るコンタミネーシヨンが抑制され、 高い信頼性 を得ることができる。 更に、 導電性化合物膜の形成により、 強誘電体膜中でのリ ーク電流を大幅に低減することができる。 Ru原料 Ru(EtCp), (Ru(C5H4C2H5)2: ビス—ェチル—シクロ 。ンタシ '、ェ二ル け二ゥム)As described in detail above, according to the present invention, the formation of the electrode film and the formation of the ferroelectric film can be performed continuously in one chamber. For this reason, the manufacturing time can be reduced, and the cost of the manufacturing equipment can be reduced. Further, since the number of times of wafer transfer is reduced, contamination that may occur during transfer is suppressed, and high reliability can be obtained. Further, by forming the conductive compound film, a leak current in the ferroelectric film can be significantly reduced. Ru raw material Ru (EtCp), (Ru (C 5 H 4 C 2 H 5 ) 2 : Bis-ethyl-cyclo.
B i原料 Bi(Ph)3 (Bi(C6H5)3: トリフヱニル—ビスマス) Bi raw material Bi (Ph) 3 (Bi (C 6 H 5 ) 3 : trifenyl-bismuth)
L a原料 La (dibm)3 (La(C8H1502)3: ト!)ス-シ、、イソフ リルメタナ―ト -ランタン)L a raw material La (dibm) 3 (La ( C 8 H 15 0 2) 3:! Door) S - Shea ,, isophthalic Rirumetana - door - lantern)
T i原料 Ti(0iPr)4 (Ti[0CH(CH3)2]4:テトラ-イソフ°口ホ°キシ-チタニウム) Ti raw material Ti (0iPr) 4 (Ti [0CH (CH 3 ) 2 ] 4 : tetra-isofuran oxy-titanium)

Claims

請求の範囲 The scope of the claims
1 . B i (ビスマス) 層状系強誘電体膜を備えた強誘電体キャパシタの製造方 法は、 1. The method for manufacturing a ferroelectric capacitor with a Bi (bismuth) layered ferroelectric film is as follows.
C VDチャンパ内に、 第 1の金属元素を含有するガスを導入して、 前記第 1の 金属元素を含有する下部電極膜を形成する工程と、  A step of introducing a gas containing a first metal element into the C VD champer to form a lower electrode film containing the first metal element;
前記 C VDチャンバ内に、 前記第 1の金属元素を含有するガスを導入しつづけ ながら、 更に B i (ビスマス) 及び O (酸素) を含有するガスを導入して、 前記 下部電極膜上に前記第 1の金属元素及び B i (ビスマス) を含有する第 1の導電 性化合物膜を形成する工程と、  While continuously introducing the gas containing the first metal element into the CVD chamber, a gas containing Bi (bismuth) and O (oxygen) is further introduced, and the gas on the lower electrode film is formed on the lower electrode film. Forming a first conductive compound film containing a first metal element and Bi (bismuth);
前記 C V Dチャンバ内への前記第 1の金属元素の導入を停止する工程と、 前記 CVDチャンバ内に、 B i (ビスマス) 及び O (酸素) を含有するガスを 導入しつづけながら、 更に前記 B i (ビスマス) 層状系強誘電体膜を構成する金 属元素のうち B i (ビスマス) を除く強誘電体膜用金属元素を含有するガスを導 入して、 前記第 1の導電性化合物膜上に前記 B i (ビスマス) 層状系強誘電体膜 を形成する工程と、  Stopping the introduction of the first metal element into the CVD chamber; and continuously introducing a gas containing Bi (bismuth) and O (oxygen) into the CVD chamber. (Bismuth) A gas containing a metal element for a ferroelectric film other than Bi (bismuth) among the metal elements constituting the layered ferroelectric film is introduced into the first conductive compound film. Forming the B i (bismuth) layered ferroelectric film in
前記 C VDチャンバ内への B i (ビスマス) 及び前記強誘電体膜用金属元素の 導入を停止する工程と、  Stopping the introduction of Bi (bismuth) and the metal element for the ferroelectric film into the CVD chamber;
前記 B i (ビスマス) 層状系強誘電体膜上に上部電極膜を形成する工程と、 を有する。  Forming an upper electrode film on the Bi (bismuth) layered ferroelectric film.
2. B i (ビスマス) 層状系強誘電体膜を備えた強誘電体キャパシタの製造方 法は、  2. The method of manufacturing a ferroelectric capacitor with a Bi (bismuth) layered ferroelectric film is as follows.
下部電極膜を形成する工程と、  Forming a lower electrode film;
前記 C VDチャンバ内に、 B i (ビスマス)、 前記 B i (ビスマス) 層状系強 誘電体膜を構成する金属元素のうち B i (ビスマス) を除く強誘電体膜用金属元 素及び O (酸素) を含有するガスを導入して、 前記下部電極膜上に前記 B i (ビ スマス) 層状系強誘電体膜を形成する工程と、  In the CVD chamber, B i (bismuth), a metal element for a ferroelectric film excluding B i (bismuth) among the metal elements constituting the layered ferroelectric film, and O ( Introducing a gas containing oxygen) to form the Bi (bismuth) layered ferroelectric film on the lower electrode film;
前記 C V Dチヤンバ内への前記強誘電体膜用金属元素の導入を停止する工程と 前記 C VDチャンバ内に、 B i (ビスマス) 及び O (酸素) を含有するガスを 導入しつづけながら、 第 2の金属元素を含有するガスを導入して、 前記 B i (ビ スマス) 層状系強誘電体膜上に前記第 2の金属元素及び B i (ビスマス) を含有 する第 2の導電性化合物膜を形成する工程と、 Stopping the introduction of the metal element for the ferroelectric film into the CVD chamber; A gas containing a second metal element is introduced into the CVD chamber while a gas containing Bi (bismuth) and O (oxygen) is continuously introduced into the CVD chamber. Forming a second conductive compound film containing the second metal element and Bi (bismuth) on the ferroelectric film;
前記 C VDチャンパ内への B i (ビスマス) の導入を停止する工程と、 前記 C VDチャンバ内に、 前記第 2の金属元素を含有するガスを導入しつづけ て、 前記第 2の導電性化合物膜上に前記第 2の金属元素を含有する上部電極膜を 形成する工程と、  Stopping the introduction of Bi (bismuth) into the CVD chamber; and continuously introducing a gas containing the second metal element into the CVD chamber; Forming an upper electrode film containing the second metal element on the film;
を有する。  Having.
3 . 請求項 1に記載の強誘電体キャパシタの製造方法において、  3. The method for manufacturing a ferroelectric capacitor according to claim 1,
前記 C VDチャンパ内への B i (ビスマス) 及び前記強誘電体膜用金属元素の 導入を停止する工程は、  The step of stopping the introduction of Bi (bismuth) and the metal element for the ferroelectric film into the CVD champer includes:
前記 C V Dチヤンパ内への前記強誘電体膜用金属元素の導入を停止する工程と 前記 C VDチャンバ内に、 B i (ビスマス) 及び O (酸素) を含有するガスを 導入しつづけながら、 第 2の金属元素を含有するガスを導入して、 前記 B i (ビ スマス) 層状系強誘電体膜上に前記第 2の金属元素及び B i (ビスマス) を含有 する第 2の導電性化合物膜を形成する工程と、  A step of stopping the introduction of the metal element for the ferroelectric film into the CVD chamber, and a step of continuously introducing a gas containing Bi (bismuth) and O (oxygen) into the CVD chamber. A gas containing the second metal element is introduced to form a second conductive compound film containing the second metal element and Bi (bismuth) on the Bi (bismuth) layered ferroelectric film. Forming,
前記 C VDチャンパ内への B i (ビスマス) の導入を停止する工程と、 を有し、  Stopping the introduction of Bi (bismuth) into the CVD champer;
前記上部電極膜を形成する工程は、  The step of forming the upper electrode film,
前記 C VDチャンバ内に、 前記第 2の金属元素を含有するガスを導入しつづけ て、 前記第 2の導電性化合物膜上に前記第 2の金属元素を含有する上部電極膜を 形成する工程を有する。  Forming a top electrode film containing the second metal element on the second conductive compound film by continuously introducing a gas containing the second metal element into the CVD chamber; Have.
4. 請求項 1に記載の強誘電体キャパシタの製造方法において、  4. The method for manufacturing a ferroelectric capacitor according to claim 1,
前記第 1の金属元素は、 R u (ルテニウム) である。  The first metal element is Ru (ruthenium).
5 . 請求項 2に記載の強誘電体キャパシタの製造方法において、  5. The method for manufacturing a ferroelectric capacitor according to claim 2,
前記第 2の金属元素は、 R u (ルテニウム) である。  The second metal element is Ru (ruthenium).
6 . 請求項 1に記載の強誘電体キャパシタの製造方法にお!/、て、 前記 C V Dチャンバ内への前記第 1の金属元素の導入を停止する工程を、 B i (ビスマス) 及び O (酸素) を含有するガスの供給量が定常状態に達した後に行 う。 6. The method for producing a ferroelectric capacitor according to claim 1! The step of stopping the introduction of the first metal element into the CVD chamber is performed after a supply amount of a gas containing Bi (bismuth) and O (oxygen) reaches a steady state.
7 . 請求項 1に記載の強誘電体キャパシタの製造方去において、  7. In the method of manufacturing a ferroelectric capacitor according to claim 1,
前記 C V Dチャンバ内への前記第 1の金属元素の導入を停止する工程を、 B i (ビスマス) 及び O (酸素) を含有するガスの供給量が定常状態に達する前に行 う。  The step of stopping the introduction of the first metal element into the CVD chamber is performed before the supply amount of the gas containing Bi (bismuth) and O (oxygen) reaches a steady state.
8. 請求項 2に記載の強誘電体キャパシタの製造方法にお!/、て、  8. The method for manufacturing a ferroelectric capacitor according to claim 2!
前記 C V Dチャンバ内への B i (ビスマス) の導入を停止する工程を、 前記第 2の金属元素を含有するガスの供給量が定常状態に達した後に行う。  The step of stopping the introduction of Bi (bismuth) into the CVD chamber is performed after the supply amount of the gas containing the second metal element reaches a steady state.
9 . 請求項 2に記載の強誘電体キャパシタの製造方法にぉレ、て、  9. The method for manufacturing a ferroelectric capacitor according to claim 2,
前記 C V Dチャンバ内への B i (ビスマス) の導入を停止する工程を、 前記第 2の金属元素を含有するガスの供給量が定常状態に達する前に行う。  The step of stopping the introduction of Bi (bismuth) into the CVD chamber is performed before the supply amount of the gas containing the second metal element reaches a steady state.
1 0 . 請求項 4に記載の強誘電体キャパシタの製造方法において、  10. The method of manufacturing a ferroelectric capacitor according to claim 4,
前記下部電極膜は、 R u (ルテニウム) 膜又は R u〇2 (酸化ルテニウム) 膜 である。 The lower electrode film, R u (ruthenium) layer or R U_〇 2 (oxide ruthenium) is a membrane.
1 1 . 請求項 5に記載の強誘電体キャパシタの製造方法  11. The method for manufacturing a ferroelectric capacitor according to claim 5.
前記上部電極膜は、 R u (ルテニウム) 膜又は R u〇2 (酸化ルテニウム) 膜 である。 The upper electrode film, R u (ruthenium) layer or R U_〇 2 (ruthenium oxide) is a membrane.
1 2 . 請求項 4に記載の強誘電体キャパシタの製造方法において、  12. The method of manufacturing a ferroelectric capacitor according to claim 4,
前記下部導電性ィ匕合物膜は、 R u (ルテニウム)、 B i (ビスマス) 及ぴ O ( 酸素) 力らなる。 '  The lower conductive film is composed of Ru (ruthenium), Bi (bismuth) and O (oxygen). '
1 3 . 請求項 5に記載の強誘電体キャパシタの製造方法にぉレ、て、  13. The method for producing a ferroelectric capacitor according to claim 5,
前記上部導電性化合物膜は、 R u (ルテニウム)、 B i (ビスマス) 及び O ( 酸素) からなる。  The upper conductive compound film is composed of Ru (ruthenium), Bi (bismuth), and O (oxygen).
1 4 . 請求項 1に記載の強誘電体キャパシタの製造方法にぉレ、て、  14. The method for manufacturing a ferroelectric capacitor according to claim 1, wherein
B i (ビスマス) の有機化合物、 前記強誘電体膜用金属元素及び前記金属元素 の有機化合物を同一の気化器を用いて気化する。  The organic compound of Bi (bismuth), the metal element for the ferroelectric film, and the organic compound of the metal element are vaporized using the same vaporizer.
1 5 . 請求項 2に記載の強誘電体キャパシタの製造方法にぉレ、て、 B i (ビスマス) の有機化合物、 前記強誘電体膜用金属元素及び前記金属元素 の有機ィ匕合物を同一の気化器を用いて気化する。 15. The method for manufacturing a ferroelectric capacitor according to claim 2, wherein The organic compound of Bi (bismuth), the metal element for the ferroelectric film, and the organic compound of the metal element are vaporized using the same vaporizer.
1 6 . 請求項 1 4に記載の強誘電体キャパシタの製造方法にぉ 、て、  16. A method for manufacturing a ferroelectric capacitor according to claim 14, wherein
前記気化器には、 B i (ビスマス) の有機化合物及び前記強誘電体膜用金属元 素の供給手段と、 前記金属元素の有機化合物の供給手段とが接続されている。 A supply means for supplying an organic compound of Bi (bismuth) and the metal element for the ferroelectric film, and a supply means for supplying the organic compound of the metal element are connected to the vaporizer.
1 7 . 請求項 1 5に記載の強誘電体キャパシタの製造方法にぉレ、て、 17. The method for manufacturing a ferroelectric capacitor according to claim 15, wherein
前記気化器には、 B i (ビスマス) の有機化合物及び前記強誘電体膜用金属元 素の供給手段と、 前記金属元素の有機化合物の供給手段とが接続されている。 A supply means for supplying an organic compound of Bi (bismuth) and the metal element for the ferroelectric film, and a supply means for supplying the organic compound of the metal element are connected to the vaporizer.
1 8 . 請求項 1に記載の強誘電体キャパシタの製造方法にぉレ、て、 18. The method for manufacturing a ferroelectric capacitor according to claim 1, wherein
前記 C VDチャンパ内へのガスの供給を開始してから、 前記 C VDチャンバ内 での成膜を終了するまでの間、 前記 C VDチャンバ内のシャワーへッドの温度及 び基板温度を一定に保持する 0 The temperature of the shower head and the substrate temperature in the CVD chamber are kept constant from the start of gas supply into the CVD chamber to the end of film formation in the CVD chamber. Keep in 0
1 9 . 請求項 2に記載の強誘電体キャパシタの製造方法にお!/、て、  1 9. The method for manufacturing a ferroelectric capacitor according to claim 2! /,hand,
前記 C VDチャンバ内へのガスの供給を開始してから、 前記 C VDチャンバ内 での成膜を終了するまでの間、 前記 C VDチャンバ内のシャワーへッドの温度及 び基板温度を一定に保持する。  From the start of gas supply into the CVD chamber to the end of film formation in the CVD chamber, the temperature of the showerhead and the substrate in the CVD chamber are kept constant. To hold.
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WO1993021637A1 (en) * 1992-04-13 1993-10-28 Ceram, Inc. Multilayer electrodes for ferroelectric devices
JPH088403A (en) * 1994-06-17 1996-01-12 Sharp Corp Substrate covered with ferroelectric crystal thin film ferroelectric thin film element including the same, and method of manufacturing the ferroelectric thin film element
JPH09241849A (en) * 1996-03-11 1997-09-16 Toshiba Corp Apparatus for production of oxide thin film and its production
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