JP2000174228A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit comprising a capacitor wherein scaling of film thickness is made easy, and degradation in characteristics under reduction action of hydrogen, etc., is suppressed. SOLUTION: Related to a semiconductor integrated circuit comprising a capacitor C1 formed on a substrate 10 covered with a silicon oxide film, the capacitor C1 comprises a lower Pt electrode 12 formed on the substrate 10 through a Ti film 11, a first PZT film 13 formed and crystallized over it, a second PZT film 14 formed and crystallized over it, and an upper Pt electrode 15 formed over it. The first PZT film 13 is crystallized containing Pt which is diffused from the Pt electrode 12 while the second PZT film 14 has little diffusion of Pt. Due to the second PZT film 14, and excellent polarity characteristics with no leakage is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit including a thin-film capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a nonvolatile semiconductor memory using a ferroelectric capacitor (hereinafter referred to as a ferroelectric memory).
It has been known. A ferroelectric capacitor is formed by stacking a lower electrode, a ferroelectric film, and an upper electrode on a semiconductor substrate covered with an insulating film. Typically, a metal oxide ferroelectric such as lead zirconate titanate (PZT: PbZr _1-x Ti _x O ₃ ) having a perovskite crystal structure is used as the ferroelectric film. When a PZT film is used,
Pt electrodes are typically used for the upper and lower electrodes.

Since such a ferroelectric memory can hold data without a battery and can operate at high speed, application to a contactless card such as RF-ID (Radio Frequency Identification) is beginning to be started. Also, SR
There are great expectations for replacement with AM, DRAM, EEPROM, etc., and for mixed logic. Pt / PZT described above
A basic manufacturing process of a ferroelectric capacitor having a / Pt structure includes a process of sequentially depositing a lower Pt electrode and a PZT film on a substrate, a process of performing a heat treatment for crystallization of the deposited PZT film, and a process of performing a PZT film. And a step of forming an upper Pt electrode thereon.

[0004]

It has been reported that the polarization characteristics of a ferroelectric capacitor having a Pt / PZT / Pt structure are deteriorated by heat treatment in a hydrogen atmosphere. This is because many oxygen vacancies are introduced into the PZT film by the hydrogen reducing action and the catalytic action of the Pt electrode. Therefore, the crystallization treatment of the PZT film described above cannot be performed in a hydrogen atmosphere, but is preferably performed in, for example, an oxygen atmosphere.

On the other hand, according to recent research by the present inventors, when a PZT film is deposited on a lower Pt electrode and crystallization is performed, the PZT film is considerably deeper from the interface between the PZT film and the lower Pt electrode. It became clear that Pt diffused to the range and a layer showing conductivity was formed. This is because the PZT film at the time of deposition is in an amorphous state, and the diffusion reaction is fast. When the above-described conductive layer is formed in the PZT film, the conductive layer loses the function of storing fixed charges. In particular, when the thickness of the PZT film is reduced to 100 nm or less, the PZT film becomes almost a conductive layer, and it is difficult to obtain spontaneous polarization characteristics. Therefore, it is difficult to scale the thickness of the ferroelectric film.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a semiconductor integrated circuit having a capacitor which can easily scale the thickness of a dielectric film and has excellent polarization characteristics or charge retention characteristics with little leakage. It is intended to provide a circuit and a method for manufacturing the circuit.

[0007]

A first semiconductor integrated circuit according to the present invention has a capacitor, and the capacitor comprises:
A lower electrode, a first metal oxide dielectric film formed on the lower electrode and crystallized, and a second metal formed on the first metal oxide dielectric film and crystallized It has an oxide dielectric film and an upper electrode formed on the second metal oxide dielectric film.

In the first semiconductor integrated circuit, the first and second metal oxide dielectric films are, for example, ferroelectric films. Further, it is assumed that the first metal oxide dielectric film is crystallized including the constituent elements of the lower electrode by diffusion from the lower electrode. In the first semiconductor integrated circuit, the first and second metal oxide dielectric films have a relative dielectric constant of 50, for example.
The above is a high dielectric film.

A second semiconductor integrated circuit according to the present invention has a capacitor, the capacitor comprising: a lower electrode; a first metal oxide dielectric film formed on the lower electrode and crystallized; A second metal oxide dielectric film formed on the first metal oxide dielectric film and crystallized; and a second metal oxide dielectric film formed on the second metal oxide dielectric film and crystallized. And a third metal oxide dielectric film and an upper electrode formed on the third metal oxide dielectric film.

In the second semiconductor integrated circuit, the first to third metal oxide dielectric films are, for example, ferroelectric films. Also, the first metal oxide dielectric film is crystallized to include the constituent elements of the lower electrode by diffusion from the lower electrode, and the third metal oxide dielectric film is formed by diffusion of the upper electrode by diffusion from the upper electrode. It shall be crystallized including the constituent elements. In the second semiconductor integrated circuit, the first to third metal oxide dielectric films are, for example, high dielectric films having a relative dielectric constant of 50 or more. In the first or second semiconductor integrated circuit, the metal oxide dielectric film preferably has a perovskite crystal structure.

A first method of manufacturing a semiconductor integrated circuit according to the present invention includes a step of depositing a first metal oxide dielectric film on a lower electrode and crystallizing the first metal oxide film by heat treatment. Depositing a second metal oxide dielectric film on the first metal oxide dielectric film, and crystallizing the second metal oxide dielectric film by heat treatment; Forming an upper electrode on the material dielectric film. In the first manufacturing method, the first and second metal oxide dielectric films are, for example, ferroelectric films.
Further, the first metal oxide dielectric film is to be crystallized including the constituent elements of the lower electrode by diffusion from the lower electrode. In the first manufacturing method, the first and second metal oxide dielectric films are, for example, high dielectric films having a relative dielectric constant of 50 or more.

A second method of manufacturing a semiconductor integrated circuit according to the present invention includes a step of depositing a first metal oxide dielectric film on a lower electrode and crystallizing the first metal oxide film by heat treatment. Depositing a second metal oxide dielectric film on the first metal oxide dielectric film, and crystallizing the second metal oxide dielectric film by heat treatment; Depositing a third metal oxide dielectric film on an object dielectric film, forming an upper electrode on the third metal oxide dielectric film, and performing a heat treatment on the third metal oxide dielectric film. Crystallizing the oxide dielectric film. In the second manufacturing method, the first to third metal oxide dielectric films are, for example, ferroelectric films. In this case, the first metal oxide dielectric film is crystallized including the constituent elements of the lower electrode by diffusion from the lower electrode, and the third metal oxide dielectric film is formed by diffusion from the upper electrode. It is assumed that it is crystallized including the constituent elements of the electrode. In the second manufacturing method, the first to third metal oxide dielectric films are, for example, high dielectric films having a relative dielectric constant of 50 or more.

In the first or second manufacturing method, preferably, the metal oxide dielectric film has a perovskite crystal structure. In the first or second manufacturing method, preferably, the first metal oxide dielectric film is formed by repeating a plurality of steps of depositing a metal oxide dielectric film having a predetermined thickness and heat treatment for crystallization. It is formed as a plurality of layers.

In the first semiconductor integrated circuit according to the present invention, the dielectric film of the capacitor has a two-layer structure of the first metal oxide dielectric film and the second metal oxide dielectric film from the lower electrode side. Is done. The first metal oxide film is crystallized after being deposited on the lower electrode. With such a laminated dielectric film structure, the constituent elements of the lower electrode are diffused into the first metal oxide film in the crystallization step of the first metal oxide dielectric film, and the crystallization is performed including the constituent elements. Is done. The constituent elements of the lower electrode taken into the first metal oxide dielectric film lose their degrees of freedom due to crystallization of the first metal oxide dielectric film, or have a small diffusion coefficient. Even in the step of crystallizing the second metal oxide dielectric film deposited thereon, it hardly diffuses into the second metal oxide dielectric film. In addition, if the crystallization of the second metal oxide dielectric film is performed before the deposition of the upper electrode, there is no diffusion of the constituent elements from the upper electrode to the second metal oxide dielectric film.

Therefore, in the case of a ferroelectric capacitor in which the first and second metal oxide films are ferroelectric films, the second metal oxide film exhibits good ferroelectric characteristics without leakage, and exhibits spontaneous polarization. Is obtained. Further, since the constituent elements of the lower electrode are not diffused in the second metal oxide dielectric film, it is easy to reduce the thickness of the second metal oxide dielectric film. Furthermore, the first metal oxide dielectric film acts as a barrier to the second metal oxide dielectric film against a reducing gas containing hydrogen or the like, so that the characteristics of the ferroelectric capacitor due to the reducing gas are reduced. Deterioration is also suppressed. Even in the case of a high-dielectric capacitor in which the first and second metal oxide films are high-dielectric films, excellent capacitor characteristics with less leakage can be obtained for the same reason. Will be possible.

In the second semiconductor integrated circuit according to the present invention, a third metal oxide dielectric film is further inserted between the above-mentioned second metal oxide dielectric film and the upper electrode. In this case, if the third metal oxide dielectric film is crystallized after depositing the upper electrode thereon, the third metal oxide dielectric film contains the constituent elements of the upper electrode similarly to the first metal oxide dielectric film. Is crystallized. Therefore, the third metal oxide dielectric film serves as a barrier against a reducing action by hydrogen or the like from above the second metal oxide dielectric film. Thereby, the characteristic deterioration of the ferroelectric capacitor due to the reducing gas is more effectively suppressed.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 shows a structure of a ferroelectric capacitor C1 in an embodiment in which the present invention is applied to a ferroelectric memory. The substrate 10 is a silicon substrate covered with an insulating film such as a silicon oxide film. On this substrate 10, as a lower electrode, T
A Pt electrode 12 is formed via an i film 11. Ti
The film 11 is provided for improving the adhesion between the Pt electrode 12 and a silicon oxide film or the like. On the Pt electrode 12, a first PZT film 13 and a second PZT film 14 are laminated, and on the second PZT film 14, a Pt electrode 15 is formed as an upper electrode.

In this embodiment, the ferroelectric capacitor C1 is patterned as shown and is covered with a protective film 16 for reducing gas. In particular, the protective film 16
The side surfaces where the interfaces between the PZT films 13 and 14 and the Pt electrodes 12 and 15 are terminated are covered to prevent the intrusion of the reducing gas into these interfaces.

The manufacturing process of the ferroelectric capacitor C1 according to this embodiment will be specifically described with reference to FIG.
As shown in FIG. 2A, a Ti film 11 of about 20 nm and a Pt electrode 12 of about 200 nm are sequentially deposited on the substrate 10 by sputtering. In this state, heat treatment is preferably performed at about 500 ° C. in an oxygen atmosphere. Next, a first PZT film 13 is deposited on the Pt electrode 12 by a sol-gel method or a sputtering method. The first PZT film 13 has a thickness of 5 to 5
The thickness is set to 0 nm, more preferably 10 to 20 nm.
At this stage, the first PZT film 13 is in an amorphous state.

Thereafter, in an oxygen atmosphere at 650-750 ° C.
Is performed to crystallize the first PZT film 13.
In this crystallization step, the Pt electrode 12 and the first PZT film 1
3, a diffusion reaction occurs, and the first PZT film 13 is crystallized including Pt. For this reason, the first PZT film 13 becomes conductive.

Next, as shown in FIG. 2B, the first P
A second PZT film 14 is deposited on the ZT film 13 by a sol-gel method or a sputter method. The thickness of the second PZT film 14 is 300 to 2000 nm. Then, heat treatment is performed at 650 to 750 ° C. in an oxygen atmosphere, and the second PZT
The film 13 is crystallized. In this crystallization step, it has been confirmed that the second PZT film 14 hardly diffuses Pt. This is because the first PZT film 13 has been crystallized at this stage, and the P
t is because the degree of freedom is small. The crystallized first
From the lower Pt electrode 12 to the second PZ
This is because Pt diffusion into the T film 14 is also prevented.

Thereafter, as shown in FIG. 2C, an upper Pt electrode 15 is deposited on the second PZT film 14 by sputtering. Thereafter, although not shown, the laminated structure up to this point is patterned to form a ferroelectric capacitor C1. In a specific patterning step, first, the upper Pt electrode 15, the second PZT film 14, and the first PZT film 13 are sequentially etched using a predetermined resist pattern.
For this etching, an RIE method using an Ar / Cl ₂ / CF ₄ gas is applied, and over-etching is performed so as to slightly remove the surface of the lower Pt electrode 12. Then, after removing the resist pattern to form the protective film 16, a resist pattern covering a wider area than the previous resist pattern is formed again, and the protective film 16 and the lower Pt electrode 12 are etched. As the protective film 16, SixNy, TiOx, Tix capable of blocking intrusion of hydrogen or the like can be used.
SiyNz or the like is used.

The memory cells of the ferroelectric memory according to this embodiment are, for example, ferroelectric capacitors C1 and M
FIG. 3 shows an example of the memory cell structure in the case where the memory cell is formed as a one-transistor / one-capacitor structure using OS transistors. As shown, a MOS transistor 3 is formed on a substrate 10 in a region defined by an element isolation insulating film 2 of a silicon substrate 1, and the MOS transistor 3 is covered with an interlayer insulating film 4 such as a silicon oxide film.

The interlayer insulating film 4 has a MOS transistor 3
The contact plug 7 for one of the diffusion layers is buried. A bit line 5 connected to the other diffusion layer of the MOS transistor is buried in the interlayer insulating film 4. On the interlayer insulating film 4, the above-described ferroelectric capacitor C1 is formed.
Is formed. In the example shown, the lower Pt electrode 12 is connected to the MOS transistor via the contact plug 7,
This connection node becomes a memory node. Capacitor C1
On top of this, an interlayer insulating film 17 is further formed. On the interlayer insulating film 17, a plate wiring 18 connected to the upper Pt electrode 15 of the capacitor C1 is formed.

FIG. 4 shows the polarization characteristics of the ferroelectric capacitor C1 according to this embodiment in comparison with the ferroelectric capacitor of the prior art. In the conventional ferroelectric capacitor, one layer of PZT film is formed on a lower Pt electrode, which is crystallized by a heat treatment, and then an upper Pt electrode is formed thereon. The spontaneous polarization in the conventional example is approximately
While 2Pr1 = 10 μC / cm ² , the amount of spontaneous polarization in this embodiment is approximately 2Pr2 = 30 μC / cm ^2.
cm ² have been obtained.

The reason why the above-described embodiment can obtain such a large spontaneous polarization is that the PZT film is formed by a two-layer structure and the first PZT film 13 is formed by the second PZT film 1.
4 that Pt is diffused from the lower Pt electrode 12 into the first PZT film 13 by crystallization prior to the formation of the Pt 4, and that Pt is not diffused into the second PZT film 14 as a result, Is the result of This is clear from the results of the SIMS analysis.

FIGS. 5 and 6 show the Pt distribution and the Pb distribution obtained by performing SIMS analysis on the ferroelectric capacitor C1 according to this embodiment and the ferroelectric capacitor of the conventional example, respectively. In the case of the conventional example, as shown in FIG. 6, deep Pt diffusion from the lower Pt electrode is recognized in the PZT film. The portion of the Pt diffusion layer exhibits conductivity as described above, so that good polarization characteristics cannot be obtained.
On the other hand, in this embodiment, as shown in FIG.
Although Pt is diffused in the first PZT film 13, Pt is hardly diffused in the second PZT film 14.

The first PZT film 13 in which Pt is diffused
Serves as a barrier against invasion of reducing elements such as hydrogen from the lower Pt electrode 12 side to the second PZT film 14. Therefore, the reduction action of the second PZT film 14 by hydrogen or the like during or after the manufacturing process is suppressed, and the deterioration of the polarization characteristics is also suppressed.

Second Embodiment FIG. 7 shows a structure of a ferroelectric capacitor C2 according to a second embodiment in which the present invention is applied to a ferroelectric memory, corresponding to FIG. The substrate 10 is a silicon substrate covered with an insulating film such as a silicon oxide film. A Pt electrode 12 is formed on the substrate 10 via a Ti film 11 as a lower electrode.
Are formed. The Ti film 11 is provided for improving the adhesion between the Pt electrode 12 and the silicon oxide film or the like. On the Pt electrode 12, a first PZT film 13, a second PZT film 14, and a third PZT film 21 are laminated.
A Pt electrode 15 is formed on the PZT film 21 as an upper electrode.

In this embodiment, the ferroelectric capacitor C2 is patterned as shown, and is covered with a protective film 16 for reducing gas. In particular, the protective film 16
The interface between the PZT films 13 and 14 and the Pt electrodes 12 and 15 is covered with the exposed side surfaces to prevent the intrusion of the reducing gas into these interfaces.

FIG. 8 shows a manufacturing process of the ferroelectric capacitor C2 according to this embodiment, specifically corresponding to FIG. As shown in FIG. 8A, on the substrate 10,
Ti film of about 20 nm, Pt electrode 12 of about 200 nm
Are sequentially deposited by sputtering. In this state, heat treatment is preferably performed at about 500 ° C. in an oxygen atmosphere. Next, a first PZT film 13 is deposited on the Pt electrode 12 by a sol-gel method or a sputtering method. First PZT film 13
Has a thickness of 5 to 50 nm, more preferably 10 to 20 nm. At this stage, the first PZT film 13 is in an amorphous state.

Thereafter, in an oxygen atmosphere, at 650 to 750 ° C.
Is performed to crystallize the first PZT film 13.
In this crystallization step, the Pt electrode 12 and the first PZT film 1
3, a diffusion reaction occurs, and the first PZT film 13 is crystallized including Pt.

Next, as shown in FIG. 8B, the first P
A second PZT film 14 is deposited on the ZT film 13 by a sol-gel method or a sputter method. The thickness of the second PZT film 14 is 300 to 2000 nm. Then, heat treatment is performed at 650 to 750 ° C. in an oxygen atmosphere, and the second PZT
The film 13 is crystallized. In this crystallization step, the second PZT film 14 hardly diffuses Pt.

Thereafter, as shown in FIG. 8C, a third PZT film 14 is formed on the second PZT film 14 by a sol-gel method or a sputtering method.
Of the PZT film 21 is 5 to 50 nm, more preferably 10 to 50 nm.
Then, the upper Pt electrode 15 is deposited by sputtering. Then, in an oxygen atmosphere, 65
Heat treatment is performed at 0 to 750 ° C. to crystallize the third PZT film 21. In this crystallization step, Pt diffuses from the upper Pt electrode 15 into the third PZT film 21 to form a third PZT film.
The film 21 becomes conductive. The protective film 16 is formed by patterning the stacked structure up to this point, as in the first embodiment.

In the second embodiment, the first embodiment is used.
Unlike the PZT film, which has a three-layer structure,
The ZT film 21 is crystallized after depositing the upper Pt electrode 15. Then, the third PZT film 21 and the upper Pt
A low resistance contact between the electrodes 15 is obtained. Also, the third P
Although Pt diffuses into the ZT film 21 as described above, the second PZT film 14 has already been crystallized, and it is possible to make the diffusion of Pt almost nil.

FIG. 9 shows a Pt distribution and a Pb distribution of the ferroelectric capacitor C2 according to the second embodiment by SIMS analysis. As shown, the first and third PZTs
While a large amount of Pt diffusion is observed in the films 13 and 21, the second PZT film 14 hardly diffuses Pt.

Therefore, also in the second embodiment, the second PZT film 14 functions as a substantial capacitor dielectric film that determines the polarization characteristics, and exhibits excellent polarization characteristics with little leakage. Also, by selecting the thickness of the second PZT film 14, the ferroelectric capacitor can be made thinner. In the second embodiment, the first PZT film 13 is
At the same time, the third PZT film 21 serves as a barrier for suppressing hydrogen degradation of the second PZT film 14 due to the catalytic action of the t-electrode 12, and the second PZT film 21 acts as the second PZT
It functions as a barrier that suppresses hydrogen deterioration of the film 14. Thereby, stable polarization characteristics with less deterioration can be obtained.

The present invention is not limited to ferroelectric capacitors,
The present invention can be applied to a DRAM using a high dielectric capacitor. In this case, as the metal oxide dielectric of the high dielectric capacitor, for example, BSTO having a relative dielectric constant of 50 or more;
(Ba, Sr) TiO ₃ is used. An embodiment in which the present invention is applied to such a high dielectric capacitor will be described below.

Third Embodiment FIG. 10 shows a structure of a high dielectric capacitor C11 according to a third embodiment of the present invention, corresponding to FIG. 1 of the first embodiment. A first BSTO film 22 on the lower Pt electrode 12
And a second BSTO film 23 are laminated, and an upper Pt
An electrode 15 is formed. The manufacturing process is the same as in the first embodiment.
In the same manner as described above, Pt diffuses into the first BSTO film 22 in the heat treatment step for crystallization of the first BSTO film 22. The second BSTO film 23 formed thereafter is formed on the upper Pt electrode 1.
Crystallized before deposition of 5, which has little diffusion of Pt.

In the case of this embodiment, unlike the ferroelectric capacitor, the problem of the deterioration of the polarization characteristics due to the reducing action of hydrogen or the like does not occur. However, the second BSTO film 2
3 functions as a capacitor dielectric film of a substantially high-dielectric capacitor with little leakage, so that excellent charge retention characteristics can be obtained. Further, since there is no diffusion of the constituent elements of the lower electrode into the second BSTO film 23, the effect of facilitating the scaling of the film thickness can be obtained.

Fourth Embodiment FIG. 11 shows a structure of a high dielectric capacitor C12 according to a fourth embodiment of the present invention, corresponding to FIG. 7 of the second embodiment. First BSTO film 2 on lower Pt electrode 12
2, a second BSTO film 23 and a third BSTO film 24 are stacked, and an upper Pt electrode 15 is formed thereon. The manufacturing process is the same as in the second embodiment, and the first B
Pt diffuses into the first BSTO film 22 in the heat treatment step of crystallization of the STO film 22. Also, the third BSTO film 24
In the case, Pt is diffused by a crystallization process after depositing the upper Pt electrode 15. The second BSTO film 23 hardly diffuses Pt. Also in this embodiment, similarly, charge retention characteristics with less leakage can be obtained, and the film thickness can be easily scaled.

Fifth Embodiment The first metal oxide dielectric film described in each of the above embodiments may be formed into a plurality of layers formed by a plurality of steps. In particular. The steps of depositing a thin metal oxide dielectric film, performing a heat treatment for crystallization, and depositing the next metal oxide dielectric film are repeated. By using such a technique, the first metal oxide dielectric film can be made thinner as a whole. This is because, by stacking thin metal oxide dielectric films while sequentially crystallizing them, the depth of Pt diffusion from the lower Pt electrode to the upper metal oxide dielectric film can be reduced to a required thickness with only one layer. This is because it can be made smaller.

The present invention is not limited to the above embodiment. For example, in the above embodiment of the ferroelectric capacitor, PZT is used as the metal oxide ferroelectric film, but other ferroelectric films, for example, SBT (SrBi ₂ Ta ₂ O)
_The present invention can be applied to the case where ₉ ) is used. As for the high dielectric capacitor, another metal oxide dielectric film having a relative dielectric constant of 50 or more can be used. Further, the upper and lower electrodes are not limited to the Pt electrodes, but may be Ru, RuO.
_The present invention is also effective when using ₂ or the like.

[0044]

As described above, according to the present invention, since the metal oxide dielectric film has a multi-layer structure, the leakage is small, the film thickness is easily scaled, and the excellent polarization characteristics or charge retention is achieved. A semiconductor integrated circuit having a capacitor exhibiting characteristics is obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a ferroelectric capacitor according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the ferroelectric capacitor according to the first embodiment.

FIG. 3 is a diagram showing a memory cell structure according to the first embodiment.

FIG. 4 is a diagram showing polarization characteristics of the ferroelectric capacitor according to the first embodiment in comparison with a conventional example.

FIG. 5 shows S of the ferroelectric capacitor according to the first embodiment.
It is a figure showing an IMS analysis result.

FIG. 6 is a diagram showing a result of SIMS analysis of a conventional ferroelectric capacitor.

FIG. 7 is a diagram showing a structure of a ferroelectric capacitor according to a second embodiment of the present invention.

FIG. 8 is a view showing a manufacturing process of the ferroelectric capacitor according to the second embodiment.

FIG. 9 shows S of the ferroelectric capacitor according to the second embodiment.
It is a figure showing an IMS analysis result.

FIG. 10 is a diagram showing a structure of a high dielectric capacitor according to Embodiment 3 of the present invention.

FIG. 11 is a diagram showing a structure of a high dielectric capacitor according to Embodiment 4 of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Substrate, 11 ... Ti film, 12 ... Pt electrode, 13 ... First PZT film, 14 ... Second PZT film, 15 ... Pt electrode, 17 ... Protective film, 21 ... Third PZT film, 22 ... First
BSTO film, 23 ... second BSTO film, 24 ... third BSTO film, C1, C2 ... ferroelectric capacitor, C1
1, C12: High dielectric capacitor.

 ────────────────────────────────────────────────── ─── Continued on the front page F term (reference) 5F083 AD21 FR02 GA06 GA27 JA13 JA14 JA15 JA17 JA38 JA39 JA43 JA45 JA56 JA60 PR00 PR03 PR22 PR33

Claims (19)

[Claims] 1. A first metal oxide dielectric film formed on a lower electrode and crystallized, and a second metal formed on the first metal oxide dielectric film and crystallized. A semiconductor integrated circuit comprising: an oxide dielectric film; and an upper electrode formed on the second metal oxide dielectric film. 2. The semiconductor integrated circuit according to claim 1, wherein said first and second metal oxide dielectric films are ferroelectric films. 3. The semiconductor integrated circuit according to claim 1, wherein the first metal oxide dielectric film is crystallized including a constituent element of the lower electrode by diffusion from the lower electrode. . 4. The semiconductor integrated circuit according to claim 1, wherein said first and second metal oxide dielectric films are high dielectric films having a relative dielectric constant of 50 or more. 5. A first metal oxide dielectric film formed on a lower electrode and crystallized, and a second metal formed on the first metal oxide dielectric film and crystallized. An oxide dielectric film; a third metal oxide dielectric film formed on the second metal oxide dielectric film and crystallized; and a third metal oxide dielectric film formed on the third metal oxide dielectric film. A semiconductor integrated circuit, comprising: an upper electrode; 6. The semiconductor integrated circuit according to claim 5, wherein said first to third metal oxide dielectric films are ferroelectric films. 7. The first metal oxide dielectric film is crystallized including a constituent element of a lower electrode by diffusion from the lower electrode, and the third metal oxide dielectric film is 6. The semiconductor integrated circuit according to claim 5, wherein the semiconductor integrated circuit is crystallized including a constituent element of the upper electrode by diffusion from the electrode. 8. The semiconductor integrated circuit according to claim 5, wherein said first to third metal oxide dielectric films are high dielectric films having a relative dielectric constant of 50 or more. 9. The semiconductor integrated circuit according to claim 2, wherein said ferroelectric film has a perovskite-type crystal structure. 10. A step of depositing a first metal oxide dielectric film on a lower electrode and crystallizing the first metal oxide film by heat treatment; Depositing a second metal oxide dielectric film, crystallizing the second metal oxide dielectric film by heat treatment, and forming an upper electrode on the second metal oxide dielectric film. A method of manufacturing a semiconductor integrated circuit, comprising: 11. The method according to claim 10, wherein the first and second metal oxide dielectric films are ferroelectric films. 12. The semiconductor integrated circuit according to claim 10, wherein the first metal oxide dielectric film is crystallized including a constituent element of the lower electrode by diffusion from the lower electrode. Production method. 13. The method according to claim 10, wherein the first and second metal oxide dielectric films are high dielectric films having a relative dielectric constant of 50 or more. 14. A step of depositing a first metal oxide dielectric film on a lower electrode and crystallizing the first metal oxide film by heat treatment; Depositing a second metal oxide dielectric film and crystallizing the second metal oxide dielectric film by heat treatment; and forming a third metal oxide dielectric film on the second metal oxide dielectric film. A step of depositing a body film, a step of forming an upper electrode on the third metal oxide dielectric film, and a step of performing heat treatment to crystallize the third metal oxide dielectric film. A method for manufacturing a semiconductor integrated circuit, comprising: 15. The method according to claim 14, wherein the first to third metal oxide dielectric films are ferroelectric films. 16. The first metal oxide dielectric film is crystallized including a constituent element of a lower electrode by diffusion from the lower electrode, and the third metal oxide dielectric film is 15. The method for manufacturing a semiconductor integrated circuit according to claim 14, wherein the semiconductor integrated circuit is crystallized including a constituent element of the upper electrode by diffusion from the electrode. 17. The method according to claim 14, wherein the first to third metal oxide dielectric films are high dielectric films having a relative dielectric constant of 50 or more. 18. The ferroelectric film according to claim 11, wherein the ferroelectric film has a perovskite crystal structure.
3. The method for manufacturing a semiconductor integrated circuit according to 1. 19. The first metal oxide dielectric film is formed as a plurality of layers by repeating a plurality of steps of depositing a metal oxide dielectric film having a predetermined thickness and heat treatment for crystallization. The method for manufacturing a semiconductor integrated circuit according to claim 10, wherein: