KR100382058B1 - Method and apparatus for generating busy signal in vfd module - Google Patents

Abstract

PURPOSE: A method and an apparatus for generating a busy signal in a VFD module are provided to improve an operating speed by generating a Busy signal to reduce a rest period of a CPU. CONSTITUTION: A high to low conversion signal is obtained at an end point of a write signal by performing a logical NOR operation for a write signal and a SEL signal of a CPU(8a). The first signal is oscillated by using the high to low conversion signal obtained from the logical NOR operation process. The second signal is oscillated by using an X-signal of a VFD processor(8e). A BUSY signal is obtained by performing a logical OR operation for the first signal, the second signal, and a Y signal of the VFD processor. The SEL signal is generated by reading an address of the CPU.

Description

Busy signal generation method and circuit of VFD module

The present invention relates to a method and a circuit for generating a busy signal of a vacuum fluorescent display (VFD) module.

The VFD refers to a flat panel display device which is variously applied to industrial and home products, and the VFD module refers to a circuit that drives the VFD in conjunction with a CPU. The Busy signal of the VFD module is a request signal of the VFD module to wait for the CPU to not send data of the next step while the VFD module processes predetermined data transmitted from the CPU.

1 is a schematic block diagram showing a signal processing relationship between a conventional CPU and a VFD module. In FIG. 1, 1a represents a CPU, 1b represents an address decoder, and 1c represents a VFD module. As shown in FIG. 1, signal processing is conventionally performed by applying a software processing technique. First, when the CPU 1a outputs a predetermined address together with the input / output request signal IORQ, the signal selected by the decoder 1b is input to the SEL terminal of the VFD module 1c. At the time when a predetermined selected signal is input to the SEL terminal, the CPU 1a sends a write signal so that the data of the data port is processed by the VFD module 1c. When the VFD module 1c receives the write signal, the VFD module 1c waits for the CPU 1a not to send data of the next step while the VFD module 1c processes the predetermined data transmitted from the CPU 1a ( The request signal of 1c), that is, the busy signal is sent. In practice, the busy signal is sent by the VFD processor in the VFD module 1c. 2 is a timing diagram based on FIG. 3 is a table for explaining each parameter of FIG. In FIG. 2, a set up time and a holding time of the data or the SEL are divided based on a time point at which the write signal WR ends. As shown in FIG. 2, when the write signal from the CPU is finished, the busy signal is sent from a VFD processor in the VFD module. The delay time 6 of the busy signal can be regarded as a blank period from when the CPU sends a write signal to when the busy signal is received. Conventionally, a write signal from a CPU is input to an interrupt terminal of a VFD processor, and the VFD processor enters a predetermined sub-routine to process data. At this time, a predetermined signal is transmitted to the CPU as long as the data is processed. Such a signal is referred to as a Y signal of the VFD processor. In addition, a signal indicating the end of data processing is sent at the end of the Y signal, which is called an X signal of the VFD processor. The VFD processor sends an X signal and exits the subroutine. The Y signal acts as a busy signal. The CPU cannot perform the processing of the next step during the time when the VFD processor enters and exits the subroutine. In other words, the busy signal is relatively short, which leads to a prolonged empty period of the CPU.

By the above process, conventionally, the Busy signal is sent directly from the VFD processor in the VFD module as a software processing technique. However, in this way, since there is no busy signal during the time that the VFD processor enters and exits the subroutine, the CPU blanking period becomes longer, resulting in slower overall processing speed and efficient operation of the CPU. There is no problem.

The present invention has been made in view of the above problems, and an object thereof is to provide a method and a circuit for generating a busy signal which can reduce a blank period by using separate hardware.

Busy signal generation method of the VFD module according to the present invention to achieve the above object,

NOR combining a write signal and a SEL signal of the CPU;

Oscillating a first signal according to the NOR output signal;

Oscillating a second signal by the X signal of the VFD processor;

OR combining the first and second signals with the Y signal of the VFD processor.

In addition, the Busy signal generation circuit of the VFD module according to the present invention to achieve the above object,

A NOR gate for NOR coupling a write signal and a SEL signal of the CPU;

A first multivibrator for performing a predetermined oscillation by the NOR output signal;

A second multivibrator for performing a predetermined oscillation by the X signal of the VFD processor;

And an OR gate for OR coupling the output signals of the first and second multivibrators to the Y signals of the VFD processor.

Next, a preferred embodiment according to the present invention will be described with reference to the accompanying drawings.

4 is a timing diagram illustrating a method for generating a busy signal of a VFD module according to the present invention. As shown in FIG. 4, when the write signal and the SEL signal of the CPU are NOR-coupled, a high to low transition signal can be obtained at the end of the write signal. The first signal can be obtained by performing oscillation of 10 μS based on the converted signal. In addition, the second signal can be obtained by performing oscillation of 10 μS based on the high / low conversion signal of the X signal output from the VFD processor. When the first signal, the Y signal of the VFD processor, and the second signal are OR-coupled, a busy signal can be obtained. Thus, the blank period during the time that the VFD processor enters the subroutine is not only saved by the first signal, but the blank period during the time that the VFD processor exits the subroutine is saved by the second signal.

In order to implement the above-described busy signal generation method of the VFD module in an actual circuit, an appropriate multivibrator capable of adjusting the output pulse width is required. In the present embodiment, 74HC123 dual monostable multivibrator is used. 5 is a pin configuration diagram of the 74HC123 element. 6 is a function table of the 74HC123 element. In Fig. 6, the functional part applied to the present invention is indicated by an arrow. That is, the CLR terminal (pin number 3 or 11) and the B terminal (pin number 2 or 10) are fixed to the 'high' voltage level, and the high to low transition (high to low transition) to the A terminal (pin number 1 or 9). When a signal is applied, one 'high' output pulse is generated at the Q terminal (pin number 13 or 5) based on the time point at which the conversion signal is input. Here, when the resistor and the capacitor are externally connected between the Rext / Cext terminal (pin number 15 or 7) and the Cext terminal (pin number 14 or 6), the output pulse width of the output Can be adjusted. 7 is a connection diagram of a resistor and a capacitor between a 74HC123 Rext / Cext terminal and a Cext terminal. As shown in FIG. 7, a resistor having a predetermined value may be connected between the power supply Vcc terminal and the Rext / Cext terminal, and a capacitor having a predetermined value may be connected between the Rext / Cext terminal and the Cext terminal. . In this case, the width of the output pulse can be adjusted by multiplying the resistance value of the resistor and the capacitance of the capacitor.

8 is a circuit diagram of a busy signal generation of the VFD module according to the present invention. In FIG. 8, 8a is a CPU and in this embodiment, a Z-80 CPU is used. 8b is an address decoder that decodes an address according to the input / output request 10RQ signal of the CPU 8a and generates a SEL signal. 8c is a D flip-flop for temporarily storing predetermined data. In this embodiment, 74HC574 8-bit D flip-flop is used. 8d is a NOR gate for NOR combining the write signal and the SEL signal of the CPU. 8e is a VFD processor that processes data input by an external interrupt signal. 8f is a dual multivibrator that performs predetermined oscillation by the NOR output signal and the X signal of the VFD processor 8e. In this embodiment, 74HC123 Dual Monostable Multivibrator is used. 8g is a first OR gate that OR-couples the first multivibrator output signal of the dual multivibrator 8f and the Y signal of the VFD processor. 8h is a second OR gate for OR combining the output signal of the first OR gate 8g and the second multivibrator output signal of the dual multivibrator 8f.

Referring to the operation of Figure 8 as follows. The CPU 8a stores predetermined data in the D flip flop 8c, and transmits the address and the input / output request signal of the data to the address decoder 8b. The address decoder 8b decodes an address according to the input / output request signal and outputs a predetermined SEL signal. As the SEL signal is NOR coupled with the write signal of the CPU 8a, a high / low conversion signal can be obtained from the output signal of the NOR gate 8d at the end of the write signal. As the output signal of the NOR gate 8d is input to the A1 terminal (pin number 1) of the dual multivibrator 8f, at the first multivibrator output terminal (Q1 pin number 13) of the dual multivibrator 8f, The first signal of 4 degrees appears. The first signal means one pulse signal having a predetermined pulse width based on the high / low conversion signal. The pulse width can be adjusted by multiplying the resistance of the externally connected resistor R1 by the capacitance of the capacitor C1. In this example, a pulse width of 10 mu S was set as an appropriate value. On the other hand, the first signal serves as a clock pulse signal of the D flip-flop 8c and an interrupt signal of the VFD processor 8e, so that data temporarily stored in the D flip-flop 8c is stored in the VFD processor ( 8e). The VFD processor 8e enters a predetermined sub-routine and processes data. The VFD processor 8e outputs a signal corresponding to a period for processing data, that is, a Y signal through the first Pn.n terminal. At the end of the Y signal, a signal indicating the end of data processing, that is, an X signal is output through the second Pn.n terminal. The VFD processor 8e outputs the X signal and exits the subroutine. As the X signal is input to the A2 terminal (pin number 9) of the dual multivibrator 8f, the second signal of FIG. 4 is received at the second multivibrator output terminal (Q2 pin number 5) of the dual multivibrator 8f. Will appear. The second signal refers to one pulse signal having a predetermined pulse width based on the high / low conversion point of the X signal. The pulse width can be adjusted by multiplying the resistance of the externally connected resistor R2 by the capacitance of the capacitor C2. In this example, a pulse width of 10 mu S was set as an appropriate value. The first multivibrator output signal of the dual multivibrator 8f, i.e., the first signal of FIG. 4 and the Y signal of the VFD processor 8e are coupled at the first OR gate 8g. In addition, the output signal of the first OR gate 8g and the second multivibrator output signal of the dual multivibrator 8f, that is, the second signal, are combined at the second OR gate 8h. The output signal of the second OR gate 8h is a busy signal and is input to the Wait terminal of the Z-80 CPU to operate. Thus, the blank period during the time that the VFD processor enters the subroutine is not only saved by the first signal, but the blank period during the time that the VFD processor exits the subroutine is saved by the second signal.

As described above, according to the method and circuit for generating a busy signal of the VFD module according to the present invention, it is possible to generate a busy signal that can reduce the blank period of the CPU, thereby improving the overall processing speed and efficiently operating the CPU. It can be operated.

1 is a schematic block diagram showing a signal processing relationship between a conventional CPU and a VFD module.

2 is a timing diagram based on FIG.

3 is a table for explaining each parameter of FIG.

4 is a timing diagram illustrating a method for generating a busy signal of a VFD module according to the present invention.

5 is a pin configuration diagram of the 74HC123 element.

6 is a function table of the 74HC123 element.

FIG. 7 is a resistor and capacitor connection diagram between a 74HC123 Rext / Cext terminal and a Cext terminal.

8 is a circuit diagram of a busy signal generation of the VFD module according to the present invention.

* Explanation of symbols for the main parts of the drawings

1a, 8a ... CPU,

1b, 8b ... Address Decoder,

1c ... VFD module,

8c ... 8 bit D Flip-flop,

8d ... NOR Gate,

8e ... VFD processor,

8f ... Dual monostable multivibrator (Dual Monostable 8g, 8h ... OR gate.

Claims (16)

NOR combining a write signal and a SEL signal of the CPU; Oscillating a first signal according to the NOR output signal; Oscillating a second signal by the X signal of the VFD processor; OR combining the first and second signals with the Y signal of the VFD processor; and a method of generating a busy signal of a VFD module. The method of claim 1, wherein the SEL signal is a signal generated by decoding the address of the CPU. The method of claim 1, wherein the NOR output signal causes a high / low conversion at the end of the write signal. 4. The method of claim 1, wherein the first signal is a predetermined pulse generated based on the high / low conversion time point. 5. The method of claim 1, wherein the X signal causes a high / low conversion when the VFD processor completes data processing in a subroutine. The method according to claim 1 or 5, wherein the second signal is a predetermined pulse generated based on the high / low conversion time point. The method according to claim 1, wherein the first signal acts as an interrupt signal of the VFD processor to cause data from the CPU to be processed by the VFD processor. A NOR gate for NOR coupling a write signal and a SEL signal of the CPU; A first multivibrator for performing a predetermined oscillation by the NOR output signal; A second multivibrator for performing a predetermined oscillation by the X signal of the VFD processor; And an OR gate for OR coupling the output signals of the first and second multivibrators to the Y signal of the VFD processor. 9. The busy signal generation circuit of the VFD module according to claim 8, wherein the SEL signal is a signal generated by decoding the address of the CPU. The busy signal generating circuit of claim 8, wherein the NOR output signal causes a high / low conversion at the end of the write signal. 9. The busy signal generating circuit of the VFD module according to claim 8, wherein the first multivibrator is a monostable multivibrator. The busy signal generating circuit of the VFD module according to claim 8 or 10, wherein the first multivibrator outputs a predetermined pulse generated on the basis of the high / low conversion point. 9. The busy signal generating circuit of claim 8, wherein the X signal causes a high / low conversion when the VFD processor completes data processing in a subroutine. 9. The busy signal generating circuit of the VFD module according to claim 8, wherein the second multivibrator is a monostable multivibrator. 14. The busy signal generation circuit of the VFD module according to claim 8 or 13, wherein the second multivibrator outputs a predetermined pulse generated on the basis of the high / low conversion time point. 10. The busy signal generating circuit of claim 8, wherein the first signal acts as an interrupt signal of the VFD processor to cause data from the CPU to be processed by the VFD processor.