JP2632395B2 - Bus connection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a bus connection device, and particularly, connects a control bus having a high bus cycle frequency and a narrow data width to a system bus having a low bus cycle frequency and a wide data width to control a system. A bus connection device for transmitting data to a bus, wherein the bus connection device transmits data between buses having different specifications so that the data transmission speed is not reduced. A bus timing converter for converting a bus cycle frequency between the control bus and the system bus; and an address converter for converting an address used by the control bus into an address used by the system bus. An address register for temporarily storing the address converted by the address conversion means,
A data register for temporarily storing data from the control bus by a data width that can be transmitted by the system bus.

[Industrial applications]

The present invention relates to a bus connection device, and in particular, connects a control bus having a high bus cycle frequency and a narrow data width to a system bus having a low bus cycle frequency and a wide data width to transmit data from the control bus to the system bus. The present invention relates to a bus connection device.

Such a bus connection device is necessary, for example, when connecting an LSI to a system. A control bus with a high bus cycle frequency on the LSI side but a narrow data width, and a control bus with a low bus cycle frequency on the system side but a low data width. It is used when a wide system bus is connected to exchange data.

[Conventional technology]

In general, when two types of buses having different specifications are connected as described above, the following is performed. For example, a control bus having a high bus cycle frequency having a data width of 1 byte, and a control bus having a data width of 4 bytes and 1 /
A case where a system bus having a bus cycle frequency of 2 is connected and data is transmitted from the control bus to the system bus will be described. In this case, the system bus is 4 bytes as shown in FIG. 5, but only one byte is used in accordance with the number of bytes of the control bus, and the bus cycle of the control bus is twice the frequency of the system bus. However, the data was controlled to be transmitted at the same frequency as the frequency of the system bus.

[Problems to be solved by the invention]

By the way, in the above-described conventional bus connection device, the data transmission speed is set according to the low-speed bus, so that there is a problem that the data transmission speed is low as a whole and the processing capability of the system is low. is there. Further, as shown in FIG. 5, there is a part that is not used at all when transmitting data on the system bus, and this part is wasted, so that the data transmission time T becomes longer, and during this time other information is transmitted. There is a problem that the processing device cannot use the system bus.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a bus connection device that does not lower the data transmission speed when transmitting data between buses having different specifications.

[Means for solving the problem]

In the present invention, as shown in FIG. 1, means for solving the above problems include a control bus 1 having a high bus cycle frequency and a narrow data width and a system bus 2 having a low bus cycle frequency and a wide data width. And control bus 1
A bus connection device for transmitting data from the control bus 1 to the system bus 2, a bus timing conversion means 3 for converting a bus cycle frequency between the control bus 1 and the system bus 2, and an address used in the control bus 1. Is converted to an address used by the system bus 2, an address register 5 for temporarily storing the address converted by the address conversion unit 4, and data from the control bus 1 can be transmitted through the system bus 2. And a data register 6 for temporarily storing the data width.

[Action]

According to the present invention, the address and data input from the control bus in a high-frequency bus cycle are converted into the bus cycle frequency of the system bus by the bus timing conversion means while the address is converted by the address conversion means. The address is converted into an address used by the system bus and stored in an address register. On the other hand, data is accumulated in the data register by the data width of the system bus,
When a predetermined number of data are accumulated, one address stored in the address register is added to the system bus and the data is transmitted to the full transmission data width of the system bus. Therefore, the control bus does not need to match the bus cycle of the data to be transmitted with the bus cycle of the system bus, and can transmit data at high speed. Also, since the system bus can transmit data to the full width of the bus, other data transmission can be performed without occupying the bus for a long time with a small bus width, and the bus can be used efficiently. Thus, the information processing device can be made highly efficient. The present invention is particularly effective for a graphic display system device requiring a data transfer amount equal to that of a system bus. In other words, these devices need only be realized with the same bus data width and bus cycle frequency as the system.However, in many cases, the number of LSI pins actually used is limited. This can be realized by narrowing and increasing the cycle frequency.

〔Example〕

Hereinafter, embodiments of a bus connection device according to the present invention will be described with reference to the drawings.

FIG. 2 and FIG. 4 show an embodiment of the bus connection device according to the present invention. In this embodiment, the bus connection device 10
2, as shown in FIG. 2, a 1-byte data bus 11 and an address bus 12 as a control bus, and 4 bytes as a system bus.
It is configured by connecting byte address data buses 13-16. In the present embodiment, the bus connection device 10
Is an address conversion circuit 17 for converting an address on the control bus into a system bus address, an address register 18 for temporarily storing this address, and a 4-byte data register 19 to 22 for temporarily storing data transmitted by the control bus. When,
The bus timing conversion circuit 23 performs correction based on the difference between the clock timings of the two buses and creates an address and data transmission timing signal.

In this example, it is assumed that the bus timing frequency of the control bus is twice the bus timing of the system bus.

Next, the operation of the bus connection device according to the present invention will be described. In this example, the device connected to the control bus 20 as shown in FIG.
A case where data of consecutive addresses stored in 21 are transmitted to the device 23 connected to the system bus 22 will be described. FIG. 3 is a timing chart showing an operation state of the bus connection device described above. Data 0 of address 0 to data 3 of address 3 are transmitted at normal (high-speed) bus timing on the control bus. In response to this, the bus connection device converts the address by the address conversion device and stores data 0, data 1, data 2, and data 3 in the corresponding registers. When four bytes of data can be stored and these data can be transmitted to a low-speed bus, data 0 to data 3 stored in the data register are stored starting from the address stored in the address register. Data is transmitted to the low-speed data bus at normal bus timing (low speed).

Therefore, according to this embodiment, when data to be transmitted to the system bus is transmitted on the control bus, it can be transmitted at the high speed bus timing inherent in the control bus, and the same amount of data can be transmitted in the system bus. In transmitting data, data transmission is not performed for a long time using only a part of the wide bus width, but is performed in a short time using the full bus width. Therefore, other data transmission can be performed during idle time of the bus, and the information processing apparatus can be operated with high efficiency as a whole. This embodiment is particularly effective for a graphic display system device that requires a data transfer amount equal to that of the system bus. In other words, these devices need only be realized with the same bus data width and bus cycle frequency as the system.However, in many cases, the number of LSI pins actually used is limited. This can be realized by narrowing and increasing the cycle frequency. For example, when converting a 64-bit bus with a bus cycle of 25 MHz to a 32-bit bus with a bus cycle of 33 MHz, the number of signal lines required for the LSI differs by a factor of two. However, according to this embodiment, the LSI can be connected to the LSI via a 32-bit bus, and the number of signals is reduced. However, since data can be transmitted at a high bus timing, the data transfer ability does not decrease so much as compared with the data transfer ability of the system bus.

〔The invention's effect〕

As described above, according to the present invention, the bus connection device converts the bus cycle frequency between the control bus and the system bus to the bus connection device, and the system bus uses the address used in the control bus. Address conversion means for converting an address converted by the address conversion means, an address register for temporarily storing the address converted by the address conversion means, and a data register for temporarily storing data from the control bus by a data width which can be transmitted by the system bus. Therefore, when data to be transmitted to the system bus is transmitted on the control bus, the data can be transmitted at the high speed bus timing inherent in the control bus, and the same amount of data is transmitted in the system bus. Data transmission in a short time using the full bus width, You can perform other data transmission at the time, an effect that it is possible to operate the information processing device with high efficiency as a whole. The present invention is particularly effective for a graphic display system device requiring a data transfer amount equal to that of a system bus. In other words, these devices need only be able to achieve the same bus data width and bus cycle frequency as the system.
In many cases, the number of pins of I is limited, and therefore, it can be realized by reducing the bus width and increasing the cycle frequency as in the present invention.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a block diagram showing an embodiment of a bus connecting device according to the present invention, FIG. 3 is a timing chart showing the operation of the bus connecting device shown in FIG. FIG. 4 is a diagram showing an example of data transmission to which the present invention is applied;
FIG. 5 is a timing chart showing the operation of the conventional example. DESCRIPTION OF SYMBOLS 1 ... Control bus 2 ... System bus 3 ... Bus timing conversion means 4 ... Address conversion means 5 ... Address register 6 ... Data register

Claims (1)

(57) [Claims] A control bus (1) comprising a control bus (1) having a high bus cycle frequency and a narrow data width and a system bus (2) having a low bus cycle frequency and a wide data width.
A bus connection device for transmitting data from the control bus to the system bus, a bus timing conversion means for converting a bus cycle frequency between the control bus and the system bus; Address conversion means (4) for converting an address used on the bus (1) into an address used on the system bus (2); and an address register for temporarily storing the address converted by the address conversion means (4). (5) A bus connection device comprising: a data register (6) for temporarily storing data from the control bus (1) by a data width that can be transmitted by the system bus (2).