JPH09135237A - Transmission control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the availability of a buffer by using both buffers respectively exclusive for transmission and reception as buffers for transmission/reception at the time other than loop back operation. SOLUTION: At the time of normal transmission, MPU 1 transmits a transmission mode to a buffer manager 10 to start an output controller 5 with a transmission start signal TXE and to switch multiplexer 21 and 22 to the output side of MPU. Next, by synchronizing with a write signal WR, MPU makes an in- clock IN outputted from the manager to write data in the whole area of buffers 33H and 33L in this order. At this time the manager looks at a pointer PIU to switch to 33H to 33L. On the other hand, the controller 5 synchronizes with its own out-clock OUT to make the out-clock OUT outputted from the manager to 33H and 33L and reads data in the order of 33H and 33L to serial-convert it by a P-S conversion circuit 4 to be outputted to a transmission line. At this time, the manager looks at a pointer POU to switch a multiplexer 24 to 33H to 33L.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to parallel data to be transmitted, which is provided in an input / output unit of transmission / reception data of a device having a buffer for temporarily storing transmission / reception data and transmitting / receiving data via a serial transmission line. Transmission control circuit for converting the serial data into serial data and transmitting the data directly or through the modem to the serial transmission line, and converting the serial data received from the serial transmission line directly or through the modem into parallel data and fetching it. The present invention also relates to a transmission control circuit having a so-called loopback function capable of immediately receiving data transmitted by itself, and particularly having a function of effectively using a buffer.

[0002] In the drawings, the same reference numerals indicate the same or corresponding parts.

[0003]

2. Description of the Related Art FIG. 5 shows an example of the structure of a main part of a conventional transmission control circuit. In the figure, reference numeral 1 denotes the MPU and DB that control the transmission control circuit and are the main body for data transmission / reception.
A data bus of PU1, RD is a read signal of MPU1 and its output terminal, WR is a write signal of MPU1 and its output terminal, and INT is an interrupt signal to MPU1 and its input terminal.

Reference numeral 31 is a transmission buffer for temporarily storing transmission data. DI and DO are data input and output terminals of the buffer 31, respectively, and IN and OUT are data writing to the buffer 31, respectively. In-clock and out-clock for giving read timing and their input terminals, E
MP is an empty signal indicating that the stored data in the buffer 31 has become empty (empty) and its output terminal.

Reference numeral 32 is a receiving buffer for temporarily accumulating received data. DI and DO are data input and output terminals of the buffer 32, and IN and OUT are data writing to the buffer 32. In-clock and out-clock for giving read timing and its input terminals, F
UL is full of accumulated data in this buffer 32 (full)
It is a full signal indicating that it has become and its output terminal.

Reference numeral 2 is a bidirectional buffer provided on the data bus DB, which stores an internal buffer circuit 2a for outputting the data of the MPU 1 and data to the data bus DB according to ON / OFF of the read signal RD of the MPU 1. It comprises an internal 3-state buffer circuit 2b for turning on / off the input paths respectively. Reference numeral 4 denotes a PS conversion circuit that performs PS conversion of parallel transmission data output from the buffer 31 into serial transmission data, and outputs the serial transmission data to a transmission line via a modem (not shown). Reference numeral 5 denotes the PS conversion circuit. 4 is an output controller for controlling the P-S conversion of 4 and the reading of data from the buffer 31 by the output of the outclock OUT.

Reference numeral 6 is an SP conversion circuit for converting the serial reception data received from a transmission line (not shown) via a modem or the like into parallel reception data, and 7 is an SP conversion circuit of the SP conversion circuit 6. It is an input controller for controlling the P conversion and the writing of the reception data to the buffer 32 by the output of the in-clock IN. Further, 8 is a register in which data is written by the MPU 1, and 9 is a NOR gate which gives the empty signal EMP output from the buffer 31 or the full signal FUL output from the buffer 32 to the MPU 1 as an interrupt signal INT.

Next, the operation of FIG. 6 will be described. The numbers in parentheses below indicate the general steps of this operation. Normal operation: (transmission); (1) MPU 1 accesses register 8 and writes signal W
R is applied and the transmission start signal TXE is set to H to start the transmission operation of the output controller 5.

(2) The MPU 1 inputs the write signal WR to the in-clock input terminal IN of the buffer 31 until the buffer 31 becomes full or writes the data for the transfer length, and the write signal WR is input to the buffer 31 via the bidirectional buffer 2. Write the transmission data. The output controller 5 inputs the outclock OUT to the buffer 31 until the transmission is completed, reads the data from the buffer 31 in synchronization with the outclock OUT, and outputs the read data to the PS through the P-S conversion circuit 4.
-S-convert and send to a transmission path not shown.

(3) When the buffer 31 becomes full, the MPU
1 interrupts the writing process to the temporary buffer 31. On the other hand, the output controller 5 continues to read data from the buffer 31, but when the buffer 31 becomes empty, the empty signal EMP is sent from the buffer 31 to the MPU 1 via the NOR gate 9, and the MPU 1 makes this empty. know.

(4) The MPU 1 sends this empty signal EM
When P is received at the interrupt terminal INT, the process (2) is executed again. (5) When the MPU 1 writes the transfer length data in the buffer 31 and the output controller 5 finishes sending all the data, the sending operation is completed. (Reception); (1) When data is transmitted from the other device to the device itself on the transmission path, the received data is S-P converted through the S-P conversion circuit 6, and the input controller 7 operates every time one byte of data is accumulated. By inputting the inclock IN to the buffer 32, the accumulated 1-byte data is written in the buffer 32.

(2) When it is detected that the buffer 32 is full or the end code in the received data is received and the reception is completed, the buffer 32 outputs the full signal FU.
It outputs L, and the MPU 1 inputs this signal to the interrupt terminal INT via the NOR gate 9 and is informed of that (full). (3) Upon receiving the interrupt signal INT as the full signal FUL, the MPU 1 inputs the read signal RD to the bidirectional buffer 2 and the outclock terminal OUT of the buffer 32 until the buffer 32 becomes empty, and then the data is output from the buffer 32. Read out. If reception has not ended at this time, MP
U suspends the read process until buffer 32 is full again. During that time, the input controller 7 continues to be SP
Continue receiving data from the conversion circuit 6 and its SP conversion,
The SP converted data is written in the buffer 32.

(4) The MPU 1 continues the processes of (2) and (3) until it finishes reading all the received data, and when all the received data is received, the receiving operation is completed. Loopback operation: In this case, P- of this transmission control circuit
The data transmitted from the S conversion circuit 4 to the transmission path is returned to the SP conversion circuit 6 of the transmission control circuit again, and the transmission operation and the reception operation described above are performed almost in parallel.

In this way, the transmission control circuit having a so-called loopback function, which can immediately receive the data transmitted by itself, has independent buffers 31 and 32 for transmission and reception of transmission. There is. Further, in the normal operation other than the loopback operation, the transmission buffer 31 and the reception buffer 32 do not operate at the same time.

[0015]

In the conventional transmission control circuit described in FIG. 5, in the normal operation other than the loopback operation, when one of the transmission or reception buffers is performing the transmission or reception operation, , The other receive or send buffer is not working. That is, during that time, the buffer included in the transmission control circuit does not function effectively, and there is a problem that a circuit element and a space for arranging the circuit element are wasted. Further, during the loopback operation, the transmission buffer 31 and the reception buffer 32 need to operate at the same time, and it is necessary to have separate buffers for transmission and reception. There is a problem that the above buffer cannot be realized with one buffer.

Therefore, it is an object of the present invention to provide a transmission control circuit capable of loopback operation which can solve such a problem.

[0017]

In order to solve the above-mentioned problems, the transmission control circuit of the present invention comprises a main body means (MPU1) which is a main body for data transmission / reception, and first and second parallel storage means for temporarily storing parallel data. Buffers (33H and 33L), P-S conversion means (PS converter circuit 4, output controller 5) for inputting parallel data and converting and outputting to serial data, serial data input and converting to parallel data and outputting. Has a SP converting means (SP converting circuit 6, input controller 7) for writing the parallel data to be transmitted by the main body means in the first buffer during the loopback operation, and the PS converting means is the first buffer. The write data in the buffer is read, converted into serial data, transmitted and output to the transmission line side, and the transmission data folded back on the transmission line side is sent to the SP.
The conversion means receives and inputs, converts into parallel data, and second
In the transmission control circuit in which the main body means reads out the write data in the second buffer, the data input section (DI) of the first buffer in response to the first control signal.
The data output unit (data bus DB) of the main body means and S
The first multiplexer (21) for switching to the data output section of the -P conversion means, and the data input section (DI) of the second buffer in response to the second control signal are connected to the data of the SP conversion means. Second multiplexer (22) for switching between the output section of the main body means and the output section of the main body data, and the input section of the main body data according to the third control signal (data bus DB)
(The three-state buffer 2b of the bidirectional buffer circuit 2
Via a third multiplexer (23) for switching between a data output part (DO) of the first buffer and a data output part (DO) of the second buffer, and P- in response to a fourth control signal. Via a fourth multiplexer (24) for switching the data input section of the S conversion means to the data output section of the first buffer and the data output section of the second buffer, and the first to fourth control signals. During normal operation transmission, the main body means can write the data to be transmitted into the first and second buffers, and the P-S conversion means can also read the write data in the two buffers. When receiving, S
The first to fourth so that the -P conversion means can write the received data in the first and second buffers, and the main body means can read the write data in the two buffers.
And a means (buffer manager 10) for controlling switching of the multiplexer.

During normal operation other than loopback operation, when data is input to the operating first buffer or second buffer and the buffer becomes full,
Data is input to the other non-functioning second buffer or first buffer.・ During loopback operation, the same operation as the conventional transmission control circuit is performed.

[0019]

1 is a block circuit diagram showing the configuration of an embodiment of the present invention. In the figure, 33
(33H, 33L) are buffers having the same structure, and are also referred to as buffers # 1 and # 2 in the following description. The buffers (# 1) 33H and (# 2) 33L have the D described in FIG.
In addition to the terminals of I, DO and IN, OUT, EMP, and FUL, output terminals of an input count-up pointer PIU and an output count-up pointer POU are newly provided.

However, in FIG. 1, originally independent terminals and signals I are provided.
N and OUT are shown by I / O and one terminal and one signal line for convenience, and similarly, EMP and FUL are also shown by E / F and one terminal and one signal line for convenience. Also, PI
The same applies to the terminals and signals of U and POU, which originally consist of two terminals and two signal lines. Then 21, 22, 2
3 and 24 are multiplexers of the same structure, each of which is a MX for convenience.
Also referred to as # 1, MX # 2, MX # 3, MX # 4. Here, MX (# 1) 21 and MX (# 2) 22 are buffers #, respectively.
The MX (# 3) 23 has a role of switching and selecting one of two input paths for data to 1 and # 2, and the MX (# 3) 23 selects one of two input paths for data to the 3-state buffer 2b of the bidirectional buffer circuit 2. It has a role of switching and selecting, and MX (#
4) 24 has a role of switching and selecting one of two input paths of data to the P-S conversion circuit 4.

Reference numeral 10 denotes multiplexers MX # 1 to MX # 4.
Is a buffer manager that switches between The buffer manager 10 can input data from the MPU 1 via the read signal RD, the write signal WR, and the data bus DB, and the MPU 1 is in the reception mode or the buffers # 1, #.
Various status signals STS and interrupt signal INT are provided to notify that 2 is full or empty.

Further, the buffer manager 10 gives a transmission start signal TXE to the output controller 5 by the mode communication from the MPU 1, inputs an outclock OUT for data reading from the output controller 5, and sends it to the buffer # 1 or # 2. Distribute. Further, the in-clock IN for data writing is input from the input controller 7, and the buffer # 1 is input.
Or distribute to # 2.

Further, the buffer manager 10 uses the buffer #
The read signal RD input from the MPU 1 and the outclock OUT input from the output controller 5 as described above are directly supplied to the output terminals 1 and # 2.
Write signal W distributed from UT and input from MPU1
R and the in-clock IN input from the input controller 7 as described above are directly input to the in-clock I for data writing.
Distribute as N. Further, the buffer manager 10 receives an input count-up pointer PIU and an output count-up pointer POU as status signals from the buffers # 1 and # 2.
Also, the empty signal EMP and the full signal FUL are input.

FIG. 2 shows a buffer 33 having a capacity of 4 bytes.
It is a block circuit diagram which shows the example of an internal structure of (33H, 33L). In the figure, 50 to 53 are buffers each having a capacity of 1 byte (referred to as internal buffers), 60 is one of the internal buffers 50 to 53, and the data is read to the data output terminal DO of the buffer 33. It is a multiplexer for sending out.

Each time the input 40 of the outclock OUT, 40, at the rising timing thereof, an address for selecting the internal buffers 50 to 53 to the multiplexer 60 one by one (for reading the data) is sequentially selected as 00 → 01 →. 1
A 2-bit counter that outputs 0 → 11,
The output count-up pointer POU is the counter 40
It is a signal which becomes H and is output at the time of counting up.

Reference numeral 41 indicates each time the inclock IN is input.
At the rising timing, it is a 2-bit counter that outputs to the encoder 42 the addresses for sequentially selecting the internal buffers 50 to 53 one by one (for data writing) as 00 → 01 → 10 → 11. The input count-up pointer PIU is a signal which becomes H and is output when the counter 41 counts up.

Reference numeral 42 converts the 2-bit calculated value (address) 00, 01, 10, 11 output from the counter 41 into an address (clock) 0001, 0010, 0100, 1000 for selecting the internal buffers 50 to 53, respectively. It is an encoder. Therefore, in the buffer 33 of FIG. 2, the data of the data input terminal DI is sequentially written to the internal buffers 50 to 53 at the rising timing of the in-clock IN, and when the counter 41 counts up at this time, the input count-up pointer PIU becomes H. Becomes Further, data is sequentially read from the internal buffers 50 to 53 to the data output terminal DO at the rising timing of the out clock OUT, and when the counter 40 counts up at this time, the output count-up pointer POU becomes H.

The data input / output timing of the buffer 33 at this time is as shown in FIG. The empty signal E
MP is output by means (not shown) when the internal buffers 50 to 53 are all empty (data has been read), and a full signal FU is output.
L is output by means not shown when all the internal buffers 50 to 53 are full (data has been written). 4 is shown in FIG.
In the flowchart showing the operation at the time of transmission of the normal operation of S1,
~ S30 shows the detailed steps.

Next, the operation of FIG. 1 will be described with reference to FIGS. The numbers in parentheses below indicate the general steps of this operation. Normal operation: (transmission); (1) The MPU 1 accesses the buffer manager 10 to notify that it is in the transmission mode. As a result, the buffer manager 10 sends the transmission start signal TX to the output controller 5.
When E is set to H and the output controller 5 is activated (S
1), MX # 1 and # 2 are switched to the output side of MPU1 (S2).

(2) The MPU 1 writes data in the buffer # 1 or (# 1 and # 2) until the buffers # 1 and # 2 are full or the data for the transfer length is written. That is, in FIG. 4, the MPU 1 causes the buffer manager 10 to send the in-clock IN to the buffer # 1 in synchronization with its own write signal WR, and first writes 1-byte data to the internal buffer 50 at the head of the buffer # 1 (S11). ), If the data for the transfer length is completely written in this buffer # 1 (S1
2, branch Y), the transmission is completed (S30), but the data for the transfer length is not written in the buffer (S12, branch N) and the input count-up pointer PIU of this buffer # 1 is not H. (S13, branch N), the process returns to step S11 again to write the next 1-byte data into the next internal buffer 51.

In this way, the operations of steps S11 to S13 are repeated, data is written in the internal buffer 53 at the tail of the buffer # 1, and when the input count-up pointer PIU becomes H (S13, branch Y), the buffer manager 10 causes the write signal WR. The output of the in-clock IN synchronized with is switched to the buffer # 2. This causes MPU1 to
As in the case of 1, unless the data for the transfer length is written into this buffer # 2 (S15, branch N), the steps from S14 to
The operation of S16 is repeated to sequentially write the data of each byte into the internal buffers 50 to 53 of the buffer # 2. Then, the input count-up pointer PIU of this buffer # 2
Becomes H (S16, branch Y), the process returns to step S11, and the data writing operation from the internal buffer 50 at the head of the buffer # 1 is repeated. However, during this period (3), (4)
When buffers # 1 and # 2 become full like
MPU until two buffers # 1 and # 2 are empty
The write operation of 1 is not started.

On the other hand, the output controller 5 reads the data from the buffer # 1 or # 2 in synchronization with its own outclock OUT until the transmission is completed, and performs P-S conversion via the P-S conversion circuit 4 for transmission line. As serial data. At this time, the buffer manager 10 buffers MX # 4 according to the buffer read by the output controller 5.
1 or buffer # 2.

That is, in FIG. 4, the operations of steps S21 to S26 described below are the same as those of steps S11 to S1 described above.
It is performed in parallel with the operation of 6. Here, the buffer manager 10 first switches MX # 4 to the output side of the buffer # 1,
The outclock OUT is given to the buffer # 1 in synchronization with the outclock OUT of the output controller 5, and the head internal buffer 50 is supplied to the multiplexer 60 in the buffer # 1.
To select. As a result, the output controller 5 reads out and transmits 1-byte data from the internal buffer 50 at the head of the buffer # 1 (S21). Then, unless the output controller 5 completes reading the transferred data from the buffer # 1 (S22, branch N) and the output count amplifier pointer POU of the buffer # 1 does not become H (S23, branch N), step S21. The operation from S23 to S23 is repeated, and the output controller 5 sequentially reads data from the internal buffers 51 to 53. And the internal buffer 5 at the tail of buffer # 1
When the data is read from 3 and the output count-up pointer POU becomes H (S23, branch Y), the buffer manager 10 switches MX # 4 to the output side of the buffer # 2 and synchronizes with the outclock OUT of the output controller 5. The output of the outclock OUT is switched to the buffer # 2. As a result, for buffer # 2,
S24 to S corresponding to steps S21 to S23 of 1 respectively
When the data read operation of 26 is performed and the output count-up pointer POU of the buffer # 2 becomes H (S26, branch N), the process returns to step S21 and the above-described step S2 is performed.
The operations of 1 to S26 are repeated.

(3) Buffers # 1 and # 2 as described above
Is full, the buffer manager 10
Based on the input of full signal FUL from 1 and # 2,
To 1 along with a status signal STS to that effect and an interrupt signal IN
Send T. Therefore, the MPU 1 suspends the data writing process to the temporary buffer # 1 or the buffer # 2. On the other hand, although data is read from the buffer # 1 or the buffer # 2 by the output controller 5, when the buffers # 1 and # 2 become empty, the buffer manager 10 causes the buffer #
Based on the input of empty signal EMP from 1, # 2,
An interrupt signal INT is sent to the MPU 1 together with a status signal STS to that effect. The MPU is then informed of this.

(4) Upon receipt of the empty interrupt signal INT, the MPU again executes the processing of (2). (5) When the transfer length data is written and all the data is transmitted, the transmission operation is completed. (Reception); (1) The buffer manager 10 learns from the input converter 7 that the reception mode should be set, and MX #
1, MX # 2 is switched to the output side of the SP conversion circuit 6.
When the data is transmitted on the transmission path, the serial data is converted into parallel data through the SP conversion circuit 6, and the in-clock IN is output from the input controller 7 every time one byte of data is accumulated, and the buffer manager 10 causes the ink The inclock IN is given to the buffer # 2 in synchronization with the lock IN. The 1-byte data accumulated as a result is sequentially written into the internal buffers 50 to 53 of the buffer # 2, and the input count-up pointer P of the buffer # 2 is written.
When IU goes high, the buffer manager 10 switches the output of the inclock IN synchronized with the inclock IN from the input controller 7 to the buffer # 1. As a result, the received data from the SP conversion circuit 6 is sequentially written into the internal buffers 50 to 53 of the buffer # 1. When the input count-up pointer PIU of buffer # 1 becomes H, the operation of writing the received data from buffer # 2 is repeated again.

(2) During this time, when the buffers # 2 and # 1 become full or the end code in the received data is received, the buffer manager 10 informs the fact based on the full signal FUL from the buffers # 2 and # 1. The interrupt signal INT is sent to the MPU 1 together with the status signal STS. This makes MP
U1 knows that. (3) In response to the interrupt signal INT, the MPU causes the buffer manager 10 to output the outclock OUT in synchronization with the read signal RD of itself, and the buffer # 2 or the buffer # 1 until the buffers # and # 1 become empty. Read data from. At this time, the buffer manager 10 switches MX # 3 to buffer # 1 or buffer # 2 according to the buffer to be read. If the reception is not completed at this time, the MPU suspends the reading process until the buffers # 2 and # 1 are full again.

(4) The MPU continues the above process (2) until it finishes reading all the received data. When all the received data is received, the receiving operation is completed. Loopback operation: The MPU 1 accesses the buffer manager 10 to inform that it is in the loopback mode. As a result, the buffer manager 10 gives a H transmission start signal TXE to the output controller 5 to activate the output controller 5, and outputs MX # 1 to the output side of MPU1 and MX # 2 to the output of the SP conversion circuit 6. To the side, MX # 3
To the output side of the buffer # 2 and MX # 4 to the output side of the buffer # 1. Therefore, the buffer # 1 serves as a transmission buffer and the buffer # 2 serves as a reception buffer.

In the subsequent operation, the buffer 31 and the buffer 32 shown in FIG. 5 are the buffer (# 1) 33H and the buffer (#), respectively.
2) Replacing with 33L, data reading and writing from the MPU 1 and the output controller 5 and the input controller 7 to the buffers # 1 and # 2 is performed via the buffer manager 10, and the buffers # 1 and # 2 It is similar to the case of FIG. 5 except that the empty signal EMP and the full signal FUL are transmitted to the MPU 1 via the buffer manager 10.

[0039]

According to the present invention, a buffer for temporary data storage, which has been used exclusively for transmission and reception in a conventional transmission control circuit, can be used for both transmission and reception. Therefore, it is possible to efficiently use the buffer that has not been efficiently used in the conventional transmission control circuit and increase the capacity of the buffer without increasing the number of elements in the circuit. As a result, it is possible to increase the capacity of the buffer, which has been impossible to achieve due to limitations such as the maximum number of elements that can be used in the circuit and the mounting area of the elements. Further, since it becomes possible to increase the capacity of the buffer in the transmission control circuit, the load on the controller such as a CPU that controls transmission is reduced, and it becomes easier to realize high speed and low power consumption of the transmission control circuit. The effect of is obtained.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a configuration as one embodiment of the present invention.

FIG. 2 is a block circuit diagram showing the structure of a buffer.

3 is an explanatory diagram of input / output timing of the data of FIG.

FIG. 4 is a detailed flowchart of the transmission operation of FIG.

FIG. 5 is a block diagram of a conventional transmission control circuit.

[Explanation of symbols]

 1 MPU 2 Bidirectional buffer circuit 2a Internal buffer circuit 2b 3 State buffer circuit 4 PS conversion circuit 5 Output controller 6 SP conversion circuit 7 Input controller 10 Buffer manager 21-24 Multiplexer 21 MX # 1 22 MX # 2 23 MX # 3 24 MX # 4 33 (33H, 33L) Buffer 33H Buffer # 1 33L Buffer # 2 40,41 Counter 42 Encoder 50-53 Internal Buffer 60 Multiplexer DB Data Bus DI Data Input Terminal DO Data Output Terminal RD Read Signal WR Write signal INT Interrupt signal STS Status signal IN In-clock OUT Out-clock EMP Empty signal FUL full signal PIU Input count-up pointer POU Output count-up pointer T E transmission start signal

Claims (1)

[Claims] 1. Main body means for data transmission / reception, first and second buffers for temporarily storing parallel data, P-S conversion means for inputting parallel data and converting to serial data, and outputting serial data It has an SP converting means for inputting and converting to parallel data and outputting it, and during the loopback operation, the main body means writes the parallel data to be transmitted to the first buffer, and the PS converting means stores the parallel data. The write data is read, converted into serial data, transmitted and output to the transmission path side, and the transmission data folded back on the transmission path side is received and input by the SP conversion means, converted into parallel data, and stored in the second buffer. In the transmission control circuit for writing and reading the write data of the second buffer by the main body means, the input unit of the data of the first buffer in response to the first control signal. , A first multiplexer for switching between the data output section of the main body means and the data output section of the SP conversion means, and the data input section of the second buffer in response to the second control signal, A second multiplexer for switching between a data output section of the conversion means and a data output section of the main body means; and a data input section of the main body means in response to a third control signal,
The third multiplexer that switches between the data output unit of the first buffer and the data output unit of the second buffer, and the data input unit of the PS conversion means according to the fourth control signal are A fourth multiplexer for switching between the data output section of the first buffer and the data output section of the second buffer, and the data to be transmitted by the main body means during the normal operation transmission via the first to fourth control signals. The data received by the SP conversion means may be stored in the first and second buffers so that the PS conversion means can read the write data in the two buffers. It is possible to write to the first and second buffers, and to provide means for controlling switching of the first to fourth multiplexers so that the main body means can read the write data of the two buffers. Transmission control circuit to.