JP2723828B2 - Two-signal mixed data transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-signal type mixed data transmission circuit, and more particularly to a NRZ type serial data and a split phase type serial data which have the same unit of change in signal level as a serial mixed data signal. The present invention relates to a two-signal format mixed data transmission circuit for transmitting.

[0002]

2. Description of the Related Art In a mobile radio system or the like, a serial mixed data signal that transmits a data signal (SPL format serial data) by an SPL (split phase) code following a synchronization signal (NRZ format serial data) by an NRZ code is used. Have been. A conventional two-signal format mixed data transmission circuit for transmitting such a serial mixed data signal processes bit data to be transmitted by a software-controlled CPU (processor) and transmits NRZ format serial data or NRZ data from a serial port thereof. It was continuously transmitted as SPL format serial data converted from the format. An example of a method for performing data conversion from the NRZ format to the SPL format by software processing is proposed in Japanese Patent Publication No. Sho 61-30774.

[0003]

In the above-mentioned conventional two-signal mixed data transmission circuit, the time that the CPU spends in the process of performing the serial transmission cannot be ignored, and software such as waiting for another interrupt during data transmission. Heavy load on processing.

[0004]

A two-signal mixed data transmission circuit according to the present invention continuously outputs data to be transmitted as NRZ-format parallel data of a predetermined bit length unit,
A CPU for outputting a start signal upon completion of output, and a clock output unit for outputting a first clock synchronized with a transmission bit rate of the NRZ serial data and a second clock synchronized with a transmission bit rate of the split phase serial data. When the start signal is received, the transmission completion timing of the NRZ serial data is determined based on the stored value and the first clock. A switching signal generator to be output, and the first clock is selected when the switching signal is not output, and the second clock is selected and output as the transmission clock when the switching signal is output. A clock switching unit for receiving and accumulating parallel data from the CPU; A FIFO memory unit that outputs accumulated data as NRZ serial data in synchronization with the transmission clock, and a code format conversion unit that converts the NRZ serial data output from the FIFO memory unit into split-phase serial data When,
When the switching signal is not output, the output data of the FIFO memory unit is selected. When the switching signal is output, the output data of the code format conversion unit is selected and output as a serial mixed data signal. A data switching unit.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. The two-signal format mixed data transmission circuit of the present embodiment performs control processing based on software, continuously outputs data to be transmitted on the data bus 11 as 1-byte NRZ format parallel data, and starts up when output is completed. Signal (STRT
Signal) and a first clock C1 synchronized with the transmission bit rate of the NRZ serial data.
And a clock output unit 50 for outputting a second clock C2 synchronized with the transmission bit rate of the serial data in the SPL (split phase) format, and the transmission scheduled bit value of the NRZ format serial data stored in the built-in counter 21 in advance, and the STRT When a signal is received, a switching signal generator 20 that performs subtraction based on the first clock C1 and outputs a switching signal at the end of counting and a first clock C1 when the switching signal has not been output is selected. Is output, a clock switching unit 40 that selects the second clock C2 and outputs it as the transmission clock C0,
A FIFO (first-in first-out) memory unit that receives and stores NRZ format parallel data from the CPU 10 via the data bus 11 and, when receiving the STRT signal, outputs the stored data as NRZ format serial data in synchronization with the transmission clock C0. 30; an SPL conversion unit 60 for code-converting the NRZ serial data output from the FIFO memory unit 30 into SPL serial data having the same bit rate; and an NRZ output from the FIFO memory unit 30 when no switching signal is output. If the serial data is selected and the switching signal is output, S
An output data switching unit 70 selects the SPL format serial data from the PL conversion unit 60 and outputs the selected data as a serial mixed data signal. Note that the specific configuration of the SPL conversion unit 60 can be realized by a well-known appropriate technique (for example, see Japanese Patent Application Laid-Open No. 63-20919), and a description thereof will be omitted.

Next, the operation will be described. In this two-signal format mixed data transmission circuit, when transmitting data to the outside, the CPU 10 transfers all data to be transmitted to the FIFO memory unit 30 via the parallel data bus 11 once (continuously in byte units). Write in NRZ format.
When the writing is completed, the CPU 10 inputs the STRT signal to the switching signal generator 20 and the FIFO memory 30. This ends the processing on the CPU 10 side.

From the clock output unit 50, the clock C1
And the clock C2 are output. The relationship between the two clocks is that the clock C2 is obtained by dividing the frequency of the clock C1 by 1/2. That is, assuming that the transmission bit rate of the NRZ serial data is 2 Tbps, the frequency of the clock C1 is 2 THz, the transmission bit rate of the SPL serial data is Tbps, and the frequency of the clock C2 is THz. The switching signal generator 20 has a built-in counter 21 in which a value corresponding to the number of bits scheduled to be transmitted as serial data output in NRZ format is set in advance. At the same time as receiving the STRT signal, the counting of the clock C1 is started and the decrement of the counter value is started. When the switching signal generator 20 is in the middle of subtraction, no switching signal is output. The switching signal is output at the same time when the counter 21 in the switching signal generator 20 finishes the subtraction. Further, the clock switching unit 40 outputs the same clock as the clock C1 as the transmission clock C0 until receiving the switching signal. When the switching signal is received, the same clock as the clock C2 is output as the transmission clock C0.

Thus, the FIFO memory unit 30 outputs NRZ-format serial data synchronized with the clock C1 from the reception of the STRT signal to the generation of the switching signal. Output the NRZ format serial data synchronized with. on the other hand,
The SPL conversion unit 60 always converts the NRZ format serial data into a code and sends it out as SPL format serial data. The output data switching unit 70 switches between NRZ serial data and SPL serial data depending on the presence or absence of a switching signal. If there is no switching signal, the NRZ serial data is received. The SPL format serial data is output as a serial mixed data signal.

As described above, the bit rate of 2 Tbps N
A bit rate Tbp at which the unit time of change of the signal level is the same following the synchronization signal based on the RZ format serial data
The data signal based on SPL serial data can be switched without interruption and output as a serial mixed data signal.

[0010]

As described above, the two-signal format mixed data transmission circuit of the present invention stores all target data from the CPU as NRZ format parallel data of a predetermined bit length at a time in the FIFO memory unit. The NRZ format serial data is output from the memory unit as NRZ format serial data, and the NRZ format serial data is converted into a split phase (SPL) format serial data by a code format conversion unit.
The switching signal generator determines the transmission completion timing of data to be transmitted as NRZ serial data, and determines the NRZ serial data and S in the output data switching unit.
A desired serial mixed data signal can be output by controlling the selection of the serial data in the PL format and the selection of the corresponding clock in the clock switching unit. NR that is usually handled without performing
Data can be output with a single memory access in the Z format, and the load can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 CPU 20 Switching signal generation part 30 FIFO memory part 40 Clock switching part 50 Clock output part 60 SPL conversion part 70 Output data switching part

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-31853 (JP, A) JP-A-59-23945 (JP, A) JP-A-1-255922 (JP, A) JP-A-2- 72719 (JP, A)

Claims (1)

(57) [Claims] 1. A two-signal format mixed data transmission circuit for transmitting NRZ format serial data and split phase format serial data having the same unit time of change in signal level as a switched serial mixed data signal without interruption. And a CPU that continuously outputs NRZ-format parallel data in a predetermined bit length unit and outputs a start signal when the output is completed; a first clock synchronized with the transmission bit rate of the NRZ-format serial data; A clock output unit for outputting a second clock synchronized with a data transmission bit rate; a value of the number of bits of the serial data in the NRZ format being stored in advance; when the start signal is received, the stored value and the first NRZ format system based on the clock A switching signal generating unit that determines a transmission completion timing of real data and outputs a switching signal, and selects the first clock when the switching signal is not output, and selects the first clock when the switching signal is output. A clock switching unit for selecting a second clock and outputting it as a transmission clock; receiving and accumulating parallel data from the CPU; receiving the activation signal, synchronizing the accumulated data with the transmission clock to generate NRZ serial data; Output as
An FIFO memory unit; a code format conversion unit for converting NRZ format serial data output from the FIFO memory unit into split phase format serial data; and an output data of the FIFO memory unit when the switching signal is not output. And selecting the output data of the code format converter when the switching signal is output, and outputting the data as the serial mixed data signal. circuit.