KR100469436B1 - Data access circuit for multimedia device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data access circuit of a multimedia device, and more particularly, to convert data to be delivered to an external processor into serial data and to input parallel data into the processor through a memory in the form of a FIFO and SRAM combination. The purpose is to enable data transfer between processors without control of the data flow. The present invention for this purpose in the serial link between the modem processor 210 and the multimedia application processor (MAP) 220, the modem processor 210 converts the data to be transmitted to the MAP 220 to the serial conversion unit 521 and a memory 522 for storing serial data transmitted from the MAP 220 and inputting parallel data into the processor, wherein the MAP 220 serializes data to be transmitted to the modem processor 210. And a format converter 523 for converting data into a data, and a memory 524 for storing serial data transmitted from the modem processor 210 and inputting parallel data into the processor.

Description

DATA ACCESS CIRCUIT FOR MULTIMEDIA DEVICE}

TECHNICAL FIELD The present invention relates to multimedia devices, and more particularly, to a data access circuit.

Wired and mobile communication terminals with multimedia functions generally include a modem processor for communication and a media processor for processing media such as audio, audio, and video, and provide video on demand (VOD) or video telephony functions. In order to perform normal functions, two processors must be operated as one integrated processor.

To this end, the communication between the two processors transmits and receives data by using an interrupt method using dual-port RAM (DPRAM) or by using an interrupt method using a designated serial port. . That is, in general, a communication technology between two processors is a regular method to match the data rate provided to a communication channel, for example, a method of requesting a counterpart processor to process a task by generating mutual interruptions of about 50 to 100 times per second. use.

Interrupts are intended to notify the other processor of events that originally occurred irregularly and to allow the other processor to process the requested interrupts in order of priority. The frequency of interrupt occurrence is determined by the amount of movement per unit time of data.

Therefore, when an interrupt is requested from a processor, the processor that receives the interrupt interrupts the task that was being performed and processes the task preferentially for the interrupt.

1 is a conventional embodiment, as shown in a block diagram of a multimedia device having a DPRAM (Dual Port RAM), a modem processor (110) in charge of data and control processing of a communication channel, and audio / video A dual application memory (Multimedia Application Processor, hereinafter abbreviated as MAP) 130 for restoring or sign-processing the data; and dual access memory for storing transmission / reception data between the modem processor 110 and the MAP 130. Access Memory 120 is configured to preferentially process data stored in the dual access memory 120 by mutual interruption between the modem processor 110 and the MAP 130.

Referring to the operation of the conventional multimedia device as follows.

Since the modem processor 110 and the MAP 130 perform data exchange processing by interrupts, interrupts are generated every 10 ms or 20 ms depending on the size of the data unit.

That is, the modem processor 110 writes the received data in the dual access memory 120 and notifies the MAP 130 of the interrupt as a request to read the data. Then, the MAP 130 receives the interrupt, interrupts the task processing currently being performed, and performs the task of reading data from the dual access memory 120.

On the contrary, even when data is transmitted from the MAP 130 to the modem processor 110, the task is processed in the same manner as described above.

FIG. 2 is a block diagram of a multimedia device capable of transmitting data to a serial port according to another exemplary embodiment. As shown in FIG. 2, the modem processor 210 and the MAP 220 are connected to the serial port.

3 is a detailed block diagram of a data access circuit in the apparatus of FIG. 2, as shown in FIG. 2, in which a modem processor 210 receives an internal or external memory 211 for storing transmission / reception data and received from the memory 211. A register 212 for temporarily storing transmission data and a register 213 for temporarily storing received data from the outside and transferring the received data to the memory 211, and the MAP 220 stores an internal or external data for storing transmission / reception data. A memory 221, a register 222 for temporarily storing the transmission data received from the memory 221, and a register 223 for temporarily storing the received data from the outside and transferring the received data to the memory 221. .

Therefore, when data is transferred from the modem processor 210 to the MAP 220, the data is moved from the internal or external memory 211 to the register 212, and the data temporarily stored in the register 212 is a CPU (not shown). Or via an interrupt by a DMA host (not shown) to the register 222 and to an internal or external memory 221. Conversely, in the case of data transfer from the MAP 220 to the modem processor 210, data temporarily stored in the register 223 from the internal or external memory 221 is transferred to the register 213 and the transferred data is internal or external. Is transferred to the memory 211. The data processing delivered as above is processed by a CPU (not shown).

4 is a block diagram of the MAP 220 when the UART and the USB are generally used in the serial port in the prior art. As shown in FIG. 4, the modem processor 210 and the MAP 220 are connected to the UART 410 and the USB port. In the serial connection with the USB 420, the MAP 220 is a bus bridge 430, DMA 440, and CPU 450 are connected to the UART 410 and USB 420 It is provided and configured.

That is, when the serial port applied to another conventional embodiment such as FIG. 2 is UART or USB, the data stored in the UART 410 or the USB 420 through the bus bridge 430 as shown in the block diagram of FIG. 450) or by DMA 440.

However, the prior art has a problem that the overall performance is degraded due to the frequent interrupt generation between the two processors, the occupancy of the bus according to the data transfer using the DMA, and the consumption of additional instructions. In other words, if a high priority interrupt occurs frequently, processing delays for existing tasks are caused by additional operations due to interrupt processing between processors, and as a result, overall performance is degraded or has the same high priority. If an interrupt occurs at the same time, a malfunction may occur and power consumption may also increase.

In addition, conventionally, when the interrupt is not used, a polling method is used, but a blind accessing (blind polling) method of frequently checking whether data is required to be processed causes the same problem as described above.

That is, the conventional problem will be described in detail as follows.

1. When using DRAM (DPRAM), the processor receives frequent interrupts during the operation because writing and reading a certain amount of data must pass each other interrupts indicating completion. For example, a large amount of data at 384kbps results in more frequent interrupts than 64 or 128 kbps, further reducing processor performance.

2. When using a dedicated serial port In general, frequent interrupts are also a problem because data must be accumulated in a small memory embedded in the serial port and processed by the processor. The serial port is a universal standard such as UART and USB.

3. When using a DRAM or serial port, the data must be moved to the main memory area of the processor to process all received data. The usual means is to use DMA. As a result, when DMA operates to move data, there are problems such as additional power consumption, limiting the bus usage of other resources in the processor due to bus occupancy, and degrading the overall performance of the system.

Accordingly, the present invention controls the data flow by converting data to be delivered to an external processor into serial data and inputting serial data from the external processor into parallel data through a FIFO and SRAM combined memory in order to solve the conventional problems. It is an object of the present invention to provide a data access circuit of a multimedia device invented to enable data transfer between processors without a processor.

1 is a block diagram of a multimedia device using DPRAM according to an embodiment of the prior art.

2 is a block diagram illustrating a multimedia device capable of transferring data to a serial port according to another embodiment of the prior art.

Figure 3 is a detailed block diagram of the data access circuit in Figure 2;

4 is a block diagram showing the structure of the MAP in FIG.

5 is a configuration diagram of a data access circuit presented in an embodiment of the present invention.

6 is an exemplary view showing an input / output signal of a memory in FIG.

FIG. 7 is a block diagram showing the structure of a MAP to which the circuit of FIG. 5 is applied; FIG.

Explanation of symbols on the main parts of the drawings

521,523: format converter 522,524: memory

In order to achieve the above object, the present invention provides a data transfer circuit between a modem processor and a multimedia application processor (MAP), each processor comprising: a format converter for converting parallel data to be transmitted to a counterpart processor into serial data; And a memory (FIFO-SRAM) configured to store serial data to be transmitted and to input parallel data into the processor.

Therefore, in the data communication between processors for processing of audio / video data that must be regularly processed first, the present invention connects without interrupts to a dedicated DPRAM or serial port, rather than a method of transferring data by a DMA or a CPU. It is characterized by using the method of transferring directly to the main memory of the opponent processor being stored.

Differences between the present invention and the prior art using this method are as follows.

1. The present invention does not use DPRAM in the connection between the modem processor and the MAP, and can transmit data without data flow control even when using a serial port.

2. The present invention uses a serial port to transfer data in blocks without delays or interrupts.

3. The present invention eliminates the need for data transfer by the CPU or DMA host by using the FIFO-SRAM, so that the CPU or DMA can be assigned to another task.

Hereinafter, the present invention will be described in detail with reference to the drawings.

Also in the embodiment of the present invention, the basic building block includes a modem processor 210 and a MAP 220, as shown in FIG.

5 is a block diagram of a data access circuit for an embodiment of the present invention, as shown therein, in the serial link between a modem processor 210 and a multimedia application processor (MAP) 220, wherein the modem processor 210 is connected. Is a format conversion unit 521 for converting data to be transmitted to the MAP 220 into serial data, and a memory (FIFO-SRAM) for storing serial data transmitted from the MAP 220 and inputting parallel data into the processor ( 522, and the MAP 220 stores a format conversion unit 523 for converting data to be transmitted to the modem processor 210 into serial data, and stores serial data transmitted from the modem processor 210 to store the internal data. A memory (FIFO-SRAM) 524 for inputting parallel data is provided.

The memories 522 and 524 are a combination of FIFOs and SRAMs, and are memories that can be read / written without accessing the same address at the same time. That is, the memories 522 and 524 are dual access type memories having a capacity of 10 to 60 Kbytes, as shown in the exemplary diagram of FIG.

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

First, when data is transmitted from the modem processor 210 to the MAP 220, the format converter 521 converts parallel data into serial data and transmits the data to the MAP 220. Accordingly, the MAP 220 stores the serial data transmitted from the modem processor 210 in the memory 524 and reads out the parallel data by the CPU or the DMA.

In addition, when data is transmitted from the MAP 220 to the modem processor 210, the format converter 523 converts parallel data into serial data and transmits the data to the modem processor 210. Accordingly, the modem processor 210 stores the serial data transferred from the MAP 220 by the memory 522 and reads out the parallel data by the CPU or the DMA.

On the other hand, the memory 522, 524 is a type of memory that combines the FIFO and SRAM so that the FIFO and SRAM can be read / write without accessing the same address at the same time, the serial data is sequentially Store in FIFO and read parallel data from SRAM at the same time. At this time, the memory 522, 524 generates an interrupt to read the data by the CPU or DMA provided in the MAP 220 / modem processor 210 when a certain amount of data is stored. Accordingly, the memory 522 and 524 may transfer data to a corresponding processor using a serial port without controlling the data flow.

The memory 522 524 is given priority to the FIFO if the same address is accessed simultaneously for both the FIFO and the SRAM. Thus, the CPU or DMA can access the data from the SRAM while performing data transfer to the FIFO of the memory 522 524 to perform other tasks.

As described above, the present invention includes the memory 522 and 524 in which the FIFO and the SRAM are combined to directly access the data from the CPU or the DMA, thereby minimizing the delay of communication data. That is, the structure of the processor to which the present invention is applied is as shown in the configuration diagram of FIG. 7, since the memory (FIFO-SRAM) 730 is directly connected to the internal bus, so that the CPU 710 or the DMA 720 is connected to the memory ( 730 can be accessed directly. For example, a modem processor when a video call or a video-on-demand video-on-demand (VOD) function is performed in a wired or wireless video device using a video / audio processing processor. Data communication delay between the video and audio processor can be minimized.

As described in detail above, the present invention can achieve the following effects.

1. Simplify circuit configuration by eliminating the need for buffer memory to control the data flow on the serial port.

2. Since the data flow is not controlled, interrupts required by the CPU or DMA are not generated, thereby preventing the processor from degrading.

3. It is possible to minimize the delay of communication data since the buffer memory is not needed on the transfer path of the transmission data and the transmission data can be directly accessed.

4. Data movement between processors is done without CPU or DMA involvement, which can improve system performance.

Claims (4)

In the multimedia device having a multimedia application processor (MAP), Format converting means for converting data transmitted to the outside into serial data; And a memory means for storing serial data transmitted from the outside and inputting parallel data therein. The method of claim 1 wherein the memory means is A data access circuit of a multimedia apparatus, comprising: a combination of a FIFO for receiving serial data from the outside and an SRAM for reading parallel data therein, wherein the FIFO and the SRAM are simultaneously accessed. 3. The data access circuit of claim 2, wherein priority is given to the FIFO when the FIFO and the SRAM are accessed at the same address. The method of claim 1 wherein the memory means is And a circuit unit for generating an interrupt to access the data by the CPU or the DMA when a certain amount of data is stored.