JP2001188770A - One chip microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a one chip microcomputer in corporated with an interface for an external serial memory in which the number of terminals is reduced. SOLUTION: This microcomputer is provided with a circuit 3 for switching that which signal lines of a synchronizing clock signal line SK, a signal line DI for data reception, a signal line DO for data transmission and a chip select signal line CS to be transmitted between an interface 2 and an external serial memory or signal lines of a bus acknowledge signal line, a bus request signal line, an I/O request signal line, and a wait signal line are connected to terminals P1, P2, P3, and P4, thus, one terminal is shared by the two signal lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip microcontroller in which a central processing unit (hereinafter abbreviated as "CPU"), a main memory, an input / output port, and a system bus are integrated on one IC chip. It is about computers.

[0002]

2. Description of the Related Art An ordinary microcomputer has a structure shown in FIG.
As shown in the figure, a bus release acknowledge signal line BUSAC used in an environment having a plurality of bus masters as external terminals.
K, each terminal P of the bus release request signal line BUSREQ
11, P12, an I / O request signal line I for controlling the external memory as a separate space between the I / O space and the memory space
An OREQ terminal P13 and a wait signal line WAIT terminal P14 for delaying execution of a program are provided.

The terminals of each signal line are connected to a CPU, a main memory, an input / output port, and a system bus by one I / O.
In a one-chip microcomputer integrated on the C chip 100, the terminals are not generally used.
It is provided because it is required at the time of U inspection.

On the other hand, when an interface 2 of an external serial memory such as an EEPROM is incorporated, as shown in FIG. 3, a synchronous clock signal line SK transmitted between the interface 2 and the external memory, , A signal line DI for reception data (a signal line for transmission data and a signal line for reception data may be common), and each terminal P of a chip select signal line CS.
15, P16, P17, and P18 were newly provided.

[0005]

SUMMARY OF THE INVENTION Therefore, the conventional 1
In the chip microcomputer, each terminal of a bus release acknowledge signal line, a bus release request signal line, an I / O request signal line, and a wait signal line, and each terminal of a signal line transmitted between the interface and the external memory And are never used at the same time,
Since they were provided separately, the number of terminals wasted and increased,
There is a problem that it is difficult to reduce the chip size accordingly.

Accordingly, an object of the present invention is to provide a one-chip microcomputer having a built-in interface for an external serial memory, in which the number of terminals is reduced and the chip size is reduced.

[0007]

According to the present invention, a CPU, a main memory, an input / output port,
And a one-chip microcomputer in which a system bus is integrated on one IC chip, a built-in interface of an external serial memory, and a signal line transmitted between the external serial memory and the interface. , A bus acknowledge signal line, a bus request signal line, an I / O request signal line, or a corresponding signal line among the corresponding wait signal lines is switched to a common terminal.

With this configuration, a signal line transmitted between the interface and the external serial memory, a bus release acknowledge signal line, a bus release request signal line,
The / O request signal line or the corresponding signal line among the wait signal lines can be shared by one terminal to reduce the number of terminals.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a main part of a microcomputer according to an embodiment of the present invention. In the figure, 1 is a CPU, 2 is an external serial EEPROM.
Memory interface with memory such as OM and RAM,
3 is a switching circuit, and 4 is a register. In this embodiment, in addition to the CPU 1, the interface 2, the switching circuit 3, and the register 4, a ROM (not shown)
M is a one-chip microcomputer in which a main storage device including M, various I / O ports, and a system bus are integrated in one IC chip 100.

When the register 4 is set to 1, the switching circuit 3 outputs a bus release acknowledge signal line BUSACK and a bus release request signal line BU of the CPU 1.
SREQ, I / O request signal line IOREQ, and wait signal line WAIT are connected to terminals P1, P2, P3, and P, respectively.
4 when the register 4 is set to 0, the synchronous clock signal line S
K, a signal line DI for receiving data, a signal line DO for transmitting data, and a chip select signal line CS are connected to terminals P1,
Connect to P2, P3, P4.

The CPU 1 executes a bus release acknowledge signal line BUSACK and a bus release request signal line BUSRE based on an application program stored in a ROM or a RAM constituting a main storage device (not shown).
When it is recognized that the Q, I / O request signal line IOREQ or the wait signal line WAIT is used,
The register 4 is set to 1 and the signal lines BUSACK, BUSREQ, IOREQ, and WAIT are connected to the terminals P1, P2, P3, and P4 via the switching circuit 3, respectively.

The CPU 1 is connected to an external memory, and is connected to the synchronous clock signal line SK of the interface 2, a signal line DI for receiving data, a signal line DO for transmitting data,
When it is recognized that each signal line of the chip select signal line CS is used, 0 is set in the register 4 and the signal lines of SK, DI, DO, and CS are connected to the terminals P1, P2, Connect to P3, P4. In other words, it is sufficient to set 1 to the register 4 when the CPU 1 is in the inspection mode.

With the above configuration, the terminals P1, P2, P
3, P4 are a bus release acknowledge signal line BUSACK and a bus release request signal line B
When a USREQ, an I / O request signal line IOREQ, or a wait signal line WAIT is required, these terminals serve as terminals for these signal lines. On the other hand, the terminals serve as terminals for each signal line of the interface 2.

As described above, in the one-chip microcomputer of the present embodiment, generally, each signal line of the interface 2 and the bus release acknowledge signal line BUSAC
K, the bus release request signal line BUSREQ, the I / O request signal line IOREQ, and the wait signal line WAIT are not used at the same time. The number of terminals is reduced by sharing terminals with the corresponding signal line among the acknowledge signal line BUSACK, the bus release request signal line BUSREQ, the I / O request signal line IOREQ, or the wait signal line WAIT.

In the above embodiment, the synchronous clock signal line SK of the interface 2 and the data receiving signal line D
I, the signal line DO for data transmission, and the chip select signal line CS are connected to the bus acknowledge signal line BUSACK,
Although the terminals are shared with the bus request signal line BUSREQ, the I / O request signal line IOREQ, and the wait signal line WAIT, the terminals may be shared by other combinations.

In the above embodiment, the CPU 1 controls the switching circuit 3 by the internal register 4. Normally, as shown in FIG. 2, a signal for switching between the normal operation mode and the inspection mode is output. Since there is a mode switching terminal P5 for inputting, the switching circuit 3 may be directly controlled by a signal input to the mode switching terminal P5.

Further, in the above embodiment, there are four interface signal lines, but if the data transmission signal line and the data reception signal line are common and there are three lines, a bus release acknowledge is used. The terminal may be shared with any three of the signal line, the bus request signal line, the I / O request signal line, and the wait signal line.

[0018]

As described above, according to the one-chip microcomputer of the present invention, a signal line transmitted between a built-in interface and an external serial memory, a bus release request signal line, and a bus release acknowledgement The signal line, the I / O request signal line, or the corresponding signal line among the wait signal lines can be shared by one terminal, so that the number of terminals can be reduced and the chip size can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a one-chip microcomputer according to an embodiment of the present invention.

FIG. 2 is a block diagram of a one-chip microcomputer according to another embodiment of the present invention.

FIG. 3 is a block diagram of a conventional microcomputer including an external serial memory interface.

[Explanation of symbols]

 1 CPU 2 Interface with external serial memory 3 Switching circuit 4 Register

Claims (1)

[Claims] 1. A one-chip microcomputer in which a central processing unit, a main storage device, an input / output port, and a system bus are integrated on one IC chip, wherein an external serial memory interface is built-in. A signal line transmitted between an external serial memory and the interface, and a corresponding signal line among a bus acknowledge signal line, a bus request signal line, an I / O request signal line, and a wait signal line A means for switching whether or not to connect to a common terminal.