KR100376720B1 - An imitating encoder signal generating device and a method thereof - Google Patents

Abstract

The present invention relates to an encoder signal simulation apparatus and a method thereof. An encoder signal simulation method of the present invention includes a method of generating an encoder signal required by a numerical controller in a motor drive, the method comprising: calculating the number and direction of pulses to be generated at each control period from high resolution position information; Generating an A / B phase signal from the calculated number and direction of pulses via a pulse train generation circuit; And generating a Z-phase pulse every time the control axis rotates.

The present invention makes it possible to simulate in real time a signal of an encoder having an arbitrary number of pulses per revolution from the high resolution positional information grasped by the control device, so as to set an arbitrary number of encoder pulses suitable for the control degree of the numerical controller. This makes it possible to improve the control of the system and can be combined with any analog interface type numerical controller regardless of the number of encoder pulses that can be connected to the numerical controller.

Description

Encoder signal simulation apparatus and method thereof {AN IMITATING ENCODER SIGNAL GENERATING DEVICE AND A METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoder signal simulation apparatus and a method thereof, and more particularly, to a method for generating an encoder signal required by a numerical controller in a motor drive. An encoder signal simulation apparatus and method for simulating and outputting a signal of an incremental encoder having a number in real time.

In general, in an analog interface type numerical control system that transmits a control command to a motor drive at a voltage of 10 V, a numerical control system (NC) must connect an encoder to obtain position information necessary for control. do. To this end, there is a method of connecting a separate encoder to the numerical controller, but in most cases, the method of relaying the signal of the motor encoder connected to the drive to the numerical controller is mainly used because of the simplicity of configuration and the advantages of cost reduction. do.

The encoder signal relay function of a conventional motor drive device uses a method of sending a motor encoder signal in a one-to-one manner through a buffer or by dividing it into 1/2, 1/4, 1/8, etc. via a divider circuit. Doing.

However, when the motor drive relays the motor encoder signal one-to-one or by dividing to the numerical control device as in the related art, the following problems may occur.

1, if the number of pulses of the relayed encoder signal does not correspond to the combination of the number of pulses that can be connected to the numerical control device, the interface is impossible

2. If the number of pulses of the signal relayed is smaller than the number of pulses of the encoder required to satisfy the minimum control unit of the numerical control system,

3. The minimum command unit and the minimum control unit do not match when the transmission ratio of the power transmission element is not a constant ratio.

As described above, a motor drive having a conventional one-to-one or dispenser repeater has a problem in that it is difficult to apply to a control system as described above.

In order to solve such a problem, the technical problem to be achieved by the present invention is to enable to generate in real time the signal of the encoder having an arbitrary number of pulses per revolution from the high resolution position information that the control device grasps There is a purpose.

1 is a block diagram showing an encoder signal simulation apparatus according to an embodiment of the present invention.

2A and 2B are diagrams showing the basic principle of generating the encoder signal simulation and the generated signal waveform according to the present invention.

3A and 3B are diagrams showing output waveforms of an A / B phase generation circuit to which a multiplication pulse is given.

4A and 4B are circuit diagrams showing a sequential logic table of the A / B phase generation circuit and the A / B phase generation circuit accordingly.

5 is a diagram showing a pulse train generation circuit and a comparison circuit.

6 is a diagram illustrating a generation process of a Z-phase signal.

FIG. 7 is a circuit diagram illustrating a Z-phase generating circuit implementing the Z-phase generating principle of FIG. 6.

8 is a flowchart illustrating a process of an encoder signal simulation generation unit according to an embodiment of the present invention.

An apparatus for generating encoder signal simulations according to one aspect of the present invention for achieving the above object,

An encoder signal simulation generation unit configured to receive a high resolution position information signal and perform arithmetic processing necessary for generating an encoder signal;

A pulse train generation unit receiving a pulse repetition period of a pulse train from the encoder signal simulation generation unit and generating a pulse train;

A counting unit for counting a pulse train output from the pulse train generator;

A comparison unit which receives the number of pulse strings to be generated in one control period from the encoder signal simulation generation unit and compares them with the output of the counting unit;

An A / B phase generator which receives the pulse string output from the pulse string generator and a rotation direction signal output from the encoder signal simulation generation processor to generate A phase and B phase signals; And

A comparison unit for comparing a Z-phase generation position signal output from the encoder signal simulation generation unit with an output of the counting unit;

And a Z-phase generator for receiving an output of the comparator, an output of the counter, and a rotation direction signal of the encoder signal simulation generation unit to generate a Z-phase signal.

An encoder signal simulation method according to another aspect of the present invention,

Calculating the number and direction of pulses to be generated for each control period from the high resolution position information;

Generating an A / B phase signal from the calculated number and direction of pulses via a pulse train generation circuit; And

Generating a Z-phase pulse for every one revolution of the control axis.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing an encoder signal simulation apparatus according to an embodiment of the present invention.

As shown in FIG. 1, an encoder signal simulation generating apparatus according to an embodiment of the present invention comprises: an encoder signal simulation generation unit 100 for receiving a high resolution position information signal and performing arithmetic processing necessary for generating an encoder simulation signal; A pulse train generation circuit 200 which receives a periodic signal of a multiplication pulse from the encoder signal simulation generation processing unit 100 and generates a pulse train; A first comparison circuit 300 and a second comparison circuit 400 for receiving and comparing the number of quadrupled pulses from the encoder signal simulation generation unit 100; A counter 500 that counts the pulse train output from the pulse train generator 200 and outputs the pulse train output to the first and second comparison circuits 300 and 400; An A / B phase generation circuit 600 for receiving the pulse string output from the pulse string generation circuit 200 and the signal output from the encoder signal simulation generation processing unit 100 to generate the A phase and B phase signals; Z phase generation circuit for receiving the signal output from the encoder signal simulation generation unit 100 and the signal counted by the counter 500 and the signal output from the second comparison circuit 400 and outputting the Z phase signal ( 700).

The encoder signal simulation generation unit 100 may be a single microprocessor in which an algorithm capable of simulating an encoder signal is stored, and the present invention is not limited to the embodiment.

Hereinafter, the operation of the encoder simulation signal generating circuit according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B are diagrams showing the basic principle of generating the encoder signal simulation and the generated signal waveform according to the present invention.

In FIG. 2A, the drive controller (not shown) grasps the position change amount [Delta] P during the control period from the high resolution position information Pk measured at every control period. The pulse number N of four multiplications corresponding to this position change amount (DELTA) P is calculated, and the encoder signal is produced by the A / B phase generation circuit 600 in a next control period. Here, four pulse signals are required to generate one cycle of the A / B phase signal having a phase difference of 90 degrees. Thus, four times the pulses of the A / B phase signal are used during the generation of the encoder signal. In fact, since the encoder provides a Z-phase signal in which one pulse is output per rotation in addition to the incremental A / B-phase signal, the encoder simulates it through the Z-phase signal generation circuit 700. When the period T of the multiplication pulse and the number N and the generation position k according to the Z phase pulse generation conditions are determined by the control routine of the encoder signal simulation generation processing unit 100 from the position change amount ΔP. The encoder signal simulation generator generates the A / B phase and the Z phase as shown in Fig. 2B.

3A and 3B are diagrams showing output waveforms of an A / B phase generation circuit to which a multiplication pulse is given.

When the signal in the forward direction (D = 0) is applied from the encoder signal simulation generation processing unit 100, the phase A of the waveforms output from the A / B phase generation circuit 600 is the phase B of the waveform as shown in FIG. 3A. 90 degrees ahead, when the reverse direction (D = 1) signal is applied from the encoder signal simulation generation processing unit 100, the phase A phase of the waveform output from the A / B phase generation circuit 600 is B as shown in FIG. 3B. It is 90 degrees slower than the phase of the phase.

4A and 4B are circuit diagrams showing a sequential logic table of the A / B phase generation circuit and the A / B phase generation circuit accordingly.

When four multiplication pulses are applied under the conditions given in the direction in Fig. 3 and the states on A / B, a sequential logic table defining a state as in Fig. 4A is obtained. If a sequential logic circuit is constructed from a sequential logic table as shown in FIG.

Ak = + A + DB + DAB = A (DB +) + (DB +) = DB +

Bk = A + AB + D + DB = B (D + A) + (D + A) = D + A

Where A = A _K-1 , B = B _K-1 Ak: k-th pulse sequence in A phase, Bk: k-th pulse sequence in B phase, A = A _K-1 , B = B _K-1

The A / B phase generation circuit 600 as shown in FIG. 4B is formed by the logic circuit shown in Equation 1 above.

The A / B phase generation circuit 600 includes a first D flip-flop and a second flip-flop for receiving a clock CLK4; A first exclusive logical sum that receives the direction signal D and the output signal of the second flip-flop and outputs an inverted signal; And a second exclusive logical sum receiving the direction signal D and an output signal of the first flip-flop.

5 is a diagram showing a pulse train generation circuit and a comparison circuit.

As shown in FIG. 5, the pulse train generation circuit 200 includes a first register, a first counter, a first comparator, and a third flip-flop.

The first register receives a clock signal (-WR_T) to store one input signal and applies an output signal to the first comparator, and the OR signal of the first comparator output signal and the first register is an input signal of the third flip-flop. Is applied to output the clock CLK4. The fourth flip-flop, which receives the input clock of the first register as a preset PR and receives the inverted output value of the first comparison circuit as a clear CLR, outputs an output signal to the first counter, and the first counter outputs the first counter. The signal is input to the first comparator.

The first comparison circuit 300 includes a second register, a second comparator, and a fifth flip flop, respectively. The second comparison circuit 400 includes a third register, a third comparator, and a sixth D flip-flop. The second register receiving the clock signal (-WR_N) receives the number of pulse strings (N) and applies a signal to the second comparator. The fifth flip-flop includes a signal obtained by outputting the output signal of the second register through a logical sum. As a result of the output signal of the two comparators passing through the logical product, the signal is input and the output signal is applied to the clear of the second flip-flop of the pulse train generator 200. The second comparison circuit 400 is the same as the first comparison circuit.

If a pulse period T other than 0 is specified in the register, the pulse train generation circuit 200 generates one clock pulse CLK4 when the pulse train cycle T is reached by counting the clock CLK. The pulse train of the period T is generated by resetting 500). The first comparison circuit 300 counts the pulses of the generated clock CLK4 and stops the pulse train generation circuit 200 when the number N is reached so that the generated pulse trains are exactly N. The second comparison circuit 400 notifies the Z phase generation circuit 700 when the counted pulse number reaches the order NZ in which the Z phase should occur.

6 is a diagram illustrating a generation process of a Z-phase signal.

As shown in FIG. 6, whenever the control axis rotates and passes the encoder reference zero, the Z phase pulse signal is 1 during the period corresponding to one cycle on A / B, that is, four quadrupled pulses. Should be To this end, when the encoder signal simulation generation processing unit 100 calculates the pulse string sequence k in the control period in which the Z phase signal should be generated in synchronization, the Z phase generation circuit 700 counts the pulse strings so that the counted value is increased. The Z phase signal is generated when the pulse train sequence k is reached. When four pulses are input in the same direction as the rotation direction when the Z phase signal occurs or one pulse is input in the inverted direction, the Z phase signal returns to zero (0).

FIG. 7 is a circuit diagram illustrating a Z-phase generating circuit implementing the Z-phase generating principle of FIG. 6.

When the Z-phase signal generation condition is input through the signal NZ_EQ, the Z-phase is designated as 1 by the flip-flop FF1, and the flip-flop FF2 stores the direction D specified at that moment, and the 4-bit The counter is cleared to zero. The Z-phase signal is stored in the forward direction (D = 0), when the 4-bit counter is 4 = (0100) B or -1 = (1111) B, or in the reverse direction (D = 1). When the 4-bit counter becomes -4 = (1100) B or 1 = (0001) B, it returns to zero.

8 is a flowchart illustrating a process of generating an encoder signal simulation according to an embodiment of the present invention.

First, the encoder signal simulation generation unit 100 calculates a rotation angle per one pulse of four times the simulation generation, and calculates a period per one pulse (S100).

The encoder signal simulation generation unit 100 receives the transmitted high resolution position information and calculates an absolute position angle (S110).

The encoder signal simulation generation unit 100 calculates the number of quadrupled pulses currently reached (S120).

The encoder signal simulation generation unit 100 calculates the number of output pulses in the next cycle from the output accumulated pulse number (S130).

The encoder signal simulation generation unit 100 determines whether the number of output pulses is greater than zero (S140). If the number of output pulses is greater than zero, the encoder signal simulation generation processing unit 100 recognizes the forward direction (S150). If the number of output pulses is less than zero, the encoder signal simulation generation processing unit 100 recognizes the reverse direction (S160). ).

The encoder signal simulation generation unit 100 determines whether the encoder passes the zero position of the encoder during the next control period (S170).

The encoder signal simulation generation unit 100 sets the number of pulses remaining up to the zero position (S180) and initializes the cumulative number of pulses (S190). The encoder signal simulation generation unit 100 outputs a pulse string period T, a pulse string number N, a pulse string direction D, and a Z-phase pulse string number NZ (S200).

If the encoder zero position does not pass during the next control period, the encoder signal simulation generation unit 100 sets the Z-phase pulse string number NZ to 0 and updates the cumulative pulse number newly (S210).

Embodiment of the present invention is only one embodiment, and many variations and modifications to the components of the present invention without departing from the gist of the invention, of course, the present invention is not limited to the embodiment. .

As described above, the encoder signal simulation apparatus and method thereof of the present invention enable to generate in real time a signal of an encoder having an arbitrary number of pulses per revolution from the high resolution positional information grasped by the control apparatus. Any number of encoder pulses can be set to suit the control level of the control device, thereby improving the control degree of the system.

In addition, the present invention can be combined with any analog interface type numerical controller regardless of the number of encoder pulses that can be connected to the numerical controller.

In addition, the present invention eliminates the need for a separate encoder, thereby reducing the cost of additional materials when applied to machine tools.

Claims (8)

In the signal generator that generates the encoder signal required by the numerical controller in the motor drive, An encoder signal simulation generation unit configured to receive a high resolution position information signal and perform arithmetic processing necessary for generating an encoder signal simulation; A pulse train generation unit receiving a pulse repetition period of a pulse train from the encoder signal simulation generation unit and generating a pulse train; A counting unit for counting a pulse train output from the pulse train generator; A comparison unit which receives the number of pulse strings to be generated in one control period from the encoder signal simulation generation unit and compares them with the output of the counting unit; An A / B phase generator which receives the pulse string output from the pulse string generator and a rotation direction signal output from the encoder signal simulation generation processor to generate A phase and B phase signals; And A comparison unit for comparing a Z-phase generation position signal output from the encoder signal simulation generation unit with an output of the counting unit; A Z-phase generator for generating a Z-phase signal by receiving an output of the comparator, an output of the counter, and a rotation direction signal of the encoder signal simulation processing unit. Encoder signal simulation apparatus comprising a. The method of claim 1, wherein the pulse train generating unit A first register, a first counter, a first comparator, a third flip-flop, a fourth flip-flop, The first register receives a clock signal to store one input signal and applies an output signal to the first comparator, and the first comparator output signal and the logic sum signal of the first register are the input signals of the third flip-flop. Is applied to output a clock, the fourth flip-flop outputs an output signal to the first counter, and the first counter inputs the output signal to the first comparator. According to claim 1, wherein the A / B phase generating unit An encoder signal simulation generator, characterized in that configured as follows. (Logical) Ak = + A + DB + DAB = A (DB +) + (DB +) = DB + Bk = A + AB + D + DB = B (D + A) + (D + A) = D + A A = A _K-1 , B = B _K-1, D: pulse train direction, Ak: k-th pulse train sequence on A phase, Bk: k-th pulse train sequence on B phase The method of claim 1, wherein the Z-phase generating unit The received pulse train is counted to generate a Z-phase signal when the counted value reaches the pulse train sequence, and four pulses are input or reversed in the same direction as the rotation direction at the time the Z-phase signal occurs. And a pulse is inputted, thereby returning the Z-phase signal to zero. In the signal generation method of the encoder connected to the numerical control device, necessary to obtain the position information necessary for the control of the numerical control device for transmitting a control command to the motor drive, A first step of calculating the number and direction of pulses to be generated for each control period from the high resolution position information; A second step of generating an A / B phase signal from the calculated number and direction of pulses via a pulse train generation circuit; And A third step of generating a simulated signal of the encoder by detecting a generation condition of a Z-phase pulse output every time the control axis rotates Encoder signal simulation generating method comprising a. The method of claim 5, wherein the first step Calculating a rotation angle per pulse generated by four-times multiplication, and calculating a period per pulse; Receiving the transmitted high resolution position information, calculating an absolute position angle, and calculating the number of quadrupled pulses currently reached; Calculating the number of output pulses of the next period from the outputted cumulative number of pulses; Determining whether the number of output pulses is greater than zero; Determining whether to pass the zero position of the encoder during the next control period; Setting the remaining pulse number to the zero position and initializing the accumulated pulse number; Outputting a pulse train cycle, a pulse train number, a pulse train direction, and a Z-phase pulse train number according to the initialization result Encoder signal simulation generating method comprising a. The method of claim 6, wherein the output pulse number determination step If the number of output pulses is greater than 0, the forward direction is recognized, and if the number of output pulses is less than 0, the encoder signal simulation method comprising the step of reversing. 7. The zero position determining step of the encoder If the encoder zero position does not pass during the next control period, setting the number of phase Z pulse trains to zero and updating the cumulative number of pulses newly.