SU1250248A1 - Simulator of electrocardiosignals - Google Patents

Description

I

The invention relates to medical equipment, namely, an electrocardiography, an ographic apparatus, and can be used to test and test devices that measure electrical parameters of the electrocardiogram (ECS), as well as automated electrocardiographic diagnostics equipment.

The aim of the invention is to reduce the time of formation of the type of signal.

FIG. Figure 1 shows the structures on the electrical circuit of the electrocardiographic simulator; 2 is a structural, electrical circuit of the control unit; FIG. 3 is a signal encoder circuit; FIG. A is a block diagram of a digital-analog conversion unit (DAC); Fig. 3 is a diagram of the first synchronization unit; figure 6 - scheme of the encoder interference; figure 7 - scheme of the coder oscillations of the isoline; Fig. 8 is a diagram of the contour displacement encoder; figure 9 - diagram of the second synchronization unit.

The simulator EX (FIG. 1) comprises a control unit I in series, a signal encoder 2 and a DAC unit whose output is connected to the signal output bus, the first synchronization unit 4 connected in series and the interference encoder 5 whose output is connected to the second input of the 3 D / block W, isoline oscillation encoder 6 connected between the second output of control unit 1 and the third input of DAC unit 3, isoline displacement encoder 7 connected between the third output of control unit 1 and the fourth input of DAC unit 3, and the second synchronization unit 8, which It is connected to the synchronization output bus, first to the second output of the encoder 2 signal, the second input to the third output of the encoder 2 signal, to the second input of the encoder 5 interference and to the first input of the first

block. 4 synchronization, and the third input - to the fourth output of the control unit 1, the fifth, sixth, seventh and eighth outputs of which are connected respectively to the fifth, sixth, seventh and eighth inputs of the DAC block 3, the ninth output - to the second encoder 2 signals, the tenth output - with the third inputs of the encoder 2 signals and the encoder 5 interference and with the second inputs of the encoder 6 oscillations.

502482

the isolines, the isoline offset encoder 7 and the first block 4 of their circuitry; the eleventh output — with the third input of the first synchronization unit 4.; and the 5th twelfth and thirteenth outputs, respectively, with the third and fourth inputs of the isoline offset encoder 7, the fifth input is connected to to the third input of the encoder 6 oscillations of the z-10 line, to the fourth input of the encoder 5 interference and the fourth output of the encoder 2 signal.

The control unit 1 (FIG. 2) contains

5 four generators 9 of the reference voltage, the outputs of which are connected respectively to the fifth, sixth, seventh and eighth inputs of block 3 of the D / A converter and thirty-eight elements of a 20-field 10, each of which contains a trigger 11, to the inputs of the installation of logic O and 1 of which is connected the switch 12, the direct and inverse outputs of the first trigger 25 li are connected respectively to the third and fourth inputs of the isoline bias encoder 7, the direct output of the second trigger 11 ic to the third input of the encoder 2 signals, and the forward outputs of the following

(j two triggers 11 - respectively to the first inputs of the encoder 2 signal, another following eight triggers 11 - to the second inputs of the encoder 2 signals, another following eight triggers 11 - to the third inputs of the first synchronization unit 4, to the next eight I triggers - to the first inputs coder 6 oscillations of the isoline, the next eight, triggers, -11 to the first inputs of the coder of the contour 7, and the last two triggers II to the third inputs of the second synchronization unit 8. Switches 12 are made on the P2K elements with fixation, except for the second switch (according to existing for the second trigger 11), executed on the P2K element without latching.

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The signal coder 2 (FIG. 3) contains a clock frequency generator 13 connected in series, the second output of which is connected to the first input of the second synchronization unit 8, the frequency divider 14, the first element 15, the first counter 16, the second input of which is connected to the second input divider 14 frequencies, first decoder, torus 17, trigger 18, second element

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the formation of ad a c | 11 11 dey input c; Which is subconsistent to the first output of control block I, and a permanent 5 memory device (ROM) 22, the code of which is connected to the first input of block 3 of the DAC in series. connected to the second decoder 23, the input. Which is connected to the output of the second 10 counter 20, and the first element SHS 24, the output of which is connected to the second input

trigger 18, the second output of which is connected to the second input of the first. element 15, connected in series with code comparison unit 25, the first input of which is connected to the output of the first counter 1.6, and the second input to the ninth output of control unit 1, the second element OR 26, the second input of which is connected to the second inputs of the second counter 20 and the first element OR 24 and with the tenth output of control unit 1, an inverter 27, whose input is also connected to the second input of the first counter 16, and a single pulse generator 28, the second input of which is connected to the first output of the clock frequency generator 13, to the second input of the second Element element And 19 and the fourth input of the encoder 5 interference, and the output to the second input of the encoder 5 interference. The code comparison unit 25 includes an eight-input element AND 29 to which eight circuits 30 of one bit match 30 are connected, each of which contains the element OR 31 ,. To the inputs of which are connected, respectively, the element 40 and 32 and the element OR 33 (FIG. 3).

The address generation unit 21 consists of two parallel-input two-way decoder / and can be connected and can be wired to 1.6C: F: FMH0G.

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fcb ftJi jrbifH aiS eifi has been converted to 35 psi 35 "% p1 & pg, yg f6, j third 37 and ё bertS 38 DAC, the first (reference) inputs of which are connected respectively to the fifth, sixth, seventh and eighth output I control, and the second (informational) inputs, respectively, with the outputs of encoder 2 signal, encoder 5 interference, encoder 6 oscillation contour and encoder displacement encoder 7, the output of adder 34 and analog signals connected to the signal output bus of the simulator cardiovascular signals.

The first block 4 of synchronization (.fig.5) contains a series-connected adder 39, the first input of which is connected to the eleventh one. the output of the control block I, the first register 40 and the second register 41, the first input of which is also connected to the first input of the interference encoder 5, the second input (synchronization) is connected to the third output of the encoder 2 signal, the third input (zero setting) to the third input cm (setting zero) of the first register is 40, and the output is with the second input of the adder 39, the first; an inverter 42 connected between the second inputs (synchronization) of the second register 41 and the first register 40, and a second inverter 43 connected between the third input of the encoder 2 signal and the third input of the first register 40.

Encoder 5 interference (6) contains a serially connected counter 44 and ROM 45, the output of which is connected to the second input of the block 3 of the DAC, and

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fcb ftJi jrbifH aiS eifi has been converted to 35 psi 35 "% p1 & pg, yg f6, j third 37 and ё bertS 38 DAC, the first (reference) inputs of which are connected respectively to the fifth, sixth, seventh and eighth output I control, and the second (informational) inputs, respectively, with the outputs of encoder 2 signal, encoder 5 interference, encoder 6 oscillation contour and encoder displacement encoder 7, the output of adder 34 and analog signals connected to the signal output bus of the simulator cardiovascular signals.

The first block 4 of synchronization (.fig.5) contains a series-connected adder 39, the first input of which is connected to the eleventh one. the output of the control block I, the first register 40 and the second register 41, the first input of which is also connected to the first input of the interference encoder 5, the second input (synchronization) is connected to the third output of the encoder 2 signal, the third input (zero setting) to the third input cm (setting zero) of the first register is 40, and the output is with the second input of the adder 39, the first; an inverter 42 connected between the second inputs (synchronization) of the second register 41 and the first register 40, and a second inverter 43 connected between the third input of the encoder 2 signal and the third input of the first register 40.

Encoder 5 interference (6) contains a serially connected counter 44 and ROM 45, the output of which is connected to the second input of the block 3 of the DAC, and

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the first (counting), the second (pre-recording), the third (information. It’s € 1) .. 11, .N tver; rj1y (installation zero) BefcTF

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control unit 1, the second

stroke (reverse counting) - with the fourth output of the encoder 2 signal, the third input (pre-recording) - with the first (counting) input of counter 6, the fourth input (setting zero) - with the second input (setting zero) of the meter 46 and with the third input of the curr 2 signals, and the output - with the first stroke of the counter 46.

The isoline displacement encoder 7 (Fig. 8) contains successively soy; zinnie frequency divider 49, the first element 30, the second input of which is connected to the thirteenth output of control unit 1, and the reversible counter 51, the output of which is connected to the fourth input of block 3 ZDL, and the second input (setting zero) - with the first input f (setting zero) of the frequency divider 49 and the third input of the encoder 2 signal, and the second element And 52, the output of which is connected to the third input (reverse counting) of the reversible counter

51, the first input is to the twelfth output of control unit 1 and the second input is to output and second input (pre-recording) of the frequency divider 49, the third input (of the countdown) of which is connected to the fourth input of the interference encoder 5, and the fourth (information) input - with the third output of the control unit 1.

The second synchronization unit 8 (FIG. 9) comprises an inverter 53 connected in series, the input of which is connected to the third output of encoder 2 signal, dividers 54 44jp-, the second (counting) input of which is connected to the second output of encoder 2 signal, and the switch 55, the second , the third and fourth inputs. Which are connected respectively to the second, third and fourth B1 IDs of the frequency divider 54, the fifth (control) input - to the fourth output of the control unit 1, and the output - to the output synchronization clock of the simulator

THE EX. .

The simulator EX works as follows.

Before starting work on the dial pad 10 of the block 1 controlling the paths for pressing buttons defined

P (1p (| ХУЧУТВЛГЙ 12 formed SL1DYu

teams in the form of multi-bit ones, looking at the appropriate

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form of the generated EKS (first exit, two bits);

the duration of one cardiocomplex (ninth yield, eight bits - dov);

the initial phase of the harmonic room of 50 Hz (eleventh output, eight bits); the period of the sinusoidal oscillation of the isoline (second output, eight bits);.

the slope of the linear displacement from the line (third run, eight bits);

polarity of contour displacement (twelfth and thirteenth outlets, one bit each);

pulse frequency at the output - sync bus (fourth output, two bits).

With the help of adjustable generators 19 of the reference voltage on the fifth, sixth and eighth codes of the control unit 1, the scales of digital-analog conversion of signals are set.

When the second switch button 12 is pressed, a pulse of the initial setting is formed. In the form of a voltage of logical 1 at the tenth output of the control unit 1. At that, counters 16.22, 44 and 46, frequency dividers 14, 48 and 49, registers are zeroed. 40 and 41, trigger 18, reversing: {counter 51 and generator 28 of a single pulse. When the button of the second switch 12 is released, the simulator EX-switches to the operating state.

The first pulse from the clock generator 13, after passing the pulse of the initial setup, arriving at the input of the generator 28 of a single pulse, triggers the impulse (... the third output of the coder 2 signal of the pulse of the beginning of the cardio complex, at which frequency divider 54 zeroes, is recorded in re 7 40 and 41 and the initial installation of the counter 44 is carried out.

In encoder 2, a signal is formed and arrives at its fourth output clock frequency, under the influence of which sequences of eight-bit binary codes of ordinate signals generated by various blocks of the simulator EX-S are generated.

The signal coder 2 implements a G9H @ pbc 1 cnfr @ p @ m §id§ non-bubbling

forms of the EKS with different repetition periods (with different lengths of kyrdiocomplexes). The shape of the ECS and the duration of the cardio complex are determined by the codes from the control block I, respectively, to the first and second inputs of code 2 of the signal, to the third input of which is an nocTynaet pulse of the initial setup.

The first synchronization unit 4 generates the address code of the ROM 1.5 of the interference coder 5, which defines the initial ordinate (i.e., phase) of the harmonic

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It is located during the filling of the first counter 16.

After the EX-simulator transitions to the working state, the first counter is filled with 16 clock pulses coming from the frequency divider 14, and the ordinate code of the EX-isoline is output to the first code of the coder 2 signal. When the contents of the first counter 16 reaches a predetermined value (e.g., 00000100), then

A signal simulating interference frequency 5 of the first decoder 17 appears

50 Hz, at the beginning of each cardiocomplex EX.

Interference encoder 5 generates a sequence of binary ordinate codes of a signal imitating a harmonic component of a 50 Hz interference, which is fed to the second input of the 3 DAL unit.

The isoline oscillation coder 6 forms and supplies to the third input of the DAC block a sequence of binary ordinate codes of a signal imitating sinusoidal oscillations of the EX line, the period of which is determined by an eight-bit code received at the first input of the isoline oscillator -6 from control unit 1.

The isoline displacement encoder 7 generates a sequence of binary codes of the ordinate sawtooth signal, with a given sign and slope, simulating a linear contour of the isoline, which is fed to the fourth input of the DAC unit.

The four code sequences thus obtained in block 3 of the DAC are converted to the analog signals specified in block I of control (respectively, in DAC 35-38), which are summed by adder 34 and fed to the signal board of the simulator EX.

Separate blocks of the simulator EX-function as follows.

In the 2-signal encoder, namely, ROM 22, the ordinate codes EX for several cardiocomplex forms are stored. In two cells of the ROM 22 with minimum and maximum addresses for each form EX, the isoline ordinate code is stored. The survey of THESE cells is

It is during the filling of the first counter 16.

After the EX-simulator transitions to the working state, the first counter is filled with 16 clock pulses coming from the frequency divider 14, and the ordinate code of the EX-isoline is output to the first code of the encoder 2 signals. When the contents of the first counter 16 reaches a predetermined value (e.g., 00000100), then

5 of the first decoder 17 appears

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the signal and the clocking pulses of the clock frequency generator 13 are switched to fill the second counter 20, changing the contents of which causes a sequential reading of the ordinate EX of a predetermined form from ROM 22. At reproducing-1 SRI of the second counter 20, the output of the second decoder 23 appears again switching clocking pulses for filling the first counter I6 and the ordinate code of the isolines EX. The first counter 16 is filled until its content becomes the same code arriving at the second input of the encoder 2 signal from the ninth output of the etching unit, and then the output of the cardiocomplex is formed at the output of the code comparison unit 25. This signal zeros the first counter 16 and the frequency divider 14, and prepares a single pulse generator 28 for issuing a pulse to the onset of the cardio complex on the first next clock pulse. According to the new pulse of the beginning of the cardio complex, the operation cycle of the signal coder 2 is repeated.

In the coder 6, the contour oscillations, as the counter 46 is filled, are sequentially read from the ROM 47 the ordinate codes of the sinusoidal oscillations of the contour EX. The counter 46 is filled with pulses coming from the frequency divider 48, the division factor of which is determined by the code received from the second output of the control unit .1 to the First input of the contour 6 oscillation encoder 6. The filling of the counter 46 causes the appearance at the output of the encoder 6 oscillations of the isolines of a sequence of 512 codes

ordinates forming one period of the sinusoidal oscillation of the isoline. Further, the cycle of operation of the isoline coder 6 is repeated.

The vertical displacement ordinate codes of the isolate EX-are formed at the output of the reversing counter 51 of the isoline displacement encoder 7. The up / down counter 51 is pulsed.

coming from the frequency divider 49, the division factor of which is determined by the code from the third output of the control block I to the first input of the isoline displacement encoder 7. The content of the reversible counter 51 either increases or decreases, depending on the codes received from the twelfth and thirteenth outputs of control unit 1, respectively, to the third and fourth inputs of the isoline offset encoder 7 and defining the polarity of the isoline offset. When the reversing counter 51 overflows, the value of the ordinate code of the linear displacement of the isoline changes by jumping to the minimum or maximum value, and then the operation cycle of the contour displacement encoder 7 repeats.

In encoder 5, the interference codes of the harmonic interference with a frequency of 50 Hz are successively read from the ROM 45 as the counter pulses 44 are filled with the clock pulses. The filling of the counter 44 causes the sequence of 256 ordinates to form a single harmonic period of 50 Hz at the output of the ROM 45. On the leading edge of the start of the cardio complex, the counter 44 records the code from the output of the first synchronization unit 4 to the first input of the interference encoder 5, which determines the first ordinate code of the interference signal at the output of the interference encoder 6, from which the generation of the ordinate codes of this cycle begins work. The contents of counter 44 are then incremented by one for each clocked pulse. This mode of operation continues even after the counter overflows in counter 44. A new operation cycle of the interference encoder 5 begins when the next pulse of the beginning of the cardio complex appears.

On the first front of the first ECM simulator in the working state of the pulse of the onset of the cardio complex received in the first synchronization unit 4, the first register 40 records the code from the output of the adder 39, which is the code received from the eleventh output of the control unit I to the third the input of the first block 4 synchronization. Then the contents of the first register 40 are rewritten by the falling edge of the pulse of the beginning of the cardiac complex into the second register 41, and by the next pulse of the beginning of the cardiac complex into the counter 4 of the encoder 5 interference. A new cycle of operation of the first synchronization unit 4 begins for each next pulse of the beginning of the cardio complex, on the leading edge of which the first register 40 records the code from the output g of the adder 39, which is the sum of the content, the second register 41 and the code received FROM control unit 1. Consequently, a code is generated at the output of the first synchronization unit 4, which increases by the amount of the input code (at the second input of the first synchronization unit 4) as each pulse of the beginning of the cardio complex is received.

The second synchronization unit 8 generates a sequence of sync pulses with a frequency of 2,000, 1,000, 500, and 250 Hz for synchronization. The ADC of the instrument is tested using the test signal EX, which is formed on the signal output bus of the simulator EX. The second synchronization unit 8 performs the function of a frequency divider with a variable division factor, which is defined by a code received from the fourth output of the control unit 1 to the third input of the second synchronization unit 8. As a result, sync pulses of the corresponding frequency are fed to the output bus of the synchronization of the simulator EX. .

Thus, the proposed EX simulator reproduces a test signal, which is a combination of EX elements (cardiblex) and electrocardiography-typical noise and distortion (50 Hz harmonic interference, oscillation and displacement of the eoelectric line) and also generates a sequence of synchronization pulses with the specified repetition period, with the harmonic component phase imitating the interference at a frequency of 50. Hz, changes discretely at the beginning of each repetition period of the cardiac complex by a predetermined elichinu that gives WHO-, operat1shnogo possibility of specifying in one implementation of various embodiments of the test signal superimposing noise on the cardiac cycle with a predetermined shape zleme - / |.. comrade, a sync position j I in each repetition period is fixed relative kardiokom- plex

Beginnings, which makes it possible, when using the EX-simulator to test instruments with ASch1, to take into account the component 5 of measurement error of signal parameters, I arising in the absence of ADC synchronization) due to an arbitrary position of reading points for dskretnyh samples from the beginning of the cardiocomplex I signal.

The use of the invention provides a reduction in the time spent on it with the help of a full 12 and sufficient test of electrocardiographic equipment, performing measurement and recording of diagnostic informative parameters of the FORMER.

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Compiled by E. Baluyev. Tehred 3.4FbicMapGasor Corrector M.Pojo

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Circulation 660 Subscription

VNIIPI USSR State KomiFet for Inventions and Discoveries - 113035, Moscow, F-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

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Claims (1)

ELECTROCARDIO SIGNALS SIMULATOR, comprising a control unit connected in series, a signal encoder and a digital-to-analog conversion unit, the output of which is connected to a signal output bus, characterized in that, in order to reduce the formation time of the signal type, the first synchronization unit and an interference encoder are connected in series, the output which is connected to the second input of the digital-to-analog conversion unit, an isoline oscillation encoder connected between the second output of the control unit and the third input of the unit digital-to-analog conversion, contour offset encoder included in between the third output of the control unit and the fourth input of the digital-to-analog conversion unit, and the second synchronization unit, the output of which is connected to the synchronization output bus, the first input is to the second output of the signal encoder, the second input to the third output of the signal encoder, to the second input of the interference encoder and to the first input of the first synchronization unit, and the third input - to the fourth output of the control unit, the fifth, sixth, seventh and eighth outputs of which are connected respectively to the fifth, sixth, seventh and eighth inputs of the digital-analog block th conversion ninth output - to a second input of the encoder signal desyatyy.vyhod - a third input of the encoder contour oscillation signal of the encoder and the encoder, and the interference with the second displacement encoder inputs and first contour. synchronization unit, the eleventh output with the third input of the first synchronization unit, and the twelfth and thirteenth outputs, respectively, with the third and fourth inputs of the isoline offset encoder, the fifth input of which is connected to the third input of the isoline oscillation encoder, to the fourth input of the interference encoder and to four of that output signal encoder. .SU <,.> 1250248